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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,2 +1,2 @@ | ||
| cv32a65x: | ||
| gates: 142603 | ||
| gates: 178869 |
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,82 @@ | ||
| /*======================================================================*/ | ||
| /* Proxy kernel linker script */ | ||
| /*======================================================================*/ | ||
| /* This is the linker script used when building the proxy kernel. */ | ||
|
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| /*----------------------------------------------------------------------*/ | ||
| /* Setup */ | ||
| /*----------------------------------------------------------------------*/ | ||
|
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| /* The OUTPUT_ARCH command specifies the machine architecture where the | ||
| argument is one of the names used in the BFD library. More | ||
| specifically one of the entires in bfd/cpu-mips.c */ | ||
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| OUTPUT_ARCH( "riscv" ) | ||
| ENTRY(_start) | ||
|
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| /*----------------------------------------------------------------------*/ | ||
| /* Sections */ | ||
| /*----------------------------------------------------------------------*/ | ||
|
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| SECTIONS | ||
| { | ||
|
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| /* text: test code section */ | ||
| . = 0x80000000; | ||
| _start_text = .; | ||
| .text.init : { *(.text.init) } | ||
|
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| . = ALIGN(0x1000); | ||
| .tohost : { *(.tohost) } | ||
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| . = ALIGN(0x1000); | ||
| .uvmif : { *(.uvmif) } | ||
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| . = ALIGN(0x1000); | ||
| .text : { *(.text) } | ||
| . = ALIGN(0x1000); | ||
| .text.startup : { *(.text.startup) } | ||
| . = ALIGN(0x1000); | ||
| _end_text = .; | ||
| . = ALIGN(0x1000); | ||
| .rodata : { *(.rodata*)} | ||
| . = ALIGN(0x8); | ||
| . = ALIGN(0x1000); | ||
| .page_table : { *(.page_table) } | ||
| .user_stack : { *(.user_stack) } | ||
| .kernel_data : { *(.kernel_data) } | ||
| .kernel_stack : { *(.kernel_stack) } | ||
|
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| /* data segment */ | ||
| .data : { *(.data) } | ||
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| .sdata : { | ||
| __global_pointer$ = . + 0x800; | ||
| *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) | ||
| *(.sdata .sdata.* .gnu.linkonce.s.*) | ||
| } | ||
|
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| /* bss segment */ | ||
| .sbss : { | ||
| *(.sbss .sbss.* .gnu.linkonce.sb.*) | ||
| *(.scommon) | ||
| } | ||
| .bss : { *(.bss) } | ||
|
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| /* thread-local data segment */ | ||
| .tdata : | ||
| { | ||
| _tdata_begin = .; | ||
| *(.tdata) | ||
| _tdata_end = .; | ||
| } | ||
| .tbss : | ||
| { | ||
| *(.tbss) | ||
| _tbss_end = .; | ||
| } | ||
|
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| /* End of uninitalized data segement */ | ||
| _end = .; | ||
| } | ||
|
|
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,53 @@ | ||
| spike_param_tree: | ||
| bootrom: true | ||
| bootrom_base: 65536 | ||
| bootrom_size: 4096 | ||
| dram: true | ||
| dram_base: 2147483648 | ||
| dram_size: 1073741824 | ||
| generic_core_config: false | ||
| max_steps: 200000 | ||
| max_steps_enabled: false | ||
| isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs | ||
| priv: M | ||
| core_configs: | ||
| - | ||
| isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs | ||
| extensions: cv32a60x,cvxif | ||
| boot_addr: 2147483648 | ||
| marchid_override_mask: 0xFFFFFFFF | ||
| marchid_override_value: 0x3 | ||
| misa_write_mask: 0x0 | ||
| pmpaddr0: 0 | ||
| pmpcfg0: 0 | ||
| pmpregions_max: 64 | ||
| pmpregions_writable: 8 | ||
| priv: M | ||
| status_fs_field_we: false | ||
| status_fs_field_we_enable: false | ||
| status_vs_field_we: false | ||
| status_vs_field_we_enable: false | ||
| mstatus_write_mask: 136 | ||
| mstatus_override_mask: 6144 | ||
| mie_write_mask: 0x00000880 | ||
| mie_override_mask: 0xfffff77f | ||
| mie_override_value: 0x00000000 | ||
| mip_write_mask: 0x00000000 | ||
| mip_override_mask: 0xfffff77f | ||
| mip_override_value: 0x00000000 | ||
| mtval_write_mask: 0 | ||
| tinfo_accessible: 0 | ||
| mscontext_accessible: 0 | ||
| mcontext_accessible: 0 | ||
| tdata1_accessible: 0 | ||
| tdata2_accessible: 0 | ||
| tdata3_accessible: 0 | ||
| tselect_accessible: 0 | ||
| mhartid: 0 | ||
| mvendorid_override_mask : 0xFFFFFFFF | ||
| mvendorid_override_value: 1538 | ||
| csr_counters_injection: true | ||
| interrupts_injection: true | ||
| unified_traps: true | ||
| mcycleh_implemented: false | ||
| mhpmevent31_implemented: false |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,102 @@ | ||
| // Copyright 2022 Thales DIS design services SAS | ||
| // | ||
| // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); | ||
| // you may not use this file except in compliance with the License. | ||
| // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 | ||
| // You may obtain a copy of the License at https://solderpad.org/licenses/ | ||
| // | ||
| // Original Author: Jean-Roch COULON - Thales | ||
|
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| package cva6_config_pkg; | ||
|
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| localparam CVA6ConfigXlen = 32; | ||
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| localparam CVA6ConfigRvfiTrace = 1; | ||
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| localparam CVA6ConfigAxiIdWidth = 4; // axi_pkg.sv | ||
| localparam CVA6ConfigAxiAddrWidth = 64; // axi_pkg.sv | ||
| localparam CVA6ConfigAxiDataWidth = 64; // axi_pkg.sv | ||
| localparam CVA6ConfigDataUserWidth = 32; // axi_pkg.sv | ||
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| localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ | ||
| XLEN: unsigned'(CVA6ConfigXlen), | ||
| VLEN: unsigned'(32), | ||
| FpgaEn: bit'(0), | ||
| FpgaAlteraEn: bit'(0), | ||
| TechnoCut: bit'(1), | ||
| SuperscalarEn: bit'(0), | ||
| NrCommitPorts: unsigned'(1), | ||
| AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), | ||
| AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), | ||
| AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), | ||
| AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), | ||
| MemTidWidth: unsigned'(CVA6ConfigAxiIdWidth), | ||
| NrLoadBufEntries: unsigned'(2), | ||
| RVF: bit'(0), | ||
| RVD: bit'(0), | ||
| XF16: bit'(0), | ||
| XF16ALT: bit'(0), | ||
| XF8: bit'(0), | ||
| RVA: bit'(0), | ||
| RVB: bit'(1), | ||
| RVV: bit'(0), | ||
| RVC: bit'(1), | ||
| RVH: bit'(0), | ||
| RVZCB: bit'(1), | ||
| RVZCMP: bit'(1), | ||
| XFVec: bit'(0), | ||
| CvxifEn: bit'(1), | ||
| RVZiCond: bit'(0), | ||
| RVZicntr: bit'(0), | ||
| RVZihpm: bit'(0), | ||
| NrScoreboardEntries: unsigned'(4), | ||
| PerfCounterEn: bit'(0), | ||
| MmuPresent: bit'(0), | ||
| RVS: bit'(0), | ||
| RVU: bit'(0), | ||
| HaltAddress: 64'h800, | ||
| ExceptionAddress: 64'h808, | ||
| RASDepth: unsigned'(2), | ||
| BTBEntries: unsigned'(0), | ||
| BHTEntries: unsigned'(32), | ||
| DmBaseAddress: 64'h0, | ||
| TvalEn: bit'(0), | ||
| DirectVecOnly: bit'(1), | ||
| NrPMPEntries: unsigned'(8), | ||
| PMPCfgRstVal: {64{64'h0}}, | ||
| PMPAddrRstVal: {64{64'h0}}, | ||
| PMPEntryReadOnly: 64'd0, | ||
| NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, | ||
| NrNonIdempotentRules: unsigned'(0), | ||
| NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), | ||
| NonIdempotentLength: 1024'({64'b0, 64'b0}), | ||
| NrExecuteRegionRules: unsigned'(0), | ||
| ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}), | ||
| ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}), | ||
| NrCachedRegionRules: unsigned'(1), | ||
| CachedRegionAddrBase: 1024'({64'h8000_0000}), | ||
| CachedRegionLength: 1024'({64'h40000000}), | ||
| MaxOutstandingStores: unsigned'(7), | ||
| DebugEn: bit'(0), | ||
| AxiBurstWriteEn: bit'(0), | ||
| IcacheByteSize: unsigned'(2048), | ||
| IcacheSetAssoc: unsigned'(2), | ||
| IcacheLineWidth: unsigned'(128), | ||
| DCacheType: config_pkg::HPDCACHE, | ||
| DcacheByteSize: unsigned'(2028), | ||
| DcacheSetAssoc: unsigned'(2), | ||
| DcacheLineWidth: unsigned'(128), | ||
| DataUserEn: unsigned'(1), | ||
| WtDcacheWbufDepth: int'(8), | ||
| FetchUserWidth: unsigned'(32), | ||
| FetchUserEn: unsigned'(1), | ||
| InstrTlbEntries: int'(2), | ||
| DataTlbEntries: int'(2), | ||
| UseSharedTlb: bit'(1), | ||
| SharedTlbDepth: int'(64), | ||
| NrLoadPipeRegs: int'(0), | ||
| NrStorePipeRegs: int'(0), | ||
| DcacheIdWidth: int'(1) | ||
| }; | ||
|
|
||
| endpackage |
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