Merge branch 'openhwgroup:master' into altera_opt_1

openhwgroup · Nov 12, 2024 · 5b731e7 · 5b731e7
2 parents 599a0e7 + 16f37b9
commit 5b731e7
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Showing 3 changed files with 51 additions and 40 deletions.
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -522,31 +522,37 @@ simu-gate:
     - asic-synthesis
   parallel:
     matrix:
-      - SIMU_PERIOD: ["20"]  # 50 Mhz
-        PERIOD:      ["15"]  # 66 Mhz
-        PROG_NAME:   "dhrystone"
+      - PROG_NAME:   ["dhrystone_smoke"]
   variables:
     DASHBOARD_JOB_TITLE: "Gate Level Simulation $DV_TARGET"
     DASHBOARD_JOB_DESCRIPTION: "Tests to check netlist from ASIC synthesis and power consumption over different patterns"
     DASHBOARD_SORT_INDEX: 6
     DASHBOARD_JOB_CATEGORY: "Post Synthesis"
     DV_TARGET: cv32a65x
     TARGET: $DV_TARGET
+    TOP: "cva6"
     SPIKE_TANDEM: 1
+    SIMU_PERIOD: "20"  # 50 Mhz
+    PERIOD: "15"  # 66 Mhz
   script:
     - git -C verif/core-v-verif fetch --unshallow
     - !reference [.copy_spike_artifacts]
     - echo $PERIOD
     - source ./verif/sim/setup-env.sh
-    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b ${SYNTH_SCRIPT_BRANCH}
+    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b testelf
+    - git -C ${SYNTH_SCRIPT_PATH} checkout cb92f846
     - cp -r ${SYNTH_SCRIPT_PATH}/cva6/ ../
     - git apply ${SYNTH_SCRIPT_PATH}/patches/*.patch
     - source verif/regress/install-riscv-tests.sh
-    - mv artifacts/cva6_${DV_TARGET} pd/synth/
-    - mv artifacts/cva6_${DV_TARGET}_synth.v pd/synth/
-    - mv artifacts/cva6_${DV_TARGET}_synth.sdf pd/synth/
-    - mkdir -p pd/synth/cva6_${DV_TARGET}/outputs/
-    - python3 ${SYNTH_SCRIPT_PATH}/scharm -p configs/modules/CVA6.yml --runner=True --compaign="simu-gate" --name=$PROG_NAME
+    - mv artifacts/${TOP}_${DV_TARGET} pd/synth/
+    - mv artifacts/${TOP}_${DV_TARGET}_synth.v pd/synth/
+    - mv artifacts/${TOP}_${DV_TARGET}_synth.sdf pd/synth/
+    - mkdir -p pd/synth/${TOP}_${DV_TARGET}/outputs/
+    - export DV_SIMULATORS="spike"
+    - bash verif/regress/${PROG_NAME}.sh
+    - cp verif/sim/out_*/directed_c_tests/*.o verif/sim/testelf.o
+    - python3 ${SYNTH_SCRIPT_PATH}/scharm -p configs/modules/CVA6.yml --runner=True --compaign="simu-gate" --name=testelf
+    - grep "Simulation terminated" verif/sim/out_*/*/*.log.iss
     - mv ${SYNTH_SCRIPT_PATH}/artifacts/ artifacts/artifacts_gate/
     - rm artifacts/artifacts_gate/*/build/*.fsdb
   after_script: *simu_after_script

diff --git a/.gitlab-ci/scripts/report_tandem.py b/.gitlab-ci/scripts/report_tandem.py
@@ -27,9 +27,12 @@ def main():
 
 
 def check_provided_args():
-    if sys.argv[1] is None or not isinstance(sys.argv[1], str):
+    if len(sys.argv) != 2 or not os.path.exists(sys.argv[1]):
         print("Usage : python report_tandem.py path/to/log/dir", file=sys.stderr)
-        sys.exit("No log directory provided !")
+        sys.exit("No valid log directory provided!")
+
+    if len(list(glob.iglob(sys.argv[1] + "/*.yaml"))) == 0:
+        sys.exit("No reports in log directory!")
 
 
 def add_table_legend(metrics_table, with_logs):
@@ -60,31 +63,33 @@ def fill_table(reports_dir, metrics_table, with_logs):
 
 
 def add_test_row(report_file, metrics_table, with_logs):
-    with open(report_file) as f:
-        report = yaml.safe_load(f)
-    mismatches_count = str(report["mismatches_count"]) if "mismatches_count" in report else "Not found"
-
-    row = [report["target"], report["isa"], report["test"], report["testlist"], report["simulator"], mismatches_count]
-
-    if with_logs:
-        logs_path = "logs/" + os.environ.get("CI_JOB_ID") + "/artifacts/logs/"
-        output_log = logs_path + "logfile.log.head"
-        log_prefix = logs_path + report['test'] + "_" + str(report["iteration"]) + "." + report["target"] \
-            if "iteration" in report else logs_path + report['test'] + "." + report["target"]
-        tb_log = log_prefix + '.log.iss.head'
-        disassembly = log_prefix + '.log.csv.head'
-
-        row.append(output_log)
-        row.append(tb_log)
-        row.append(disassembly)
-
-    if report["exit_cause"] == "SUCCESS" and report["exit_code"] == 0:
-        metrics_table.add_pass(*row)
-        return 1
-
-    metrics_table.add_fail(*row)
-    return 0
-
+    try:
+        with open(report_file) as f:
+            report = yaml.safe_load(f)
+        mismatches_count = str(report["mismatches_count"]) if "mismatches_count" in report else "Not found"
+
+        row = [report["target"], report["isa"], report["test"], report["testlist"], report["simulator"], mismatches_count]
+
+        if with_logs:
+            logs_path = "logs/" + os.environ.get("CI_JOB_ID") + "/artifacts/logs/"
+            output_log = logs_path + "logfile.log.head"
+            log_prefix = logs_path + report['test'] + "_" + str(report["iteration"]) + "." + report["target"] \
+                if "iteration" in report else logs_path + report['test'] + "." + report["target"]
+            tb_log = log_prefix + '.log.iss.head'
+            disassembly = log_prefix + '.log.csv.head'
+
+            row.append(output_log)
+            row.append(tb_log)
+            row.append(disassembly)
+
+        if report["exit_cause"] == "SUCCESS" and report["exit_code"] == 0:
+            metrics_table.add_pass(*row)
+            return 1
+
+        metrics_table.add_fail(*row)
+        return 0
+    except (TypeError, KeyError):
+        sys.exit("Invalid yaml file in log directory! Is the log directory correct?")
 
 def report(metrics_table, passed_test_count, total_test_count):
     report = report_builder.Report(f'{passed_test_count}/{total_test_count}')

diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv
@@ -161,9 +161,9 @@ module csr_regfile
     // TO_BE_COMPLETED - PERF_COUNTERS
     output logic perf_we_o,
     // PMP configuration containing pmpcfg for max 64 PMPs - ACC_DISPATCHER
-    output riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries-1:0] pmpcfg_o,
+    output riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg_o,
     // PMP addresses - ACC_DISPATCHER
-    output logic [CVA6Cfg.NrPMPEntries-1:0][CVA6Cfg.PLEN-3:0] pmpaddr_o,
+    output logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr_o,
     // TO_BE_COMPLETED - PERF_COUNTERS
     output logic [31:0] mcountinhibit_o,
     // RVFI
@@ -291,8 +291,8 @@ module csr_regfile
   | (CVA6Cfg.XLEN'(CVA6Cfg.NSX) << 23)  // X - Non-standard extensions present
   | ((CVA6Cfg.XLEN == 64 ? 2 : 1) << CVA6Cfg.XLEN - 2);  // MXL
 
-  assign pmpcfg_o  = pmpcfg_q[CVA6Cfg.NrPMPEntries-1:0];
-  assign pmpaddr_o = pmpaddr_q[CVA6Cfg.NrPMPEntries-1:0];
+  assign pmpcfg_o  = pmpcfg_q[(CVA6Cfg.NrPMPEntries>0?CVA6Cfg.NrPMPEntries-1 : 0):0];
+  assign pmpaddr_o = pmpaddr_q[(CVA6Cfg.NrPMPEntries>0?CVA6Cfg.NrPMPEntries-1 : 0):0];
 
   riscv::fcsr_t fcsr_q, fcsr_d;
   // ----------------