diff --git a/.gitlab-ci/scripts/report_benchmark.py b/.gitlab-ci/scripts/report_benchmark.py
index 7f781c8046..cec2c10fdc 100644
--- a/.gitlab-ci/scripts/report_benchmark.py
+++ b/.gitlab-ci/scripts/report_benchmark.py
@@ -19,12 +19,12 @@
 # Keep it up-to-date with compiler version and core performance improvements
 # Will fail if the number of cycles is different from this one
 valid_cycles = {
-    "dhrystone_dual": 20199,
-    "dhrystone_single": 25019,
-    "coremark_dual": 1017451,
-    "coremark_single": 1308656,
-    "dhrystone_cv32a65x": 32566,
-    "dhrystone_cv32a60x": 39994,
+    "dhrystone_dual": 18935,
+    "dhrystone_single": 24127,
+    "coremark_dual": 1001191,
+    "coremark_single": 1300030,
+    "dhrystone_cv32a65x": 31976,
+    "dhrystone_cv32a60x": 39449,
 }
 
 for arg in sys.argv[1:]:
diff --git a/verif/core-v-verif b/verif/core-v-verif
index bfbbd19c13..b7f57c145c 160000
--- a/verif/core-v-verif
+++ b/verif/core-v-verif
@@ -1 +1 @@
-Subproject commit bfbbd19c13aaf24b724eb32e5b5ac7b0cb951c54
+Subproject commit b7f57c145c0f2de2115c75267d9124faab071d03
diff --git a/verif/env/uvme/uvme_cva6_cfg.sv b/verif/env/uvme/uvme_cva6_cfg.sv
index dfcbbe7932..d3cce1d48f 100644
--- a/verif/env/uvme/uvme_cva6_cfg.sv
+++ b/verif/env/uvme/uvme_cva6_cfg.sv
@@ -181,7 +181,8 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
       isacov_cfg.reg_hazards_enabled        == 1;
       rvfi_cfg.nret                         == RTLCVA6Cfg.NrCommitPorts;
       unified_traps                         == 0;
-      axi_cfg.rand_channel_delay_enabled    == 0;
+      axi_cfg.zero_delay_mode               == 1;
+      axi_cfg.disable_trs_randomization     == 1;
 
       if (is_active == UVM_ACTIVE) {
          clknrst_cfg.is_active        == UVM_ACTIVE;