hyperbus.core

CAPI=2:
name : ::hyperbus:1.0
description: "Hyperbus Memory Controller"

filesets:
    rtl:
        files:
            - rtl/verilog/ioddr.v
            - rtl/verilog/hyperbus.v
            - rtl/verilog/hyperbus_fifo.v
            - rtl/verilog/hyperbus_wishbone.v
        file_type: verilogSource
        depend:
            - async_fifo

    constraints:
        files:
            - data/hyperbus.sdc: {file_type: SDC}

    tb:
        files:
            - tb/hyperbus_tb.v
            - tb/hyperbus_fifo_tb.v
        file_type: verilogSource

    tb_verilator:
        files:
            - tb/hyperbus_test.cpp
        file_type: cppSource

    tb_verilator_fifo:
        files:
            - tb/hyperbus_fifo_test.cpp
        file_type: cppSource

targets:
    sim:
        default_tool: verilator
        filesets:
            - rtl
            - tb
            - tb_verilator
        toplevel: [hyperbus_test_top]
        tools:
            verilator:
                verilator_options : [--trace, -Wno-WIDTH, -DEXCLUDE_ALTDDIO]
    sim_fifo:
        default_tool: verilator
        filesets:
            - rtl
            - tb
            - tb_verilator_fifo
        toplevel: [hyperbus_fifo_test_top]
        tools:
            verilator:
                verilator_options : [--trace, -Wno-WIDTH, -DEXCLUDE_ALTDDIO]
    default: &base
        filesets: [rtl, constraints]


#provider:
#    name: github
#    user: wtfuzz
#    repo: hyperbus