[Darjeeling] Instantiate Darjeeling

hw/ip/dma/rtl/dma.sv

@@ -426,7 +426,7 @@ module dma
   );
 
   // The SHA engine requires the message length in bits
-  logic [127:0] sha2_message_len_bits;
+  logic [63:0] sha2_message_len_bits;
   assign sha2_message_len_bits = reg2hw.total_data_size.q << 3;
 
   // Translate the DMA opcode to the SHA2 digest mode

hw/ip/keymgr/rtl/keymgr.sv

@@ -88,6 +88,8 @@ module keymgr
   import lc_ctrl_pkg::lc_tx_test_true_strict;
   import lc_ctrl_pkg::lc_tx_t;
 
+  localparam int unsigned NumRomDigestInputs = 1;
+
   /////////////////////////////////////
   // Anchor incoming seeds and constants
   /////////////////////////////////////
@@ -507,7 +509,8 @@ module keymgr
   // SEC_CM: CONSTANTS.CONSISTENCY
   // SEC_CM: INTERSIG.CONSISTENCY
   keymgr_input_checks #(
-    .KmacEnMasking(KmacEnMasking)
+    .KmacEnMasking(KmacEnMasking),
+    .NumRomDigestInputs(NumRomDigestInputs)
   ) u_checks (
     .rom_digest_i,
     .cur_max_key_version_i(cur_max_key_version),

hw/ip/keymgr/rtl/keymgr_input_checks.sv

@@ -9,9 +9,10 @@
 
 // We should also check for input validity
 module keymgr_input_checks import keymgr_pkg::*; #(
-  parameter bit KmacEnMasking = 1'b1
+  parameter bit          KmacEnMasking      = 1'b1,
+  parameter int unsigned NumRomDigestInputs = 1
 ) (
-  input rom_ctrl_pkg::keymgr_data_t rom_digest_i,
+  input rom_ctrl_pkg::keymgr_data_t [NumRomDigestInputs-1:0] rom_digest_i,
   input [KeyVersionWidth-1:0] cur_max_key_version_i,
   input hw_key_req_t key_i,
   input [31:0] key_version_i,
@@ -97,8 +98,11 @@ module keymgr_input_checks import keymgr_pkg::*; #(
 
   assign key_vld_o = &key_chk;
 
-  // rom digest check
-  assign rom_digest_vld_o = rom_digest_i.valid &
-                            valid_chk(MaxWidth'(rom_digest_i.data));
+  always_comb begin
+    rom_digest_vld_o = 1'b1;
+    for (int k = 0; k < NumRomDigestInputs; k++) begin
+      rom_digest_vld_o &= rom_digest_i[k].valid && valid_chk(MaxWidth'(rom_digest_i[k].data));
+    end
+  end
 
 endmodule // keymgr_input_checks

hw/ip/keymgr_dpe/rtl/keymgr_dpe.sv

@@ -447,6 +447,7 @@ module keymgr_dpe
   // Advance to creator_root_key
   // The values coming from otp_ctrl / lc_ctrl are treat as quasi-static for CDC purposes
   logic [KeyWidth-1:0] creator_seed;
+  logic unused_creator_seed;
   assign unused_creator_seed = ^{otp_key_i.creator_seed_valid};
   assign creator_seed = otp_key_i.creator_seed;
 
@@ -500,7 +501,8 @@ module keymgr_dpe
   // SEC_CM: CONSTANTS.CONSISTENCY
   // SEC_CM: INTERSIG.CONSISTENCY
   keymgr_input_checks #(
-    .KmacEnMasking(KmacEnMasking)
+    .KmacEnMasking(KmacEnMasking),
+    .NumRomDigestInputs(NumRomDigestInputs)
   ) u_checks (
     .rom_digest_i,
     // In keymgr_dpe, key version comparison is handled by the ctrl logic.

hw/ip/prim/lint/prim_ram_1r1w.waiver

@@ -6,3 +6,6 @@
 
 waive -rules {STAR_PORT_CONN_USE} -location {prim_ram_1r1w.sv} -regexp {.*wild card port connection encountered on instance.*} \
       -comment "Generated prims may have wildcard connections."
+
+waive -rules {HIER_BRANCH_NOT_READ} -location {prim_ram_1r1w_async_adv.sv} -regexp {Net 'rst_a_ni' is not read from in module 'prim_ram_1r1w_async_adv} \
+      -comment "rst_a_ni is only used in assertions in certain confgurations."

hw/ip/rv_dm/rtl/rv_dm.sv

@@ -115,7 +115,7 @@ module rv_dm
   tlul_pkg::tl_d2h_t mem_tl_win_d2h;
   rv_dm_reg_pkg::rv_dm_regs_reg2hw_t regs_reg2hw;
   logic regs_intg_error, rom_intg_error, dmi_intg_error, dbg_intg_error;
-  logic sba_gate_intg_error, rom_gate_intg_error, dmi_gate_intg_error;
+  logic sba_gate_intg_error, rom_gate_intg_error;
 
   rv_dm_regs_reg_top u_reg_regs (
     .clk_i,
@@ -136,7 +136,7 @@ module rv_dm
   logic [NumAlerts-1:0] alert_test, alerts;
 
   assign alerts[0] = regs_intg_error | rom_intg_error | dmi_intg_error | dbg_intg_error |
-                     sba_gate_intg_error | rom_gate_intg_error | dmi_gate_intg_error;
+                     sba_gate_intg_error | rom_gate_intg_error;
 
   assign alert_test = {
     regs_reg2hw.alert_test.q &
@@ -481,8 +481,10 @@ module rv_dm
     assign dbg_tl_d_o = tlul_pkg::TL_D2H_DEFAULT;
 `endif
 
-    // Tied-off signals from the JTAG interface
+    // Tied-off signals from the JTAG interface and read unsed signals
     assign jtag_o = '0;
+    logic unused_signals;
+    assign unused_signals = ^{jtag_i, scan_rst_ni, pinmux_hw_debug_en_i};
   end else begin : gen_jtag_gating
     // Gating of JTAG signals
     jtag_pkg::jtag_req_t jtag_in_int;
@@ -573,7 +575,6 @@ module rv_dm
     // Tied-off and ignore signals from the DMI interface
     assign dmi_intg_error      = 1'b0;
     assign dbg_intg_error      = 1'b0;
-    assign dmi_gate_intg_error = 1'b0;
     assign dbg_tl_d_o          = tlul_pkg::TL_D2H_DEFAULT;
 
     logic unused_signals;

hw/ip_templates/pinmux/data/pinmux.hjson.tpl

@@ -57,12 +57,15 @@
     { name: "pin_wkup_req",
       desc: "pin wake request"
     },
+  % if enable_usb_wakeup:
     { name: "usb_wkup_req",
       desc: "usb wake request"
     },
+  % endif
   ],
 
   inter_signal_list: [
+  % if enable_strap_sampling:
     // Life cycle inputs
     { struct:  "lc_tx"
       type:    "uni"
@@ -170,6 +173,7 @@
                ''',
       default: "'0"
     }
+  % endif
     // Define pwr mgr <-> pinmux signals
     { struct:  "logic",
       type:    "uni",
@@ -181,6 +185,7 @@
                ''',
       default: "1'b0"
     },
+  % if enable_strap_sampling:
     { struct:  "logic",
       type:    "uni",
       name:    "strap_en",
@@ -203,6 +208,7 @@
                ''',
       default: "1'b0"
     },
+  % endif
     { struct:  "logic",
       type:    "uni",
       name:    "pin_wkup_req",
@@ -213,6 +219,7 @@
                ''',
       default: "1'b0"
     },
+  % if enable_usb_wakeup:
     { name:    "usbdev_dppullup_en",
       type:    "uni",
       act:     "rcv",
@@ -329,9 +336,11 @@
       width:   1,
       default: "1'b0"
     },
+  % endif
   ]
 
   param_list: [
+  % if enable_strap_sampling:
     // Secure parameters
     { name:    "SecVolatileRawUnlockEn",
       type:    "bit",
@@ -347,6 +356,7 @@
       local:   "false",
       expose:  "true"
     },
+  % endif
     { name: "NMioPeriphIn",
       desc: "Number of muxed peripheral inputs",
       type: "int",
@@ -399,6 +409,7 @@
     { name: "BUS.INTEGRITY",
       desc: "End-to-end bus integrity scheme."
     }
+  % if enable_strap_sampling:
     { name: "LC_DFT_EN.INTERSIG.MUBI",
       desc: "The life cycle DFT enable signal is multibit encoded."
     }
@@ -425,6 +436,7 @@
                the DFT TAP can only be selected when LC_DFT_EN is asserted.
             '''
     }
+  % endif
   ]
 
   registers: [

hw/ip_templates/pinmux/data/pinmux_sec_cm_testplan.hjson → hw/ip_templates/pinmux/data/pinmux_sec_cm_testplan.hjson.tpl

@@ -29,6 +29,7 @@
       stage: V2S
       tests: []
     }
+  % if enable_strap_sampling:
     {
       name: sec_cm_lc_dft_en_intersig_mubi
       desc: "Verify the countermeasure(s) LC_DFT_EN.INTERSIG.MUBI."
@@ -65,5 +66,6 @@
       stage: V2S
       tests: []
     }
+  % endif
   ]
 }

hw/ip_templates/pinmux/lint/pinmux.waiver → hw/ip_templates/pinmux/lint/pinmux.waiver.tpl

@@ -4,39 +4,44 @@
 #
 # waiver file for pinmux
 
-waive -rules NOT_READ -location {pinmux_reg_top.sv} -regexp {.*reg_wdata.*} \
+waive -rules NOT_READ -location {pinmux_reg_top.sv} -regexp {.*reg_wdata.*} ${"\\"}
       -comment "Upper bits of reg_wdata are not read"
 
-waive -rules HIER_NET_NOT_READ -location {pinmux_reg_top.sv} -regexp {.*reg_wdata.*} \
+waive -rules HIER_NET_NOT_READ -location {pinmux_reg_top.sv} -regexp {.*reg_wdata.*} ${"\\"}
       -comment "Upper bits of reg_wdata are not read"
 
-waive -rules VAR_INDEX_RANGE -location {pinmux.sv} -regexp {.*maximum value.*} \
+waive -rules VAR_INDEX_RANGE -location {pinmux.sv} -regexp {.*maximum value.*} ${"\\"}
       -comment "Indexed arrays may not be fully populated."
+% if enable_strap_sampling:
 
-waive -rules RESET_USE -location {pinmux_strap_sampling.sv} -regexp {'rst_ni' is connected to 'prim_clock_mux2' port 'clk1_i
-', and used as an asynchronous reset or set at pinmux_strap_sampling} \
+waive -rules RESET_USE -location {pinmux_strap_sampling.sv} -regexp {'rst_ni' is connected to 'prim_clock_mux2' port 'clk1_i', and used as an asynchronous reset or set at pinmux_strap_sampling} ${"\\"}
       -comment "This is a clock mux for DFT."
 
-waive -rules RESET_MUX -location {pinmux_strap_sampling.sv} -regexp {Asynchronous reset 'rst_ni' reaches a multiplexer here, used as a reset at pinmux_strap_sampling} \
+waive -rules RESET_MUX -location {pinmux_strap_sampling.sv} -regexp {Asynchronous reset 'rst_ni' reaches a multiplexer here, used as a reset at pinmux_strap_sampling} ${"\\"}
       -comment "This is a clock mux for DFT."
 
-waive -rules {CLOCK_DRIVER CLOCK_MUX} -location {pinmux_strap_sampling.sv} -regexp {'(lc|rv)_jtag_req.tck' is driven( by a multiplexer)? here,( and)? used as a clock 'tck_i' at dmi_jtag_tap.sv} \
+waive -rules {CLOCK_DRIVER CLOCK_MUX} -location {pinmux_strap_sampling.sv} -regexp {'(lc|rv)_jtag_req.tck' is driven( by a multiplexer)? here,( and)? used as a clock 'tck_i' at dmi_jtag_tap.sv} ${"\\"}
       -comment "These signals are muxed using the JTAG Selection Mux."
 
-waive -rules CLOCK_MUX -location {pinmux_strap_sampling.sv pinmux.sv} -regexp {Clock '(in_padring_i\[38\]|mio_in_i\[38\]|jtag_req.tck)' reaches a multiplexer here, used as a clock 'tck_i' at dmi_jtag_tap.sv} \
+waive -rules CLOCK_MUX -location {pinmux_strap_sampling.sv pinmux.sv} -regexp {Clock '(in_padring_i\[38\]|mio_in_i\[38\]|jtag_req.tck)' reaches a multiplexer here, used as a clock 'tck_i' at dmi_jtag_tap.sv} ${"\\"}
       -comment "The 'mio_in_i[TckPadIdx]' input signal is connected to 'jtag_req.tck' which eventually feeds into the JTAG Selection Mux."
+% else:
 
-waive -rules CLOCK_DRIVER -location {pinmux.sv} -regexp {'mio_attr\[28\].pull_select' is driven here, and used as a clock} \
+waive -rules CLOCK_MUX -location {pinmux.sv} -regexp {Clock '(in_padring_i\[38\]|mio_in_i\[38\]|jtag_req.tck)' reaches a multiplexer here, used as a clock 'tck_i' at dmi_jtag_tap.sv} ${"\\"}
+      -comment "The 'mio_in_i[TckPadIdx]' input signal is connected to 'jtag_req.tck' which eventually feeds into the JTAG Selection Mux."
+% endif
+
+waive -rules CLOCK_DRIVER -location {pinmux.sv} -regexp {'mio_attr\[28\].pull_select' is driven here, and used as a clock} ${"\\"}
       -comment "'MioPadIoc6' at index 28 may also serve as an external clock input. The 'pull_select' signal impacts the actual value obtained from the pad simulation model."
 
-waive -rules CLOCK_USE -location {pinmux.sv} -regexp {'hw2reg.mio_pad_attr\[28\].pull_select.d' is connected to 'pinmux_reg_top' port 'hw2reg.mio_pad_attr\[28\].pull_select.d', and used as a clock} \
+waive -rules CLOCK_USE -location {pinmux.sv} -regexp {'hw2reg.mio_pad_attr\[28\].pull_select.d' is connected to 'pinmux_reg_top' port 'hw2reg.mio_pad_attr\[28\].pull_select.d', and used as a clock} ${"\\"}
       -comment "'MioPadIoc6' at index 28 may also serve as an external clock input. The 'pull_select' signal impacts the actual value obtained from the pad simulation model."
 
-waive -rules CLOCK_USE -location {pinmux.sv} -regexp {'(dio_wkup_mux\[12\]|dio_wkup_mux\[13\]|mio_wkup_mux\[40\])' is used for some other purpose, and as clock} \
+waive -rules CLOCK_USE -location {pinmux.sv} -regexp {'(dio_wkup_mux\[12\]|dio_wkup_mux\[13\]|mio_wkup_mux\[40\])' is used for some other purpose, and as clock} ${"\\"}
       -comment "The wakeup detectors can be configured to observe any MIO / DIO pins. 'DioSpiDeviceSck' (index 12) is the spi_device clock, 'DioSpiDeviceCsb' (index 13) is the spi_device chip select (used as a clock for detecting toggles inside spi_device), and 'Dft0PadIdx' (index 40) controls the first TAP strap and thus the TAP selection mux driving the JTAG clocks."
 
-waive -rules CLOCK_MUX -location {pinmux.sv} -regexp {Clock 'dio_in_i\[12\]' reaches a multiplexer here, used as a clock 'clk_i'} \
+waive -rules CLOCK_MUX -location {pinmux.sv} -regexp {Clock 'dio_in_i\[12\]' reaches a multiplexer here, used as a clock 'clk_i'} ${"\\"}
       -comment "This mux is required to filter designated scan clock inputs (e.g. 'DioSpiDeviceSck' at index 12) from wakeup detector inputs"
 
-waive -rules RESET_ONLY -location {pinmux.sv} -regexp {'mio_pad_attr_q\[0\]' is asynchronously reset but has no other assignments in this block} \
+waive -rules RESET_ONLY -location {pinmux.sv} -regexp {'mio_pad_attr_q\[0\]' is asynchronously reset but has no other assignments in this block} ${"\\"}
       -comment "This error can safely be ignored: The signal is obviously driven further down in the very same block, changing the TargetCfg.tap_strap0_idx value to a non-zero value (which it actually is in the Earlgrey top level) makes the error go away."

hw/ip_templates/pinmux/pinmux.core.tpl

@@ -28,7 +28,9 @@ filesets:
       - rtl/pinmux_wkup.sv
       - rtl/pinmux_jtag_buf.sv
       - rtl/pinmux_jtag_breakout.sv
+    % if enable_strap_sampling:
       - rtl/pinmux_strap_sampling.sv
+    % endif
       - rtl/pinmux.sv
     file_type: systemVerilogSource
 

hw/ip_templates/pinmux/rtl/pinmux.sv.tpl

@@ -15,8 +15,10 @@ module pinmux
   // Taget-specific pinmux configuration passed down from the
   // target-specific top-level.
   parameter target_cfg_t TargetCfg = DefaultTargetCfg,
-  parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
+  parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}${"," if enable_strap_sampling else ""}
+% if enable_strap_sampling:
   parameter bit SecVolatileRawUnlockEn = 0
+% endif
 ) (
   input                            clk_i,
   input                            rst_ni,
@@ -298,6 +300,10 @@ module pinmux
     assign hw2reg.mio_pad_attr[k].invert.d         = mio_attr[k].invert;
   end
 
+  // Local versions of the input signals
+  logic [NMioPads-1:0] mio_out, mio_oe, mio_in;
+  logic [NDioPads-1:0] dio_out, dio_oe, dio_in;
+
 % if enable_strap_sampling:
 
   //////////////////////////
@@ -338,10 +344,6 @@ module pinmux
     assign strap_en = strap_en_i;
   end
 
-  // Local versions of the input signals
-  logic [NMioPads-1:0] mio_out, mio_oe, mio_in;
-  logic [NDioPads-1:0] dio_out, dio_oe, dio_in;
-
   // This module contains the strap sampling and JTAG mux.
   // Affected inputs are intercepted/tapped before they go to the pinmux
   // matrix. Likewise, affected outputs are intercepted/tapped after the
@@ -390,7 +392,7 @@ module pinmux
   // Just pass through these signals.
   assign { dio_out_o,  mio_out_o  }  = { dio_out,  mio_out  };
   assign { dio_oe_o ,  mio_oe_o   }  = { dio_oe,   mio_oe   };
-  assign { dio_in,     mio_i      }  = { dio_in_i, mio_in_i };
+  assign { dio_in,     mio_in     }  = { dio_in_i, mio_in_i };
   assign { dio_attr_o, mio_attr_o }  = { dio_attr, mio_attr };
 % endif
 % if enable_usb_wakeup: