diff --git a/hw/ip/dma/data/dma.hjson b/hw/ip/dma/data/dma.hjson index 960fc8bbaa4c02..9d4e3f6088db8e 100644 --- a/hw/ip/dma/data/dma.hjson +++ b/hw/ip/dma/data/dma.hjson @@ -470,35 +470,7 @@ No explicit clearing necessary. ''' } - { bits: "5" - name: "memory_buffer_auto_increment_enable" - resval: 0x0 - desc: ''' - Used in conjunction with the hardware handshake mode of operation. - Auto Increments the memory buffer address register by data size to point to the next memory buffer address. - Generate a warning (assert interrupt) if the auto-incremented address reaches close to the value set in limit address register to prevent destination buffer overflow. - Enables firmware to take appropriate action prior to reaching the limit. - ''' - } - { bits: "6" - name: "fifo_auto_increment_enable" - resval: 0x0 - desc: ''' - Used in conjunction with the hardware handshake mode of operation. - If set, reads/writes from/to incremental addresses for FIFO data accesses within each chunk, resetting to the initial value at the beginning of each new chunk. - Else uses the same address for all transactions. - ''' - } - { bits: "7" - name: "data_direction" - resval: 0x0 - desc: ''' - Used in conjunction with the hardware handshake enable. - 0: Receive data from LSIO FIFO to memory buffer. - 1: Send data from memory buffer to LSIO FIFO. - ''' - } - { bits: "8" + { bits: "9" name: "initial_transfer" resval: 0x0 hwaccess: "hrw" @@ -537,6 +509,58 @@ // tests are not aware of. tags: ["excl:CsrAllTests:CsrExclWrite"] } + { + name: "SRC_CONTROL" + desc: "Defines the addressing behavior of the DMA for the source address." + swaccess: "rw" + hwaccess: "hro" + regwen: "CFG_REGWEN" + fields: [ + { bits: 0 + name: "increment" + resval: 0x0 + desc: ''' + Defines the increment behavior after every DMA read. + When 0: Source address is not changed. + All reads are done from the same address. + When 1: Source address is incremented by transfer_width after each read. + ''' + } + { bits: "1" + name: "wrap" + resval: 0x0 + desc: ''' + When 1: Source address wrapped back to the starting address when finishing a chunk. + ''' + } + ] + } + { + name: "DST_CONTROL" + desc: "Defines the addressing behavior of the DMA for the destination address." + swaccess: "rw" + hwaccess: "hro" + regwen: "CFG_REGWEN" + fields: [ + { bits: "0" + name: "increment" + resval: 0x0 + desc: ''' + Defines the increment behavior after every DMA write. + When 0: Destination address is not changed. + All writes are done to the same address. + When 1: Destintation address is incremented by transfer_width after each write. + ''' + } + { bits: "1" + name: "wrap" + resval: 0x0 + desc: ''' + When 1: Destination address wrapped back to the starting address when finishing a chunk. + ''' + } + ] + } { name: "STATUS" desc: "Status indication for DMA data movement." swaccess: "rw1c" @@ -736,7 +760,7 @@ ] } } - { skipto: "0x11C" } + { skipto: "0x124" } { multireg: { name: "INTR_SRC_WR_VAL" desc: "Write value for interrupt clearing write." diff --git a/hw/ip/dma/doc/registers.md b/hw/ip/dma/doc/registers.md index 5db59c41c61bb2..dee68d6e4a68b8 100644 --- a/hw/ip/dma/doc/registers.md +++ b/hw/ip/dma/doc/registers.md @@ -23,49 +23,51 @@ | dma.[`CHUNK_DATA_SIZE`](#chunk_data_size) | 0x3c | 4 | Number of bytes to be transferred in response to each interrupt/firmware request. | | dma.[`TRANSFER_WIDTH`](#transfer_width) | 0x40 | 4 | Denotes the width of each transaction that the DMA shall issue. | | dma.[`CONTROL`](#control) | 0x44 | 4 | Control register for DMA data movement. | -| dma.[`STATUS`](#status) | 0x48 | 4 | Status indication for DMA data movement. | -| dma.[`ERROR_CODE`](#error_code) | 0x4c | 4 | Denotes the source of the operational error. | -| dma.[`SHA2_DIGEST_0`](#sha2_digest) | 0x50 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_1`](#sha2_digest) | 0x54 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_2`](#sha2_digest) | 0x58 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_3`](#sha2_digest) | 0x5c | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_4`](#sha2_digest) | 0x60 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_5`](#sha2_digest) | 0x64 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_6`](#sha2_digest) | 0x68 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_7`](#sha2_digest) | 0x6c | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_8`](#sha2_digest) | 0x70 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_9`](#sha2_digest) | 0x74 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_10`](#sha2_digest) | 0x78 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_11`](#sha2_digest) | 0x7c | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_12`](#sha2_digest) | 0x80 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_13`](#sha2_digest) | 0x84 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_14`](#sha2_digest) | 0x88 | 4 | Digest register for the inline hashing operation. | -| dma.[`SHA2_DIGEST_15`](#sha2_digest) | 0x8c | 4 | Digest register for the inline hashing operation. | -| dma.[`HANDSHAKE_INTR_ENABLE`](#handshake_intr_enable) | 0x90 | 4 | Enable bits for incoming handshake interrupt wires. | -| dma.[`CLEAR_INTR_SRC`](#clear_intr_src) | 0x94 | 4 | Valid bits for which interrupt sources need clearing. | -| dma.[`CLEAR_INTR_BUS`](#clear_intr_bus) | 0x98 | 4 | Bus selection bit where the clearing command should be performed." | -| dma.[`INTR_SRC_ADDR_0`](#intr_src_addr) | 0x9c | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_1`](#intr_src_addr) | 0xa0 | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_2`](#intr_src_addr) | 0xa4 | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_3`](#intr_src_addr) | 0xa8 | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_4`](#intr_src_addr) | 0xac | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_5`](#intr_src_addr) | 0xb0 | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_6`](#intr_src_addr) | 0xb4 | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_7`](#intr_src_addr) | 0xb8 | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_8`](#intr_src_addr) | 0xbc | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_9`](#intr_src_addr) | 0xc0 | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_ADDR_10`](#intr_src_addr) | 0xc4 | 4 | Destination address for interrupt source clearing write. | -| dma.[`INTR_SRC_WR_VAL_0`](#intr_src_wr_val) | 0x11c | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_1`](#intr_src_wr_val) | 0x120 | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_2`](#intr_src_wr_val) | 0x124 | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_3`](#intr_src_wr_val) | 0x128 | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_4`](#intr_src_wr_val) | 0x12c | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_5`](#intr_src_wr_val) | 0x130 | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_6`](#intr_src_wr_val) | 0x134 | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_7`](#intr_src_wr_val) | 0x138 | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_8`](#intr_src_wr_val) | 0x13c | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_9`](#intr_src_wr_val) | 0x140 | 4 | Write value for interrupt clearing write. | -| dma.[`INTR_SRC_WR_VAL_10`](#intr_src_wr_val) | 0x144 | 4 | Write value for interrupt clearing write. | +| dma.[`SRC_CONTROL`](#src_control) | 0x48 | 4 | Defines the addressing behavior of the DMA for the source address. | +| dma.[`DST_CONTROL`](#dst_control) | 0x4c | 4 | Defines the addressing behavior of the DMA for the destination address. | +| dma.[`STATUS`](#status) | 0x50 | 4 | Status indication for DMA data movement. | +| dma.[`ERROR_CODE`](#error_code) | 0x54 | 4 | Denotes the source of the operational error. | +| dma.[`SHA2_DIGEST_0`](#sha2_digest) | 0x58 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_1`](#sha2_digest) | 0x5c | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_2`](#sha2_digest) | 0x60 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_3`](#sha2_digest) | 0x64 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_4`](#sha2_digest) | 0x68 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_5`](#sha2_digest) | 0x6c | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_6`](#sha2_digest) | 0x70 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_7`](#sha2_digest) | 0x74 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_8`](#sha2_digest) | 0x78 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_9`](#sha2_digest) | 0x7c | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_10`](#sha2_digest) | 0x80 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_11`](#sha2_digest) | 0x84 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_12`](#sha2_digest) | 0x88 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_13`](#sha2_digest) | 0x8c | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_14`](#sha2_digest) | 0x90 | 4 | Digest register for the inline hashing operation. | +| dma.[`SHA2_DIGEST_15`](#sha2_digest) | 0x94 | 4 | Digest register for the inline hashing operation. | +| dma.[`HANDSHAKE_INTR_ENABLE`](#handshake_intr_enable) | 0x98 | 4 | Enable bits for incoming handshake interrupt wires. | +| dma.[`CLEAR_INTR_SRC`](#clear_intr_src) | 0x9c | 4 | Valid bits for which interrupt sources need clearing. | +| dma.[`CLEAR_INTR_BUS`](#clear_intr_bus) | 0xa0 | 4 | Bus selection bit where the clearing command should be performed." | +| dma.[`INTR_SRC_ADDR_0`](#intr_src_addr) | 0xa4 | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_1`](#intr_src_addr) | 0xa8 | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_2`](#intr_src_addr) | 0xac | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_3`](#intr_src_addr) | 0xb0 | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_4`](#intr_src_addr) | 0xb4 | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_5`](#intr_src_addr) | 0xb8 | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_6`](#intr_src_addr) | 0xbc | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_7`](#intr_src_addr) | 0xc0 | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_8`](#intr_src_addr) | 0xc4 | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_9`](#intr_src_addr) | 0xc8 | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_ADDR_10`](#intr_src_addr) | 0xcc | 4 | Destination address for interrupt source clearing write. | +| dma.[`INTR_SRC_WR_VAL_0`](#intr_src_wr_val) | 0x124 | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_1`](#intr_src_wr_val) | 0x128 | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_2`](#intr_src_wr_val) | 0x12c | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_3`](#intr_src_wr_val) | 0x130 | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_4`](#intr_src_wr_val) | 0x134 | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_5`](#intr_src_wr_val) | 0x138 | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_6`](#intr_src_wr_val) | 0x13c | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_7`](#intr_src_wr_val) | 0x140 | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_8`](#intr_src_wr_val) | 0x144 | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_9`](#intr_src_wr_val) | 0x148 | 4 | Write value for interrupt clearing write. | +| dma.[`INTR_SRC_WR_VAL_10`](#intr_src_wr_val) | 0x14c | 4 | Write value for interrupt clearing write. | ## INTR_STATE Interrupt State Register @@ -456,26 +458,24 @@ Other values are reserved. Control register for DMA data movement. - Offset: `0x44` - Reset default: `0x0` -- Reset mask: `0x880001ff` +- Reset mask: `0x8800021f` ### Fields ```wavejson -{"reg": [{"name": "opcode", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "hardware_handshake_enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "memory_buffer_auto_increment_enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "fifo_auto_increment_enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "data_direction", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "initial_transfer", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 18}, {"name": "abort", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 3}, {"name": "go", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 370}} +{"reg": [{"name": "opcode", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "hardware_handshake_enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 4}, {"name": "initial_transfer", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 17}, {"name": "abort", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 3}, {"name": "go", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}} ``` -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------------------------------------------------------------------| -| 31 | rw | 0x0 | [go](#control--go) | -| 30:28 | | | Reserved | -| 27 | wo | 0x0 | [abort](#control--abort) | -| 26:9 | | | Reserved | -| 8 | rw | 0x0 | [initial_transfer](#control--initial_transfer) | -| 7 | rw | 0x0 | [data_direction](#control--data_direction) | -| 6 | rw | 0x0 | [fifo_auto_increment_enable](#control--fifo_auto_increment_enable) | -| 5 | rw | 0x0 | [memory_buffer_auto_increment_enable](#control--memory_buffer_auto_increment_enable) | -| 4 | rw | 0x0 | [hardware_handshake_enable](#control--hardware_handshake_enable) | -| 3:0 | rw | 0x0 | [opcode](#control--opcode) | +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:-----------------------------------------------------------------| +| 31 | rw | 0x0 | [go](#control--go) | +| 30:28 | | | Reserved | +| 27 | wo | 0x0 | [abort](#control--abort) | +| 26:10 | | | Reserved | +| 9 | rw | 0x0 | [initial_transfer](#control--initial_transfer) | +| 8:5 | | | Reserved | +| 4 | rw | 0x0 | [hardware_handshake_enable](#control--hardware_handshake_enable) | +| 3:0 | rw | 0x0 | [opcode](#control--opcode) | ### CONTROL . go Trigger the DMA operation when the Go bit is set. @@ -493,22 +493,6 @@ Marks the initial transfer to initialize the DMA and SHA engine for one transfer Used for hardware handshake and ordinary transfers, in which multiple transfers contribute to a final digest. Note, for non-handshake transfers with inline hashing mode enabled, this bit must be set to also mark the first transfer. -### CONTROL . data_direction -Used in conjunction with the hardware handshake enable. -0: Receive data from LSIO FIFO to memory buffer. -1: Send data from memory buffer to LSIO FIFO. - -### CONTROL . fifo_auto_increment_enable -Used in conjunction with the hardware handshake mode of operation. -If set, reads/writes from/to incremental addresses for FIFO data accesses within each chunk, resetting to the initial value at the beginning of each new chunk. -Else uses the same address for all transactions. - -### CONTROL . memory_buffer_auto_increment_enable -Used in conjunction with the hardware handshake mode of operation. -Auto Increments the memory buffer address register by data size to point to the next memory buffer address. -Generate a warning (assert interrupt) if the auto-incremented address reaches close to the value set in limit address register to prevent destination buffer overflow. -Enables firmware to take appropriate action prior to reaching the limit. - ### CONTROL . hardware_handshake_enable Enable hardware handshake mode. Used to clear FIFOs from low speed IO peripherals receiving data, e.g., I3C receive buffer. @@ -531,9 +515,47 @@ Defines the type of DMA operations. Other values are reserved. +## SRC_CONTROL +Defines the addressing behavior of the DMA for the source address. +- Offset: `0x48` +- Reset default: `0x0` +- Reset mask: `0x3` +- Register enable: [`CFG_REGWEN`](#cfg_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "increment", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "wrap", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:2 | | | | Reserved | +| 1 | rw | 0x0 | wrap | When 1: Source address wrapped back to the starting address when finishing a chunk. | +| 0 | rw | 0x0 | increment | Defines the increment behavior after every DMA read. When 0: Source address is not changed. All reads are done from the same address. When 1: Source address is incremented by transfer_width after each read. | + +## DST_CONTROL +Defines the addressing behavior of the DMA for the destination address. +- Offset: `0x4c` +- Reset default: `0x0` +- Reset mask: `0x3` +- Register enable: [`CFG_REGWEN`](#cfg_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "increment", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "wrap", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:2 | | | | Reserved | +| 1 | rw | 0x0 | wrap | When 1: Destination address wrapped back to the starting address when finishing a chunk. | +| 0 | rw | 0x0 | increment | Defines the increment behavior after every DMA write. When 0: Destination address is not changed. All writes are done to the same address. When 1: Destintation address is incremented by transfer_width after each write. | + ## STATUS Status indication for DMA data movement. -- Offset: `0x48` +- Offset: `0x50` - Reset default: `0x0` - Reset mask: `0x3f` @@ -556,7 +578,7 @@ Status indication for DMA data movement. ## ERROR_CODE Denotes the source of the operational error. The error is cleared by writing the RW1C STATUS.error register. -- Offset: `0x4c` +- Offset: `0x54` - Reset default: `0x0` - Reset mask: `0xff` @@ -591,22 +613,22 @@ Depending on the used hashing mode, not all registers are used. | Name | Offset | |:---------------|:---------| -| SHA2_DIGEST_0 | 0x50 | -| SHA2_DIGEST_1 | 0x54 | -| SHA2_DIGEST_2 | 0x58 | -| SHA2_DIGEST_3 | 0x5c | -| SHA2_DIGEST_4 | 0x60 | -| SHA2_DIGEST_5 | 0x64 | -| SHA2_DIGEST_6 | 0x68 | -| SHA2_DIGEST_7 | 0x6c | -| SHA2_DIGEST_8 | 0x70 | -| SHA2_DIGEST_9 | 0x74 | -| SHA2_DIGEST_10 | 0x78 | -| SHA2_DIGEST_11 | 0x7c | -| SHA2_DIGEST_12 | 0x80 | -| SHA2_DIGEST_13 | 0x84 | -| SHA2_DIGEST_14 | 0x88 | -| SHA2_DIGEST_15 | 0x8c | +| SHA2_DIGEST_0 | 0x58 | +| SHA2_DIGEST_1 | 0x5c | +| SHA2_DIGEST_2 | 0x60 | +| SHA2_DIGEST_3 | 0x64 | +| SHA2_DIGEST_4 | 0x68 | +| SHA2_DIGEST_5 | 0x6c | +| SHA2_DIGEST_6 | 0x70 | +| SHA2_DIGEST_7 | 0x74 | +| SHA2_DIGEST_8 | 0x78 | +| SHA2_DIGEST_9 | 0x7c | +| SHA2_DIGEST_10 | 0x80 | +| SHA2_DIGEST_11 | 0x84 | +| SHA2_DIGEST_12 | 0x88 | +| SHA2_DIGEST_13 | 0x8c | +| SHA2_DIGEST_14 | 0x90 | +| SHA2_DIGEST_15 | 0x94 | ### Fields @@ -621,7 +643,7 @@ Depending on the used hashing mode, not all registers are used. ## HANDSHAKE_INTR_ENABLE Enable bits for incoming handshake interrupt wires. -- Offset: `0x90` +- Offset: `0x98` - Reset default: `0x7ff` - Reset mask: `0x7ff` - Register enable: [`CFG_REGWEN`](#cfg_regwen) @@ -642,7 +664,7 @@ Valid bits for which interrupt sources need clearing. When HANDSHAKE_INTR_ENABLE is non-zero and corresponding lsio_trigger becomes set, DMA issues writes with address from INTR_SRC_ADDR and write value from INTR_SRC_WR_VAL corresponding to each bit set in this register. -- Offset: `0x94` +- Offset: `0x9c` - Reset default: `0x0` - Reset mask: `0x7ff` - Register enable: [`CFG_REGWEN`](#cfg_regwen) @@ -662,7 +684,7 @@ bit set in this register. Bus selection bit where the clearing command should be performed." 0: CTN/System fabric 1: OT-internal crossbar -- Offset: `0x98` +- Offset: `0xa0` - Reset default: `0x0` - Reset mask: `0x7ff` - Register enable: [`CFG_REGWEN`](#cfg_regwen) @@ -687,17 +709,17 @@ Destination address for interrupt source clearing write. | Name | Offset | |:-----------------|:---------| -| INTR_SRC_ADDR_0 | 0x9c | -| INTR_SRC_ADDR_1 | 0xa0 | -| INTR_SRC_ADDR_2 | 0xa4 | -| INTR_SRC_ADDR_3 | 0xa8 | -| INTR_SRC_ADDR_4 | 0xac | -| INTR_SRC_ADDR_5 | 0xb0 | -| INTR_SRC_ADDR_6 | 0xb4 | -| INTR_SRC_ADDR_7 | 0xb8 | -| INTR_SRC_ADDR_8 | 0xbc | -| INTR_SRC_ADDR_9 | 0xc0 | -| INTR_SRC_ADDR_10 | 0xc4 | +| INTR_SRC_ADDR_0 | 0xa4 | +| INTR_SRC_ADDR_1 | 0xa8 | +| INTR_SRC_ADDR_2 | 0xac | +| INTR_SRC_ADDR_3 | 0xb0 | +| INTR_SRC_ADDR_4 | 0xb4 | +| INTR_SRC_ADDR_5 | 0xb8 | +| INTR_SRC_ADDR_6 | 0xbc | +| INTR_SRC_ADDR_7 | 0xc0 | +| INTR_SRC_ADDR_8 | 0xc4 | +| INTR_SRC_ADDR_9 | 0xc8 | +| INTR_SRC_ADDR_10 | 0xcc | ### Fields @@ -719,17 +741,17 @@ Write value for interrupt clearing write. | Name | Offset | |:-------------------|:---------| -| INTR_SRC_WR_VAL_0 | 0x11c | -| INTR_SRC_WR_VAL_1 | 0x120 | -| INTR_SRC_WR_VAL_2 | 0x124 | -| INTR_SRC_WR_VAL_3 | 0x128 | -| INTR_SRC_WR_VAL_4 | 0x12c | -| INTR_SRC_WR_VAL_5 | 0x130 | -| INTR_SRC_WR_VAL_6 | 0x134 | -| INTR_SRC_WR_VAL_7 | 0x138 | -| INTR_SRC_WR_VAL_8 | 0x13c | -| INTR_SRC_WR_VAL_9 | 0x140 | -| INTR_SRC_WR_VAL_10 | 0x144 | +| INTR_SRC_WR_VAL_0 | 0x124 | +| INTR_SRC_WR_VAL_1 | 0x128 | +| INTR_SRC_WR_VAL_2 | 0x12c | +| INTR_SRC_WR_VAL_3 | 0x130 | +| INTR_SRC_WR_VAL_4 | 0x134 | +| INTR_SRC_WR_VAL_5 | 0x138 | +| INTR_SRC_WR_VAL_6 | 0x13c | +| INTR_SRC_WR_VAL_7 | 0x140 | +| INTR_SRC_WR_VAL_8 | 0x144 | +| INTR_SRC_WR_VAL_9 | 0x148 | +| INTR_SRC_WR_VAL_10 | 0x14c | ### Fields diff --git a/hw/ip/dma/rtl/dma.sv b/hw/ip/dma/rtl/dma.sv index 360f281ec37431..292dd6f8915f37 100644 --- a/hw/ip/dma/rtl/dma.sv +++ b/hw/ip/dma/rtl/dma.sv @@ -72,7 +72,6 @@ module dma logic capture_return_data; logic [top_pkg::TL_DW-1:0] read_return_data_q, read_return_data_d, dma_rsp_data; - logic [SYS_ADDR_WIDTH-1:0] new_src_addr, new_dst_addr; logic dma_state_error; dma_ctrl_state_e ctrl_state_q, ctrl_state_d; @@ -268,14 +267,9 @@ module dma always_comb begin control_d.opcode = opcode_e'(reg2hw.control.opcode.q); control_d.cfg_handshake_en = reg2hw.control.hardware_handshake_enable.q; - control_d.cfg_data_direction = reg2hw.control.data_direction.q; - control_d.cfg_fifo_auto_increment_en = reg2hw.control.fifo_auto_increment_enable.q; control_d.range_valid = reg2hw.range_valid.q; control_d.enabled_memory_range_base = reg2hw.enabled_memory_range_base.q; control_d.enabled_memory_range_limit = reg2hw.enabled_memory_range_limit.q; - - control_d.cfg_memory_buffer_auto_increment_en = - reg2hw.control.memory_buffer_auto_increment_enable.q; end prim_flop_en #( @@ -748,30 +742,28 @@ module dma default: next_error[DmaSizeErr] = 1'b1; // Invalid transfer_width endcase + // Use start address on first byte of transaction if ((transfer_byte_q == '0) || - (control_q.cfg_handshake_en && - // Does the source address need resetting to the configured base address? - ((control_q.cfg_data_direction && chunk_byte_q == '0 && - !control_q.cfg_memory_buffer_auto_increment_en) || - (!control_q.cfg_data_direction && - (chunk_byte_q == '0 || !control_q.cfg_fifo_auto_increment_en))))) begin + // or when being in the fixed address mode + reg2hw.src_ctrl.increment.q == NoIncrement || + // or when transferring the first byte of a chunk and in wrapped increment mode + (chunk_byte_q == '0 && reg2hw.src_ctrl.wrap.q == WrapChunk)) begin src_addr_d = {reg2hw.src_addr_hi.q, reg2hw.src_addr_lo.q}; end else begin // Advance from the previous transaction within this chunk src_addr_d = src_addr_q + SYS_ADDR_WIDTH'(transfer_width_d); end + // Use start address on first byte of transaction if ((transfer_byte_q == '0) || - (control_q.cfg_handshake_en && - // Does the destination address need resetting to the configured base address? - ((!control_q.cfg_data_direction && chunk_byte_q == '0 && - !control_q.cfg_memory_buffer_auto_increment_en) || - (control_q.cfg_data_direction && - (chunk_byte_q == '0 || !control_q.cfg_fifo_auto_increment_en))))) begin - dst_addr_d = {reg2hw.dst_addr_hi.q, reg2hw.dst_addr_lo.q}; + // or when being in the fixed address mode + reg2hw.dst_ctrl.increment.q == NoIncrement || + // or when transferring the first byte of a chunk and in wrapped increment mode + (chunk_byte_q == '0 && reg2hw.dst_ctrl.wrap.q == WrapChunk)) begin + dst_addr_d = {reg2hw.src_addr_hi.q, reg2hw.src_addr_lo.q}; end else begin // Advance from the previous transaction within this chunk - dst_addr_d = dst_addr_q + SYS_ADDR_WIDTH'(transfer_width_d); + dst_addr_d = src_addr_q + SYS_ADDR_WIDTH'(transfer_width_d); end unique case (transfer_width_d) @@ -1139,14 +1131,6 @@ module dma (ctrl_state_q == DmaShaWait) || (ctrl_state_q == DmaShaFinalize); - assign new_dst_addr = control_q.cfg_data_direction ? - ({reg2hw.dst_addr_hi.q, reg2hw.dst_addr_lo.q} + SYS_ADDR_WIDTH'(transfer_width_q)) : - ({reg2hw.dst_addr_hi.q, reg2hw.dst_addr_lo.q} + SYS_ADDR_WIDTH'(reg2hw.chunk_data_size.q)); - - assign new_src_addr = control_q.cfg_data_direction ? - ({reg2hw.src_addr_hi.q, reg2hw.src_addr_lo.q} + SYS_ADDR_WIDTH'(reg2hw.chunk_data_size.q)) : - ({reg2hw.src_addr_hi.q, reg2hw.src_addr_lo.q} + SYS_ADDR_WIDTH'(transfer_width_q)); - // Calculate the number of bytes remaining until the end of the current chunk. // Note that the total transfer size may be a non-integral multiple of the programmed chunk size, // so we must consider the `total_data_size` here too; this is important in determining the @@ -1183,14 +1167,6 @@ module dma end end - hw2reg.control.initial_transfer.de = 1'b0; - hw2reg.control.initial_transfer.d = 1'b0; - // Clear the inline initial transfer flag starting flag when leaving the DmaIdle the first time - if ((ctrl_state_q == DmaIdle) && (ctrl_state_d != DmaIdle) && - reg2hw.control.initial_transfer.q) begin - hw2reg.control.initial_transfer.de = 1'b1; - end - hw2reg.dst_addr_hi.de = update_dst_addr_reg; hw2reg.dst_addr_hi.d = new_dst_addr[63:32]; @@ -1203,6 +1179,14 @@ module dma hw2reg.src_addr_lo.de = update_src_addr_reg; hw2reg.src_addr_lo.d = new_src_addr[31:0]; + hw2reg.control.initial_transfer.de = 1'b0; + hw2reg.control.initial_transfer.d = 1'b0; + // Clear the inline initial transfer flag starting flag when leaving the DmaIdle the first time + if ((ctrl_state_q == DmaIdle) && (ctrl_state_d != DmaIdle) && + reg2hw.control.initial_transfer.q) begin + hw2reg.control.initial_transfer.de = 1'b1; + end + // Assert busy write enable on // - transitions from IDLE out // - clearing the go bit (going back to idle) @@ -1277,23 +1261,23 @@ module dma set_error_code = (ctrl_state_q != DmaError) && (ctrl_state_d == DmaError); // Fiddle out error signals - hw2reg.error_code.src_addr_error.de = set_error_code | clear_status; - hw2reg.error_code.dst_addr_error.de = set_error_code | clear_status; - hw2reg.error_code.opcode_error.de = set_error_code | clear_status; - hw2reg.error_code.size_error.de = set_error_code | clear_status; - hw2reg.error_code.bus_error.de = set_error_code | clear_status; - hw2reg.error_code.base_limit_error.de = set_error_code | clear_status; - hw2reg.error_code.range_valid_error.de = set_error_code | clear_status; - hw2reg.error_code.asid_error.de = set_error_code | clear_status; - - hw2reg.error_code.src_addr_error.d = clear_status? '0 : next_error[DmaSrcAddrErr]; - hw2reg.error_code.dst_addr_error.d = clear_status? '0 : next_error[DmaDstAddrErr]; - hw2reg.error_code.opcode_error.d = clear_status? '0 : next_error[DmaOpcodeErr]; - hw2reg.error_code.size_error.d = clear_status? '0 : next_error[DmaSizeErr]; - hw2reg.error_code.bus_error.d = clear_status? '0 : next_error[DmaBusErr]; - hw2reg.error_code.base_limit_error.d = clear_status? '0 : next_error[DmaBaseLimitErr]; - hw2reg.error_code.range_valid_error.d = clear_status? '0 : next_error[DmaRangeValidErr]; - hw2reg.error_code.asid_error.d = clear_status? '0 : next_error[DmaAsidErr]; + hw2reg.error_code.src_addr_error.de = set_error_code | clear_status; + hw2reg.error_code.dst_addr_error.de = set_error_code | clear_status; + hw2reg.error_code.opcode_error.de = set_error_code | clear_status; + hw2reg.error_code.size_error.de = set_error_code | clear_status; + hw2reg.error_code.bus_error.de = set_error_code | clear_status; + hw2reg.error_code.base_limit_error.de = set_error_code | clear_status; + hw2reg.error_code.range_valid_error.de = set_error_code | clear_status; + hw2reg.error_code.asid_error.de = set_error_code | clear_status; + + hw2reg.error_code.src_addr_error.d = clear_status? '0 : next_error[DmaSrcAddrErr]; + hw2reg.error_code.dst_addr_error.d = clear_status? '0 : next_error[DmaDstAddrErr]; + hw2reg.error_code.opcode_error.d = clear_status? '0 : next_error[DmaOpcodeErr]; + hw2reg.error_code.size_error.d = clear_status? '0 : next_error[DmaSizeErr]; + hw2reg.error_code.bus_error.d = clear_status? '0 : next_error[DmaBusErr]; + hw2reg.error_code.base_limit_error.d = clear_status? '0 : next_error[DmaBaseLimitErr]; + hw2reg.error_code.range_valid_error.d = clear_status? '0 : next_error[DmaRangeValidErr]; + hw2reg.error_code.asid_error.d = clear_status? '0 : next_error[DmaAsidErr]; // Clear the control.abort bit once we have handled the abort request hw2reg.control.abort.de = hw2reg.status.aborted.de; diff --git a/hw/ip/dma/rtl/dma_pkg.sv b/hw/ip/dma/rtl/dma_pkg.sv index 0c7a45fdb496d9..a626671ee50879 100644 --- a/hw/ip/dma/rtl/dma_pkg.sv +++ b/hw/ip/dma/rtl/dma_pkg.sv @@ -8,7 +8,7 @@ package dma_pkg; typedef logic [dma_reg_pkg::NumIntClearSources-1:0] lsio_trigger_t; // Possible error bits the DMA can raise - typedef enum logic [3:0] { + typedef enum logic [4:0] { DmaSrcAddrErr, DmaDstAddrErr, DmaOpcodeErr, @@ -44,14 +44,14 @@ package dma_pkg; OpcSha512 = 4'h3 } opcode_e; + parameter bit NoIncrement = 1'b0; + parameter bit WrapChunk = 1'b1; + // Control state captured during the operation typedef struct packed { // Control register opcode_e opcode; logic cfg_handshake_en; - logic cfg_memory_buffer_auto_increment_en; - logic cfg_fifo_auto_increment_en; - logic cfg_data_direction; logic range_valid; // Enabled memory base register logic [31:0] enabled_memory_range_base; diff --git a/hw/ip/dma/rtl/dma_reg_pkg.sv b/hw/ip/dma/rtl/dma_reg_pkg.sv index e8a4c115ddb7f9..83ab6414b8190a 100644 --- a/hw/ip/dma/rtl/dma_reg_pkg.sv +++ b/hw/ip/dma/rtl/dma_reg_pkg.sv @@ -129,20 +129,29 @@ package dma_reg_pkg; } initial_transfer; struct packed { logic q; - } data_direction; + } hardware_handshake_enable; + struct packed { + logic [3:0] q; + } opcode; + } dma_reg2hw_control_reg_t; + + typedef struct packed { struct packed { logic q; - } fifo_auto_increment_enable; + } wrap; struct packed { logic q; - } memory_buffer_auto_increment_enable; + } increment; + } dma_reg2hw_src_control_reg_t; + + typedef struct packed { struct packed { logic q; - } hardware_handshake_enable; + } wrap; struct packed { - logic [3:0] q; - } opcode; - } dma_reg2hw_control_reg_t; + logic q; + } increment; + } dma_reg2hw_dst_control_reg_t; typedef struct packed { struct packed { @@ -307,23 +316,25 @@ package dma_reg_pkg; // Register -> HW type typedef struct packed { - dma_reg2hw_intr_state_reg_t intr_state; // [1042:1040] - dma_reg2hw_intr_enable_reg_t intr_enable; // [1039:1037] - dma_reg2hw_intr_test_reg_t intr_test; // [1036:1031] - dma_reg2hw_alert_test_reg_t alert_test; // [1030:1029] - dma_reg2hw_src_addr_lo_reg_t src_addr_lo; // [1028:997] - dma_reg2hw_src_addr_hi_reg_t src_addr_hi; // [996:965] - dma_reg2hw_dst_addr_lo_reg_t dst_addr_lo; // [964:933] - dma_reg2hw_dst_addr_hi_reg_t dst_addr_hi; // [932:901] - dma_reg2hw_addr_space_id_reg_t addr_space_id; // [900:893] - dma_reg2hw_enabled_memory_range_base_reg_t enabled_memory_range_base; // [892:860] - dma_reg2hw_enabled_memory_range_limit_reg_t enabled_memory_range_limit; // [859:827] - dma_reg2hw_range_valid_reg_t range_valid; // [826:826] - dma_reg2hw_range_regwen_reg_t range_regwen; // [825:822] - dma_reg2hw_total_data_size_reg_t total_data_size; // [821:790] - dma_reg2hw_chunk_data_size_reg_t chunk_data_size; // [789:758] - dma_reg2hw_transfer_width_reg_t transfer_width; // [757:756] - dma_reg2hw_control_reg_t control; // [755:744] + dma_reg2hw_intr_state_reg_t intr_state; // [1043:1041] + dma_reg2hw_intr_enable_reg_t intr_enable; // [1040:1038] + dma_reg2hw_intr_test_reg_t intr_test; // [1037:1032] + dma_reg2hw_alert_test_reg_t alert_test; // [1031:1030] + dma_reg2hw_src_addr_lo_reg_t src_addr_lo; // [1029:998] + dma_reg2hw_src_addr_hi_reg_t src_addr_hi; // [997:966] + dma_reg2hw_dst_addr_lo_reg_t dst_addr_lo; // [965:934] + dma_reg2hw_dst_addr_hi_reg_t dst_addr_hi; // [933:902] + dma_reg2hw_addr_space_id_reg_t addr_space_id; // [901:894] + dma_reg2hw_enabled_memory_range_base_reg_t enabled_memory_range_base; // [893:861] + dma_reg2hw_enabled_memory_range_limit_reg_t enabled_memory_range_limit; // [860:828] + dma_reg2hw_range_valid_reg_t range_valid; // [827:827] + dma_reg2hw_range_regwen_reg_t range_regwen; // [826:823] + dma_reg2hw_total_data_size_reg_t total_data_size; // [822:791] + dma_reg2hw_chunk_data_size_reg_t chunk_data_size; // [790:759] + dma_reg2hw_transfer_width_reg_t transfer_width; // [758:757] + dma_reg2hw_control_reg_t control; // [756:748] + dma_reg2hw_src_control_reg_t src_control; // [747:746] + dma_reg2hw_dst_control_reg_t dst_control; // [745:744] dma_reg2hw_status_reg_t status; // [743:737] dma_reg2hw_handshake_intr_enable_reg_t handshake_intr_enable; // [736:726] dma_reg2hw_clear_intr_src_reg_t clear_intr_src; // [725:715] @@ -365,49 +376,51 @@ package dma_reg_pkg; parameter logic [BlockAw-1:0] DMA_CHUNK_DATA_SIZE_OFFSET = 9'h 3c; parameter logic [BlockAw-1:0] DMA_TRANSFER_WIDTH_OFFSET = 9'h 40; parameter logic [BlockAw-1:0] DMA_CONTROL_OFFSET = 9'h 44; - parameter logic [BlockAw-1:0] DMA_STATUS_OFFSET = 9'h 48; - parameter logic [BlockAw-1:0] DMA_ERROR_CODE_OFFSET = 9'h 4c; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_0_OFFSET = 9'h 50; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_1_OFFSET = 9'h 54; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_2_OFFSET = 9'h 58; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_3_OFFSET = 9'h 5c; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_4_OFFSET = 9'h 60; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_5_OFFSET = 9'h 64; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_6_OFFSET = 9'h 68; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_7_OFFSET = 9'h 6c; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_8_OFFSET = 9'h 70; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_9_OFFSET = 9'h 74; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_10_OFFSET = 9'h 78; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_11_OFFSET = 9'h 7c; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_12_OFFSET = 9'h 80; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_13_OFFSET = 9'h 84; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_14_OFFSET = 9'h 88; - parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_15_OFFSET = 9'h 8c; - parameter logic [BlockAw-1:0] DMA_HANDSHAKE_INTR_ENABLE_OFFSET = 9'h 90; - parameter logic [BlockAw-1:0] DMA_CLEAR_INTR_SRC_OFFSET = 9'h 94; - parameter logic [BlockAw-1:0] DMA_CLEAR_INTR_BUS_OFFSET = 9'h 98; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_0_OFFSET = 9'h 9c; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_1_OFFSET = 9'h a0; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_2_OFFSET = 9'h a4; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_3_OFFSET = 9'h a8; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_4_OFFSET = 9'h ac; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_5_OFFSET = 9'h b0; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_6_OFFSET = 9'h b4; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_7_OFFSET = 9'h b8; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_8_OFFSET = 9'h bc; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_9_OFFSET = 9'h c0; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_10_OFFSET = 9'h c4; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_0_OFFSET = 9'h 11c; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_1_OFFSET = 9'h 120; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_2_OFFSET = 9'h 124; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_3_OFFSET = 9'h 128; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_4_OFFSET = 9'h 12c; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_5_OFFSET = 9'h 130; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_6_OFFSET = 9'h 134; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_7_OFFSET = 9'h 138; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_8_OFFSET = 9'h 13c; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_9_OFFSET = 9'h 140; - parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_10_OFFSET = 9'h 144; + parameter logic [BlockAw-1:0] DMA_SRC_CONTROL_OFFSET = 9'h 48; + parameter logic [BlockAw-1:0] DMA_DST_CONTROL_OFFSET = 9'h 4c; + parameter logic [BlockAw-1:0] DMA_STATUS_OFFSET = 9'h 50; + parameter logic [BlockAw-1:0] DMA_ERROR_CODE_OFFSET = 9'h 54; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_0_OFFSET = 9'h 58; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_1_OFFSET = 9'h 5c; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_2_OFFSET = 9'h 60; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_3_OFFSET = 9'h 64; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_4_OFFSET = 9'h 68; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_5_OFFSET = 9'h 6c; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_6_OFFSET = 9'h 70; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_7_OFFSET = 9'h 74; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_8_OFFSET = 9'h 78; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_9_OFFSET = 9'h 7c; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_10_OFFSET = 9'h 80; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_11_OFFSET = 9'h 84; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_12_OFFSET = 9'h 88; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_13_OFFSET = 9'h 8c; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_14_OFFSET = 9'h 90; + parameter logic [BlockAw-1:0] DMA_SHA2_DIGEST_15_OFFSET = 9'h 94; + parameter logic [BlockAw-1:0] DMA_HANDSHAKE_INTR_ENABLE_OFFSET = 9'h 98; + parameter logic [BlockAw-1:0] DMA_CLEAR_INTR_SRC_OFFSET = 9'h 9c; + parameter logic [BlockAw-1:0] DMA_CLEAR_INTR_BUS_OFFSET = 9'h a0; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_0_OFFSET = 9'h a4; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_1_OFFSET = 9'h a8; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_2_OFFSET = 9'h ac; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_3_OFFSET = 9'h b0; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_4_OFFSET = 9'h b4; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_5_OFFSET = 9'h b8; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_6_OFFSET = 9'h bc; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_7_OFFSET = 9'h c0; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_8_OFFSET = 9'h c4; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_9_OFFSET = 9'h c8; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_ADDR_10_OFFSET = 9'h cc; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_0_OFFSET = 9'h 124; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_1_OFFSET = 9'h 128; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_2_OFFSET = 9'h 12c; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_3_OFFSET = 9'h 130; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_4_OFFSET = 9'h 134; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_5_OFFSET = 9'h 138; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_6_OFFSET = 9'h 13c; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_7_OFFSET = 9'h 140; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_8_OFFSET = 9'h 144; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_9_OFFSET = 9'h 148; + parameter logic [BlockAw-1:0] DMA_INTR_SRC_WR_VAL_10_OFFSET = 9'h 14c; // Reset values for hwext registers and their fields parameter logic [2:0] DMA_INTR_TEST_RESVAL = 3'h 0; @@ -439,6 +452,8 @@ package dma_reg_pkg; DMA_CHUNK_DATA_SIZE, DMA_TRANSFER_WIDTH, DMA_CONTROL, + DMA_SRC_CONTROL, + DMA_DST_CONTROL, DMA_STATUS, DMA_ERROR_CODE, DMA_SHA2_DIGEST_0, @@ -485,7 +500,7 @@ package dma_reg_pkg; } dma_id_e; // Register width information to check illegal writes - parameter logic [3:0] DMA_PERMIT [61] = '{ + parameter logic [3:0] DMA_PERMIT [63] = '{ 4'b 0001, // index[ 0] DMA_INTR_STATE 4'b 0001, // index[ 1] DMA_INTR_ENABLE 4'b 0001, // index[ 2] DMA_INTR_TEST @@ -504,49 +519,51 @@ package dma_reg_pkg; 4'b 1111, // index[15] DMA_CHUNK_DATA_SIZE 4'b 0001, // index[16] DMA_TRANSFER_WIDTH 4'b 1111, // index[17] DMA_CONTROL - 4'b 0001, // index[18] DMA_STATUS - 4'b 0001, // index[19] DMA_ERROR_CODE - 4'b 1111, // index[20] DMA_SHA2_DIGEST_0 - 4'b 1111, // index[21] DMA_SHA2_DIGEST_1 - 4'b 1111, // index[22] DMA_SHA2_DIGEST_2 - 4'b 1111, // index[23] DMA_SHA2_DIGEST_3 - 4'b 1111, // index[24] DMA_SHA2_DIGEST_4 - 4'b 1111, // index[25] DMA_SHA2_DIGEST_5 - 4'b 1111, // index[26] DMA_SHA2_DIGEST_6 - 4'b 1111, // index[27] DMA_SHA2_DIGEST_7 - 4'b 1111, // index[28] DMA_SHA2_DIGEST_8 - 4'b 1111, // index[29] DMA_SHA2_DIGEST_9 - 4'b 1111, // index[30] DMA_SHA2_DIGEST_10 - 4'b 1111, // index[31] DMA_SHA2_DIGEST_11 - 4'b 1111, // index[32] DMA_SHA2_DIGEST_12 - 4'b 1111, // index[33] DMA_SHA2_DIGEST_13 - 4'b 1111, // index[34] DMA_SHA2_DIGEST_14 - 4'b 1111, // index[35] DMA_SHA2_DIGEST_15 - 4'b 0011, // index[36] DMA_HANDSHAKE_INTR_ENABLE - 4'b 0011, // index[37] DMA_CLEAR_INTR_SRC - 4'b 0011, // index[38] DMA_CLEAR_INTR_BUS - 4'b 1111, // index[39] DMA_INTR_SRC_ADDR_0 - 4'b 1111, // index[40] DMA_INTR_SRC_ADDR_1 - 4'b 1111, // index[41] DMA_INTR_SRC_ADDR_2 - 4'b 1111, // index[42] DMA_INTR_SRC_ADDR_3 - 4'b 1111, // index[43] DMA_INTR_SRC_ADDR_4 - 4'b 1111, // index[44] DMA_INTR_SRC_ADDR_5 - 4'b 1111, // index[45] DMA_INTR_SRC_ADDR_6 - 4'b 1111, // index[46] DMA_INTR_SRC_ADDR_7 - 4'b 1111, // index[47] DMA_INTR_SRC_ADDR_8 - 4'b 1111, // index[48] DMA_INTR_SRC_ADDR_9 - 4'b 1111, // index[49] DMA_INTR_SRC_ADDR_10 - 4'b 1111, // index[50] DMA_INTR_SRC_WR_VAL_0 - 4'b 1111, // index[51] DMA_INTR_SRC_WR_VAL_1 - 4'b 1111, // index[52] DMA_INTR_SRC_WR_VAL_2 - 4'b 1111, // index[53] DMA_INTR_SRC_WR_VAL_3 - 4'b 1111, // index[54] DMA_INTR_SRC_WR_VAL_4 - 4'b 1111, // index[55] DMA_INTR_SRC_WR_VAL_5 - 4'b 1111, // index[56] DMA_INTR_SRC_WR_VAL_6 - 4'b 1111, // index[57] DMA_INTR_SRC_WR_VAL_7 - 4'b 1111, // index[58] DMA_INTR_SRC_WR_VAL_8 - 4'b 1111, // index[59] DMA_INTR_SRC_WR_VAL_9 - 4'b 1111 // index[60] DMA_INTR_SRC_WR_VAL_10 + 4'b 0001, // index[18] DMA_SRC_CONTROL + 4'b 0001, // index[19] DMA_DST_CONTROL + 4'b 0001, // index[20] DMA_STATUS + 4'b 0001, // index[21] DMA_ERROR_CODE + 4'b 1111, // index[22] DMA_SHA2_DIGEST_0 + 4'b 1111, // index[23] DMA_SHA2_DIGEST_1 + 4'b 1111, // index[24] DMA_SHA2_DIGEST_2 + 4'b 1111, // index[25] DMA_SHA2_DIGEST_3 + 4'b 1111, // index[26] DMA_SHA2_DIGEST_4 + 4'b 1111, // index[27] DMA_SHA2_DIGEST_5 + 4'b 1111, // index[28] DMA_SHA2_DIGEST_6 + 4'b 1111, // index[29] DMA_SHA2_DIGEST_7 + 4'b 1111, // index[30] DMA_SHA2_DIGEST_8 + 4'b 1111, // index[31] DMA_SHA2_DIGEST_9 + 4'b 1111, // index[32] DMA_SHA2_DIGEST_10 + 4'b 1111, // index[33] DMA_SHA2_DIGEST_11 + 4'b 1111, // index[34] DMA_SHA2_DIGEST_12 + 4'b 1111, // index[35] DMA_SHA2_DIGEST_13 + 4'b 1111, // index[36] DMA_SHA2_DIGEST_14 + 4'b 1111, // index[37] DMA_SHA2_DIGEST_15 + 4'b 0011, // index[38] DMA_HANDSHAKE_INTR_ENABLE + 4'b 0011, // index[39] DMA_CLEAR_INTR_SRC + 4'b 0011, // index[40] DMA_CLEAR_INTR_BUS + 4'b 1111, // index[41] DMA_INTR_SRC_ADDR_0 + 4'b 1111, // index[42] DMA_INTR_SRC_ADDR_1 + 4'b 1111, // index[43] DMA_INTR_SRC_ADDR_2 + 4'b 1111, // index[44] DMA_INTR_SRC_ADDR_3 + 4'b 1111, // index[45] DMA_INTR_SRC_ADDR_4 + 4'b 1111, // index[46] DMA_INTR_SRC_ADDR_5 + 4'b 1111, // index[47] DMA_INTR_SRC_ADDR_6 + 4'b 1111, // index[48] DMA_INTR_SRC_ADDR_7 + 4'b 1111, // index[49] DMA_INTR_SRC_ADDR_8 + 4'b 1111, // index[50] DMA_INTR_SRC_ADDR_9 + 4'b 1111, // index[51] DMA_INTR_SRC_ADDR_10 + 4'b 1111, // index[52] DMA_INTR_SRC_WR_VAL_0 + 4'b 1111, // index[53] DMA_INTR_SRC_WR_VAL_1 + 4'b 1111, // index[54] DMA_INTR_SRC_WR_VAL_2 + 4'b 1111, // index[55] DMA_INTR_SRC_WR_VAL_3 + 4'b 1111, // index[56] DMA_INTR_SRC_WR_VAL_4 + 4'b 1111, // index[57] DMA_INTR_SRC_WR_VAL_5 + 4'b 1111, // index[58] DMA_INTR_SRC_WR_VAL_6 + 4'b 1111, // index[59] DMA_INTR_SRC_WR_VAL_7 + 4'b 1111, // index[60] DMA_INTR_SRC_WR_VAL_8 + 4'b 1111, // index[61] DMA_INTR_SRC_WR_VAL_9 + 4'b 1111 // index[62] DMA_INTR_SRC_WR_VAL_10 }; endpackage diff --git a/hw/ip/dma/rtl/dma_reg_top.sv b/hw/ip/dma/rtl/dma_reg_top.sv index 8651840da9f1a5..9038e2d2f8ca36 100644 --- a/hw/ip/dma/rtl/dma_reg_top.sv +++ b/hw/ip/dma/rtl/dma_reg_top.sv @@ -52,9 +52,9 @@ module dma_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [60:0] reg_we_check; + logic [62:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(61) + .OneHotWidth(63) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -182,17 +182,21 @@ module dma_reg_top ( logic [3:0] control_opcode_wd; logic control_hardware_handshake_enable_qs; logic control_hardware_handshake_enable_wd; - logic control_memory_buffer_auto_increment_enable_qs; - logic control_memory_buffer_auto_increment_enable_wd; - logic control_fifo_auto_increment_enable_qs; - logic control_fifo_auto_increment_enable_wd; - logic control_data_direction_qs; - logic control_data_direction_wd; logic control_initial_transfer_qs; logic control_initial_transfer_wd; logic control_abort_wd; logic control_go_qs; logic control_go_wd; + logic src_control_we; + logic src_control_increment_qs; + logic src_control_increment_wd; + logic src_control_wrap_qs; + logic src_control_wrap_wd; + logic dst_control_we; + logic dst_control_increment_qs; + logic dst_control_increment_wd; + logic dst_control_wrap_qs; + logic dst_control_wrap_wd; logic status_we; logic status_busy_qs; logic status_done_qs; @@ -1005,7 +1009,7 @@ module dma_reg_top ( // R[control]: V(False) logic control_qe; - logic [7:0] control_flds_we; + logic [4:0] control_flds_we; prim_flop #( .Width(1), .ResetValue(0) @@ -1069,168 +1073,209 @@ module dma_reg_top ( .qs (control_hardware_handshake_enable_qs) ); - // F[memory_buffer_auto_increment_enable]: 5:5 + // F[initial_transfer]: 9:9 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_control_memory_buffer_auto_increment_enable ( + ) u_control_initial_transfer ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (control_we), - .wd (control_memory_buffer_auto_increment_enable_wd), + .wd (control_initial_transfer_wd), // from internal hardware - .de (1'b0), - .d ('0), + .de (hw2reg.control.initial_transfer.de), + .d (hw2reg.control.initial_transfer.d), // to internal hardware .qe (control_flds_we[2]), - .q (reg2hw.control.memory_buffer_auto_increment_enable.q), + .q (reg2hw.control.initial_transfer.q), .ds (), // to register interface (read) - .qs (control_memory_buffer_auto_increment_enable_qs) + .qs (control_initial_transfer_qs) ); - // F[fifo_auto_increment_enable]: 6:6 + // F[abort]: 27:27 prim_subreg #( .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), + .SwAccess(prim_subreg_pkg::SwAccessWO), .RESVAL (1'h0), .Mubi (1'b0) - ) u_control_fifo_auto_increment_enable ( + ) u_control_abort ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (control_we), - .wd (control_fifo_auto_increment_enable_wd), + .wd (control_abort_wd), // from internal hardware - .de (1'b0), - .d ('0), + .de (hw2reg.control.abort.de), + .d (hw2reg.control.abort.d), // to internal hardware .qe (control_flds_we[3]), - .q (reg2hw.control.fifo_auto_increment_enable.q), + .q (reg2hw.control.abort.q), .ds (), // to register interface (read) - .qs (control_fifo_auto_increment_enable_qs) + .qs () ); - // F[data_direction]: 7:7 + // F[go]: 31:31 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_control_data_direction ( + ) u_control_go ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (control_we), - .wd (control_data_direction_wd), + .wd (control_go_wd), + + // from internal hardware + .de (hw2reg.control.go.de), + .d (hw2reg.control.go.d), + + // to internal hardware + .qe (control_flds_we[4]), + .q (reg2hw.control.go.q), + .ds (), + + // to register interface (read) + .qs (control_go_qs) + ); + assign reg2hw.control.go.qe = control_qe; + + + // R[src_control]: V(False) + // Create REGWEN-gated WE signal + logic src_control_gated_we; + assign src_control_gated_we = + src_control_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(cfg_regwen_qs)); + // F[increment]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_src_control_increment ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (src_control_gated_we), + .wd (src_control_increment_wd), // from internal hardware .de (1'b0), .d ('0), // to internal hardware - .qe (control_flds_we[4]), - .q (reg2hw.control.data_direction.q), + .qe (), + .q (reg2hw.src_control.increment.q), .ds (), // to register interface (read) - .qs (control_data_direction_qs) + .qs (src_control_increment_qs) ); - // F[initial_transfer]: 8:8 + // F[wrap]: 1:1 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_control_initial_transfer ( + ) u_src_control_wrap ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (control_we), - .wd (control_initial_transfer_wd), + .we (src_control_gated_we), + .wd (src_control_wrap_wd), // from internal hardware - .de (hw2reg.control.initial_transfer.de), - .d (hw2reg.control.initial_transfer.d), + .de (1'b0), + .d ('0), // to internal hardware - .qe (control_flds_we[5]), - .q (reg2hw.control.initial_transfer.q), + .qe (), + .q (reg2hw.src_control.wrap.q), .ds (), // to register interface (read) - .qs (control_initial_transfer_qs) + .qs (src_control_wrap_qs) ); - // F[abort]: 27:27 + + // R[dst_control]: V(False) + // Create REGWEN-gated WE signal + logic dst_control_gated_we; + assign dst_control_gated_we = + dst_control_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(cfg_regwen_qs)); + // F[increment]: 0:0 prim_subreg #( .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessWO), + .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_control_abort ( + ) u_dst_control_increment ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (control_we), - .wd (control_abort_wd), + .we (dst_control_gated_we), + .wd (dst_control_increment_wd), // from internal hardware - .de (hw2reg.control.abort.de), - .d (hw2reg.control.abort.d), + .de (1'b0), + .d ('0), // to internal hardware - .qe (control_flds_we[6]), - .q (reg2hw.control.abort.q), + .qe (), + .q (reg2hw.dst_control.increment.q), .ds (), // to register interface (read) - .qs () + .qs (dst_control_increment_qs) ); - // F[go]: 31:31 + // F[wrap]: 1:1 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) - ) u_control_go ( + ) u_dst_control_wrap ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (control_we), - .wd (control_go_wd), + .we (dst_control_gated_we), + .wd (dst_control_wrap_wd), // from internal hardware - .de (hw2reg.control.go.de), - .d (hw2reg.control.go.d), + .de (1'b0), + .d ('0), // to internal hardware - .qe (control_flds_we[7]), - .q (reg2hw.control.go.q), + .qe (), + .q (reg2hw.dst_control.wrap.q), .ds (), // to register interface (read) - .qs (control_go_qs) + .qs (dst_control_wrap_qs) ); - assign reg2hw.control.go.qe = control_qe; // R[status]: V(False) @@ -2940,7 +2985,7 @@ module dma_reg_top ( - logic [60:0] addr_hit; + logic [62:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == DMA_INTR_STATE_OFFSET); @@ -2961,49 +3006,51 @@ module dma_reg_top ( addr_hit[15] = (reg_addr == DMA_CHUNK_DATA_SIZE_OFFSET); addr_hit[16] = (reg_addr == DMA_TRANSFER_WIDTH_OFFSET); addr_hit[17] = (reg_addr == DMA_CONTROL_OFFSET); - addr_hit[18] = (reg_addr == DMA_STATUS_OFFSET); - addr_hit[19] = (reg_addr == DMA_ERROR_CODE_OFFSET); - addr_hit[20] = (reg_addr == DMA_SHA2_DIGEST_0_OFFSET); - addr_hit[21] = (reg_addr == DMA_SHA2_DIGEST_1_OFFSET); - addr_hit[22] = (reg_addr == DMA_SHA2_DIGEST_2_OFFSET); - addr_hit[23] = (reg_addr == DMA_SHA2_DIGEST_3_OFFSET); - addr_hit[24] = (reg_addr == DMA_SHA2_DIGEST_4_OFFSET); - addr_hit[25] = (reg_addr == DMA_SHA2_DIGEST_5_OFFSET); - addr_hit[26] = (reg_addr == DMA_SHA2_DIGEST_6_OFFSET); - addr_hit[27] = (reg_addr == DMA_SHA2_DIGEST_7_OFFSET); - addr_hit[28] = (reg_addr == DMA_SHA2_DIGEST_8_OFFSET); - addr_hit[29] = (reg_addr == DMA_SHA2_DIGEST_9_OFFSET); - addr_hit[30] = (reg_addr == DMA_SHA2_DIGEST_10_OFFSET); - addr_hit[31] = (reg_addr == DMA_SHA2_DIGEST_11_OFFSET); - addr_hit[32] = (reg_addr == DMA_SHA2_DIGEST_12_OFFSET); - addr_hit[33] = (reg_addr == DMA_SHA2_DIGEST_13_OFFSET); - addr_hit[34] = (reg_addr == DMA_SHA2_DIGEST_14_OFFSET); - addr_hit[35] = (reg_addr == DMA_SHA2_DIGEST_15_OFFSET); - addr_hit[36] = (reg_addr == DMA_HANDSHAKE_INTR_ENABLE_OFFSET); - addr_hit[37] = (reg_addr == DMA_CLEAR_INTR_SRC_OFFSET); - addr_hit[38] = (reg_addr == DMA_CLEAR_INTR_BUS_OFFSET); - addr_hit[39] = (reg_addr == DMA_INTR_SRC_ADDR_0_OFFSET); - addr_hit[40] = (reg_addr == DMA_INTR_SRC_ADDR_1_OFFSET); - addr_hit[41] = (reg_addr == DMA_INTR_SRC_ADDR_2_OFFSET); - addr_hit[42] = (reg_addr == DMA_INTR_SRC_ADDR_3_OFFSET); - addr_hit[43] = (reg_addr == DMA_INTR_SRC_ADDR_4_OFFSET); - addr_hit[44] = (reg_addr == DMA_INTR_SRC_ADDR_5_OFFSET); - addr_hit[45] = (reg_addr == DMA_INTR_SRC_ADDR_6_OFFSET); - addr_hit[46] = (reg_addr == DMA_INTR_SRC_ADDR_7_OFFSET); - addr_hit[47] = (reg_addr == DMA_INTR_SRC_ADDR_8_OFFSET); - addr_hit[48] = (reg_addr == DMA_INTR_SRC_ADDR_9_OFFSET); - addr_hit[49] = (reg_addr == DMA_INTR_SRC_ADDR_10_OFFSET); - addr_hit[50] = (reg_addr == DMA_INTR_SRC_WR_VAL_0_OFFSET); - addr_hit[51] = (reg_addr == DMA_INTR_SRC_WR_VAL_1_OFFSET); - addr_hit[52] = (reg_addr == DMA_INTR_SRC_WR_VAL_2_OFFSET); - addr_hit[53] = (reg_addr == DMA_INTR_SRC_WR_VAL_3_OFFSET); - addr_hit[54] = (reg_addr == DMA_INTR_SRC_WR_VAL_4_OFFSET); - addr_hit[55] = (reg_addr == DMA_INTR_SRC_WR_VAL_5_OFFSET); - addr_hit[56] = (reg_addr == DMA_INTR_SRC_WR_VAL_6_OFFSET); - addr_hit[57] = (reg_addr == DMA_INTR_SRC_WR_VAL_7_OFFSET); - addr_hit[58] = (reg_addr == DMA_INTR_SRC_WR_VAL_8_OFFSET); - addr_hit[59] = (reg_addr == DMA_INTR_SRC_WR_VAL_9_OFFSET); - addr_hit[60] = (reg_addr == DMA_INTR_SRC_WR_VAL_10_OFFSET); + addr_hit[18] = (reg_addr == DMA_SRC_CONTROL_OFFSET); + addr_hit[19] = (reg_addr == DMA_DST_CONTROL_OFFSET); + addr_hit[20] = (reg_addr == DMA_STATUS_OFFSET); + addr_hit[21] = (reg_addr == DMA_ERROR_CODE_OFFSET); + addr_hit[22] = (reg_addr == DMA_SHA2_DIGEST_0_OFFSET); + addr_hit[23] = (reg_addr == DMA_SHA2_DIGEST_1_OFFSET); + addr_hit[24] = (reg_addr == DMA_SHA2_DIGEST_2_OFFSET); + addr_hit[25] = (reg_addr == DMA_SHA2_DIGEST_3_OFFSET); + addr_hit[26] = (reg_addr == DMA_SHA2_DIGEST_4_OFFSET); + addr_hit[27] = (reg_addr == DMA_SHA2_DIGEST_5_OFFSET); + addr_hit[28] = (reg_addr == DMA_SHA2_DIGEST_6_OFFSET); + addr_hit[29] = (reg_addr == DMA_SHA2_DIGEST_7_OFFSET); + addr_hit[30] = (reg_addr == DMA_SHA2_DIGEST_8_OFFSET); + addr_hit[31] = (reg_addr == DMA_SHA2_DIGEST_9_OFFSET); + addr_hit[32] = (reg_addr == DMA_SHA2_DIGEST_10_OFFSET); + addr_hit[33] = (reg_addr == DMA_SHA2_DIGEST_11_OFFSET); + addr_hit[34] = (reg_addr == DMA_SHA2_DIGEST_12_OFFSET); + addr_hit[35] = (reg_addr == DMA_SHA2_DIGEST_13_OFFSET); + addr_hit[36] = (reg_addr == DMA_SHA2_DIGEST_14_OFFSET); + addr_hit[37] = (reg_addr == DMA_SHA2_DIGEST_15_OFFSET); + addr_hit[38] = (reg_addr == DMA_HANDSHAKE_INTR_ENABLE_OFFSET); + addr_hit[39] = (reg_addr == DMA_CLEAR_INTR_SRC_OFFSET); + addr_hit[40] = (reg_addr == DMA_CLEAR_INTR_BUS_OFFSET); + addr_hit[41] = (reg_addr == DMA_INTR_SRC_ADDR_0_OFFSET); + addr_hit[42] = (reg_addr == DMA_INTR_SRC_ADDR_1_OFFSET); + addr_hit[43] = (reg_addr == DMA_INTR_SRC_ADDR_2_OFFSET); + addr_hit[44] = (reg_addr == DMA_INTR_SRC_ADDR_3_OFFSET); + addr_hit[45] = (reg_addr == DMA_INTR_SRC_ADDR_4_OFFSET); + addr_hit[46] = (reg_addr == DMA_INTR_SRC_ADDR_5_OFFSET); + addr_hit[47] = (reg_addr == DMA_INTR_SRC_ADDR_6_OFFSET); + addr_hit[48] = (reg_addr == DMA_INTR_SRC_ADDR_7_OFFSET); + addr_hit[49] = (reg_addr == DMA_INTR_SRC_ADDR_8_OFFSET); + addr_hit[50] = (reg_addr == DMA_INTR_SRC_ADDR_9_OFFSET); + addr_hit[51] = (reg_addr == DMA_INTR_SRC_ADDR_10_OFFSET); + addr_hit[52] = (reg_addr == DMA_INTR_SRC_WR_VAL_0_OFFSET); + addr_hit[53] = (reg_addr == DMA_INTR_SRC_WR_VAL_1_OFFSET); + addr_hit[54] = (reg_addr == DMA_INTR_SRC_WR_VAL_2_OFFSET); + addr_hit[55] = (reg_addr == DMA_INTR_SRC_WR_VAL_3_OFFSET); + addr_hit[56] = (reg_addr == DMA_INTR_SRC_WR_VAL_4_OFFSET); + addr_hit[57] = (reg_addr == DMA_INTR_SRC_WR_VAL_5_OFFSET); + addr_hit[58] = (reg_addr == DMA_INTR_SRC_WR_VAL_6_OFFSET); + addr_hit[59] = (reg_addr == DMA_INTR_SRC_WR_VAL_7_OFFSET); + addr_hit[60] = (reg_addr == DMA_INTR_SRC_WR_VAL_8_OFFSET); + addr_hit[61] = (reg_addr == DMA_INTR_SRC_WR_VAL_9_OFFSET); + addr_hit[62] = (reg_addr == DMA_INTR_SRC_WR_VAL_10_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -3071,7 +3118,9 @@ module dma_reg_top ( (addr_hit[57] & (|(DMA_PERMIT[57] & ~reg_be))) | (addr_hit[58] & (|(DMA_PERMIT[58] & ~reg_be))) | (addr_hit[59] & (|(DMA_PERMIT[59] & ~reg_be))) | - (addr_hit[60] & (|(DMA_PERMIT[60] & ~reg_be))))); + (addr_hit[60] & (|(DMA_PERMIT[60] & ~reg_be))) | + (addr_hit[61] & (|(DMA_PERMIT[61] & ~reg_be))) | + (addr_hit[62] & (|(DMA_PERMIT[62] & ~reg_be))))); end // Generate write-enables @@ -3137,18 +3186,22 @@ module dma_reg_top ( assign control_hardware_handshake_enable_wd = reg_wdata[4]; - assign control_memory_buffer_auto_increment_enable_wd = reg_wdata[5]; + assign control_initial_transfer_wd = reg_wdata[9]; + + assign control_abort_wd = reg_wdata[27]; - assign control_fifo_auto_increment_enable_wd = reg_wdata[6]; + assign control_go_wd = reg_wdata[31]; + assign src_control_we = addr_hit[18] & reg_we & !reg_error; - assign control_data_direction_wd = reg_wdata[7]; + assign src_control_increment_wd = reg_wdata[0]; - assign control_initial_transfer_wd = reg_wdata[8]; + assign src_control_wrap_wd = reg_wdata[1]; + assign dst_control_we = addr_hit[19] & reg_we & !reg_error; - assign control_abort_wd = reg_wdata[27]; + assign dst_control_increment_wd = reg_wdata[0]; - assign control_go_wd = reg_wdata[31]; - assign status_we = addr_hit[18] & reg_we & !reg_error; + assign dst_control_wrap_wd = reg_wdata[1]; + assign status_we = addr_hit[20] & reg_we & !reg_error; assign status_done_wd = reg_wdata[1]; @@ -3157,79 +3210,79 @@ module dma_reg_top ( assign status_error_wd = reg_wdata[3]; assign status_chunk_done_wd = reg_wdata[5]; - assign handshake_intr_enable_we = addr_hit[36] & reg_we & !reg_error; + assign handshake_intr_enable_we = addr_hit[38] & reg_we & !reg_error; assign handshake_intr_enable_wd = reg_wdata[10:0]; - assign clear_intr_src_we = addr_hit[37] & reg_we & !reg_error; + assign clear_intr_src_we = addr_hit[39] & reg_we & !reg_error; assign clear_intr_src_wd = reg_wdata[10:0]; - assign clear_intr_bus_we = addr_hit[38] & reg_we & !reg_error; + assign clear_intr_bus_we = addr_hit[40] & reg_we & !reg_error; assign clear_intr_bus_wd = reg_wdata[10:0]; - assign intr_src_addr_0_we = addr_hit[39] & reg_we & !reg_error; + assign intr_src_addr_0_we = addr_hit[41] & reg_we & !reg_error; assign intr_src_addr_0_wd = reg_wdata[31:0]; - assign intr_src_addr_1_we = addr_hit[40] & reg_we & !reg_error; + assign intr_src_addr_1_we = addr_hit[42] & reg_we & !reg_error; assign intr_src_addr_1_wd = reg_wdata[31:0]; - assign intr_src_addr_2_we = addr_hit[41] & reg_we & !reg_error; + assign intr_src_addr_2_we = addr_hit[43] & reg_we & !reg_error; assign intr_src_addr_2_wd = reg_wdata[31:0]; - assign intr_src_addr_3_we = addr_hit[42] & reg_we & !reg_error; + assign intr_src_addr_3_we = addr_hit[44] & reg_we & !reg_error; assign intr_src_addr_3_wd = reg_wdata[31:0]; - assign intr_src_addr_4_we = addr_hit[43] & reg_we & !reg_error; + assign intr_src_addr_4_we = addr_hit[45] & reg_we & !reg_error; assign intr_src_addr_4_wd = reg_wdata[31:0]; - assign intr_src_addr_5_we = addr_hit[44] & reg_we & !reg_error; + assign intr_src_addr_5_we = addr_hit[46] & reg_we & !reg_error; assign intr_src_addr_5_wd = reg_wdata[31:0]; - assign intr_src_addr_6_we = addr_hit[45] & reg_we & !reg_error; + assign intr_src_addr_6_we = addr_hit[47] & reg_we & !reg_error; assign intr_src_addr_6_wd = reg_wdata[31:0]; - assign intr_src_addr_7_we = addr_hit[46] & reg_we & !reg_error; + assign intr_src_addr_7_we = addr_hit[48] & reg_we & !reg_error; assign intr_src_addr_7_wd = reg_wdata[31:0]; - assign intr_src_addr_8_we = addr_hit[47] & reg_we & !reg_error; + assign intr_src_addr_8_we = addr_hit[49] & reg_we & !reg_error; assign intr_src_addr_8_wd = reg_wdata[31:0]; - assign intr_src_addr_9_we = addr_hit[48] & reg_we & !reg_error; + assign intr_src_addr_9_we = addr_hit[50] & reg_we & !reg_error; assign intr_src_addr_9_wd = reg_wdata[31:0]; - assign intr_src_addr_10_we = addr_hit[49] & reg_we & !reg_error; + assign intr_src_addr_10_we = addr_hit[51] & reg_we & !reg_error; assign intr_src_addr_10_wd = reg_wdata[31:0]; - assign intr_src_wr_val_0_we = addr_hit[50] & reg_we & !reg_error; + assign intr_src_wr_val_0_we = addr_hit[52] & reg_we & !reg_error; assign intr_src_wr_val_0_wd = reg_wdata[31:0]; - assign intr_src_wr_val_1_we = addr_hit[51] & reg_we & !reg_error; + assign intr_src_wr_val_1_we = addr_hit[53] & reg_we & !reg_error; assign intr_src_wr_val_1_wd = reg_wdata[31:0]; - assign intr_src_wr_val_2_we = addr_hit[52] & reg_we & !reg_error; + assign intr_src_wr_val_2_we = addr_hit[54] & reg_we & !reg_error; assign intr_src_wr_val_2_wd = reg_wdata[31:0]; - assign intr_src_wr_val_3_we = addr_hit[53] & reg_we & !reg_error; + assign intr_src_wr_val_3_we = addr_hit[55] & reg_we & !reg_error; assign intr_src_wr_val_3_wd = reg_wdata[31:0]; - assign intr_src_wr_val_4_we = addr_hit[54] & reg_we & !reg_error; + assign intr_src_wr_val_4_we = addr_hit[56] & reg_we & !reg_error; assign intr_src_wr_val_4_wd = reg_wdata[31:0]; - assign intr_src_wr_val_5_we = addr_hit[55] & reg_we & !reg_error; + assign intr_src_wr_val_5_we = addr_hit[57] & reg_we & !reg_error; assign intr_src_wr_val_5_wd = reg_wdata[31:0]; - assign intr_src_wr_val_6_we = addr_hit[56] & reg_we & !reg_error; + assign intr_src_wr_val_6_we = addr_hit[58] & reg_we & !reg_error; assign intr_src_wr_val_6_wd = reg_wdata[31:0]; - assign intr_src_wr_val_7_we = addr_hit[57] & reg_we & !reg_error; + assign intr_src_wr_val_7_we = addr_hit[59] & reg_we & !reg_error; assign intr_src_wr_val_7_wd = reg_wdata[31:0]; - assign intr_src_wr_val_8_we = addr_hit[58] & reg_we & !reg_error; + assign intr_src_wr_val_8_we = addr_hit[60] & reg_we & !reg_error; assign intr_src_wr_val_8_wd = reg_wdata[31:0]; - assign intr_src_wr_val_9_we = addr_hit[59] & reg_we & !reg_error; + assign intr_src_wr_val_9_we = addr_hit[61] & reg_we & !reg_error; assign intr_src_wr_val_9_wd = reg_wdata[31:0]; - assign intr_src_wr_val_10_we = addr_hit[60] & reg_we & !reg_error; + assign intr_src_wr_val_10_we = addr_hit[62] & reg_we & !reg_error; assign intr_src_wr_val_10_wd = reg_wdata[31:0]; @@ -3254,9 +3307,9 @@ module dma_reg_top ( reg_we_check[15] = chunk_data_size_gated_we; reg_we_check[16] = transfer_width_gated_we; reg_we_check[17] = control_we; - reg_we_check[18] = status_we; - reg_we_check[19] = 1'b0; - reg_we_check[20] = 1'b0; + reg_we_check[18] = src_control_gated_we; + reg_we_check[19] = dst_control_gated_we; + reg_we_check[20] = status_we; reg_we_check[21] = 1'b0; reg_we_check[22] = 1'b0; reg_we_check[23] = 1'b0; @@ -3272,31 +3325,33 @@ module dma_reg_top ( reg_we_check[33] = 1'b0; reg_we_check[34] = 1'b0; reg_we_check[35] = 1'b0; - reg_we_check[36] = handshake_intr_enable_gated_we; - reg_we_check[37] = clear_intr_src_gated_we; - reg_we_check[38] = clear_intr_bus_gated_we; - reg_we_check[39] = intr_src_addr_0_gated_we; - reg_we_check[40] = intr_src_addr_1_gated_we; - reg_we_check[41] = intr_src_addr_2_gated_we; - reg_we_check[42] = intr_src_addr_3_gated_we; - reg_we_check[43] = intr_src_addr_4_gated_we; - reg_we_check[44] = intr_src_addr_5_gated_we; - reg_we_check[45] = intr_src_addr_6_gated_we; - reg_we_check[46] = intr_src_addr_7_gated_we; - reg_we_check[47] = intr_src_addr_8_gated_we; - reg_we_check[48] = intr_src_addr_9_gated_we; - reg_we_check[49] = intr_src_addr_10_gated_we; - reg_we_check[50] = intr_src_wr_val_0_gated_we; - reg_we_check[51] = intr_src_wr_val_1_gated_we; - reg_we_check[52] = intr_src_wr_val_2_gated_we; - reg_we_check[53] = intr_src_wr_val_3_gated_we; - reg_we_check[54] = intr_src_wr_val_4_gated_we; - reg_we_check[55] = intr_src_wr_val_5_gated_we; - reg_we_check[56] = intr_src_wr_val_6_gated_we; - reg_we_check[57] = intr_src_wr_val_7_gated_we; - reg_we_check[58] = intr_src_wr_val_8_gated_we; - reg_we_check[59] = intr_src_wr_val_9_gated_we; - reg_we_check[60] = intr_src_wr_val_10_gated_we; + reg_we_check[36] = 1'b0; + reg_we_check[37] = 1'b0; + reg_we_check[38] = handshake_intr_enable_gated_we; + reg_we_check[39] = clear_intr_src_gated_we; + reg_we_check[40] = clear_intr_bus_gated_we; + reg_we_check[41] = intr_src_addr_0_gated_we; + reg_we_check[42] = intr_src_addr_1_gated_we; + reg_we_check[43] = intr_src_addr_2_gated_we; + reg_we_check[44] = intr_src_addr_3_gated_we; + reg_we_check[45] = intr_src_addr_4_gated_we; + reg_we_check[46] = intr_src_addr_5_gated_we; + reg_we_check[47] = intr_src_addr_6_gated_we; + reg_we_check[48] = intr_src_addr_7_gated_we; + reg_we_check[49] = intr_src_addr_8_gated_we; + reg_we_check[50] = intr_src_addr_9_gated_we; + reg_we_check[51] = intr_src_addr_10_gated_we; + reg_we_check[52] = intr_src_wr_val_0_gated_we; + reg_we_check[53] = intr_src_wr_val_1_gated_we; + reg_we_check[54] = intr_src_wr_val_2_gated_we; + reg_we_check[55] = intr_src_wr_val_3_gated_we; + reg_we_check[56] = intr_src_wr_val_4_gated_we; + reg_we_check[57] = intr_src_wr_val_5_gated_we; + reg_we_check[58] = intr_src_wr_val_6_gated_we; + reg_we_check[59] = intr_src_wr_val_7_gated_we; + reg_we_check[60] = intr_src_wr_val_8_gated_we; + reg_we_check[61] = intr_src_wr_val_9_gated_we; + reg_we_check[62] = intr_src_wr_val_10_gated_we; end // Read data return @@ -3381,15 +3436,22 @@ module dma_reg_top ( addr_hit[17]: begin reg_rdata_next[3:0] = control_opcode_qs; reg_rdata_next[4] = control_hardware_handshake_enable_qs; - reg_rdata_next[5] = control_memory_buffer_auto_increment_enable_qs; - reg_rdata_next[6] = control_fifo_auto_increment_enable_qs; - reg_rdata_next[7] = control_data_direction_qs; - reg_rdata_next[8] = control_initial_transfer_qs; + reg_rdata_next[9] = control_initial_transfer_qs; reg_rdata_next[27] = '0; reg_rdata_next[31] = control_go_qs; end addr_hit[18]: begin + reg_rdata_next[0] = src_control_increment_qs; + reg_rdata_next[1] = src_control_wrap_qs; + end + + addr_hit[19]: begin + reg_rdata_next[0] = dst_control_increment_qs; + reg_rdata_next[1] = dst_control_wrap_qs; + end + + addr_hit[20]: begin reg_rdata_next[0] = status_busy_qs; reg_rdata_next[1] = status_done_qs; reg_rdata_next[2] = status_aborted_qs; @@ -3398,7 +3460,7 @@ module dma_reg_top ( reg_rdata_next[5] = status_chunk_done_qs; end - addr_hit[19]: begin + addr_hit[21]: begin reg_rdata_next[0] = error_code_src_addr_error_qs; reg_rdata_next[1] = error_code_dst_addr_error_qs; reg_rdata_next[2] = error_code_opcode_error_qs; @@ -3409,167 +3471,167 @@ module dma_reg_top ( reg_rdata_next[7] = error_code_asid_error_qs; end - addr_hit[20]: begin + addr_hit[22]: begin reg_rdata_next[31:0] = sha2_digest_0_qs; end - addr_hit[21]: begin + addr_hit[23]: begin reg_rdata_next[31:0] = sha2_digest_1_qs; end - addr_hit[22]: begin + addr_hit[24]: begin reg_rdata_next[31:0] = sha2_digest_2_qs; end - addr_hit[23]: begin + addr_hit[25]: begin reg_rdata_next[31:0] = sha2_digest_3_qs; end - addr_hit[24]: begin + addr_hit[26]: begin reg_rdata_next[31:0] = sha2_digest_4_qs; end - addr_hit[25]: begin + addr_hit[27]: begin reg_rdata_next[31:0] = sha2_digest_5_qs; end - addr_hit[26]: begin + addr_hit[28]: begin reg_rdata_next[31:0] = sha2_digest_6_qs; end - addr_hit[27]: begin + addr_hit[29]: begin reg_rdata_next[31:0] = sha2_digest_7_qs; end - addr_hit[28]: begin + addr_hit[30]: begin reg_rdata_next[31:0] = sha2_digest_8_qs; end - addr_hit[29]: begin + addr_hit[31]: begin reg_rdata_next[31:0] = sha2_digest_9_qs; end - addr_hit[30]: begin + addr_hit[32]: begin reg_rdata_next[31:0] = sha2_digest_10_qs; end - addr_hit[31]: begin + addr_hit[33]: begin reg_rdata_next[31:0] = sha2_digest_11_qs; end - addr_hit[32]: begin + addr_hit[34]: begin reg_rdata_next[31:0] = sha2_digest_12_qs; end - addr_hit[33]: begin + addr_hit[35]: begin reg_rdata_next[31:0] = sha2_digest_13_qs; end - addr_hit[34]: begin + addr_hit[36]: begin reg_rdata_next[31:0] = sha2_digest_14_qs; end - addr_hit[35]: begin + addr_hit[37]: begin reg_rdata_next[31:0] = sha2_digest_15_qs; end - addr_hit[36]: begin + addr_hit[38]: begin reg_rdata_next[10:0] = handshake_intr_enable_qs; end - addr_hit[37]: begin + addr_hit[39]: begin reg_rdata_next[10:0] = clear_intr_src_qs; end - addr_hit[38]: begin + addr_hit[40]: begin reg_rdata_next[10:0] = clear_intr_bus_qs; end - addr_hit[39]: begin + addr_hit[41]: begin reg_rdata_next[31:0] = intr_src_addr_0_qs; end - addr_hit[40]: begin + addr_hit[42]: begin reg_rdata_next[31:0] = intr_src_addr_1_qs; end - addr_hit[41]: begin + addr_hit[43]: begin reg_rdata_next[31:0] = intr_src_addr_2_qs; end - addr_hit[42]: begin + addr_hit[44]: begin reg_rdata_next[31:0] = intr_src_addr_3_qs; end - addr_hit[43]: begin + addr_hit[45]: begin reg_rdata_next[31:0] = intr_src_addr_4_qs; end - addr_hit[44]: begin + addr_hit[46]: begin reg_rdata_next[31:0] = intr_src_addr_5_qs; end - addr_hit[45]: begin + addr_hit[47]: begin reg_rdata_next[31:0] = intr_src_addr_6_qs; end - addr_hit[46]: begin + addr_hit[48]: begin reg_rdata_next[31:0] = intr_src_addr_7_qs; end - addr_hit[47]: begin + addr_hit[49]: begin reg_rdata_next[31:0] = intr_src_addr_8_qs; end - addr_hit[48]: begin + addr_hit[50]: begin reg_rdata_next[31:0] = intr_src_addr_9_qs; end - addr_hit[49]: begin + addr_hit[51]: begin reg_rdata_next[31:0] = intr_src_addr_10_qs; end - addr_hit[50]: begin + addr_hit[52]: begin reg_rdata_next[31:0] = intr_src_wr_val_0_qs; end - addr_hit[51]: begin + addr_hit[53]: begin reg_rdata_next[31:0] = intr_src_wr_val_1_qs; end - addr_hit[52]: begin + addr_hit[54]: begin reg_rdata_next[31:0] = intr_src_wr_val_2_qs; end - addr_hit[53]: begin + addr_hit[55]: begin reg_rdata_next[31:0] = intr_src_wr_val_3_qs; end - addr_hit[54]: begin + addr_hit[56]: begin reg_rdata_next[31:0] = intr_src_wr_val_4_qs; end - addr_hit[55]: begin + addr_hit[57]: begin reg_rdata_next[31:0] = intr_src_wr_val_5_qs; end - addr_hit[56]: begin + addr_hit[58]: begin reg_rdata_next[31:0] = intr_src_wr_val_6_qs; end - addr_hit[57]: begin + addr_hit[59]: begin reg_rdata_next[31:0] = intr_src_wr_val_7_qs; end - addr_hit[58]: begin + addr_hit[60]: begin reg_rdata_next[31:0] = intr_src_wr_val_8_qs; end - addr_hit[59]: begin + addr_hit[61]: begin reg_rdata_next[31:0] = intr_src_wr_val_9_qs; end - addr_hit[60]: begin + addr_hit[62]: begin reg_rdata_next[31:0] = intr_src_wr_val_10_qs; end