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[hw,dma,rtl] Use a status interrupt and interrupt prims
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Signed-off-by: Robert Schilling <[email protected]>
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@Razer6
Razer6 committed Sep 19, 2024
1 parent d46f9fc commit 1d03f6b
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Showing 4 changed files with 43 additions and 36 deletions.
2 changes: 2 additions & 0 deletions hw/ip/dma/data/dma.hjson
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Expand Up @@ -100,9 +100,11 @@
interrupt_list: [
{ name: "dma_done"
desc: "DMA operation has been completed."
type: "status"
}
{ name: "dma_error"
desc: "DMA error has occurred. DMA_STATUS.error_code register shows the details."
type: "status"
}
]
alert_list: [
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6 changes: 3 additions & 3 deletions hw/ip/dma/doc/registers.md
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Expand Up @@ -76,14 +76,14 @@ Interrupt State Register
### Fields

```wavejson
{"reg": [{"name": "dma_done", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "dma_error", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
{"reg": [{"name": "dma_done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "dma_error", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
```

| Bits | Type | Reset | Name | Description |
|:------:|:------:|:-------:|:----------|:--------------------------------------------------------------------------|
| 31:2 | | | | Reserved |
| 1 | rw1c | 0x0 | dma_error | DMA error has occurred. DMA_STATUS.error_code register shows the details. |
| 0 | rw1c | 0x0 | dma_done | DMA operation has been completed. |
| 1 | ro | 0x0 | dma_error | DMA error has occurred. DMA_STATUS.error_code register shows the details. |
| 0 | ro | 0x0 | dma_done | DMA operation has been completed. |

## INTR_ENABLE
Interrupt Enable Register
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49 changes: 31 additions & 18 deletions hw/ip/dma/rtl/dma.sv
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Expand Up @@ -1082,17 +1082,39 @@ module dma
assign sha2_data.mask = {<<1{req_dst_be_q}};

// Interrupt logic
logic test_done_interrupt;
logic test_error_interrupt;
logic data_move_state, data_move_state_valid;
logic update_dst_addr_reg, update_src_addr_reg;

assign test_done_interrupt = reg2hw.intr_test.dma_done.q && reg2hw.intr_test.dma_done.qe;
assign test_error_interrupt = reg2hw.intr_test.dma_error.q && reg2hw.intr_test.dma_error.qe;
prim_intr_hw #(
.IntrT ( "Status" )
) u_intr_dma_done (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.event_intr_i ( reg2hw.intr_state.dma_done.q ),
.reg2hw_intr_enable_q_i ( reg2hw.intr_enable.dma_done.q ),
.reg2hw_intr_test_q_i ( reg2hw.intr_test.dma_done.q ),
.reg2hw_intr_test_qe_i ( reg2hw.intr_test.dma_done.qe ),
.reg2hw_intr_state_q_i ( reg2hw.intr_state.dma_done.q ),
.hw2reg_intr_state_de_o ( hw2reg.intr_state.dma_done.de ),
.hw2reg_intr_state_d_o ( hw2reg.intr_state.dma_done.d ),
.intr_o ( intr_dma_done_o )
);

// Signal interrupt controller whenever an enabled interrupt info bit is set
assign intr_dma_done_o = reg2hw.intr_state.dma_done.q && reg2hw.intr_enable.dma_done.q;
assign intr_dma_error_o = reg2hw.intr_state.dma_error.q && reg2hw.intr_enable.dma_error.q;
prim_intr_hw #(
.IntrT ( "Status" )
) u_intr_error (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.event_intr_i ( reg2hw.intr_state.dma_error.q ),
.reg2hw_intr_enable_q_i ( reg2hw.intr_enable.dma_error.q ),
.reg2hw_intr_test_q_i ( reg2hw.intr_test.dma_error.q ),
.reg2hw_intr_test_qe_i ( reg2hw.intr_test.dma_error.qe ),
.reg2hw_intr_state_q_i ( reg2hw.intr_state.dma_error.q ),
.hw2reg_intr_state_de_o ( hw2reg.intr_state.dma_error.de ),
.hw2reg_intr_state_d_o ( hw2reg.intr_state.dma_error.d ),
.intr_o ( intr_dma_error_o )
);

logic data_move_state, data_move_state_valid;
logic update_dst_addr_reg, update_src_addr_reg;

// Data was moved if we get a write valid response
assign data_move_state_valid = (write_rsp_valid && (ctrl_state_q == DmaSendWrite ||
Expand Down Expand Up @@ -1258,15 +1280,6 @@ module dma
hw2reg.control.abort.de = hw2reg.status.aborted.de;
hw2reg.control.abort.d = 1'b0;

// Interrupt management
// Raise the done interrupt either when finishing finishing a single chunk or the whole
// transfer.
hw2reg.intr_state.dma_done.de = reg2hw.status.done.q | chunk_done | test_done_interrupt;
hw2reg.intr_state.dma_done.d = 1'b1;

hw2reg.intr_state.dma_error.de = reg2hw.status.error.q | test_error_interrupt;
hw2reg.intr_state.dma_error.d = 1'b1;

// Clear the SHA2 digests if the SHA2 valid flag is cleared (RW1C)
if (reg2hw.status.sha2_digest_valid.qe & reg2hw.status.sha2_digest_valid.q) begin
for (int i = 0; i < NR_SHA_DIGEST_ELEMENTS; i++) begin
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22 changes: 7 additions & 15 deletions hw/ip/dma/rtl/dma_reg_top.sv
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Expand Up @@ -124,11 +124,8 @@ module dma_reg_top (
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
// or <reg>_{wd|we|qs} if field == 1 or 0
logic intr_state_we;
logic intr_state_dma_done_qs;
logic intr_state_dma_done_wd;
logic intr_state_dma_error_qs;
logic intr_state_dma_error_wd;
logic intr_enable_we;
logic intr_enable_dma_done_qs;
logic intr_enable_dma_done_wd;
Expand Down Expand Up @@ -311,16 +308,16 @@ module dma_reg_top (
// F[dma_done]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0),
.Mubi (1'b0)
) u_intr_state_dma_done (
.clk_i (clk_i),
.rst_ni (rst_ni),

// from register interface
.we (intr_state_we),
.wd (intr_state_dma_done_wd),
.we (1'b0),
.wd ('0),

// from internal hardware
.de (hw2reg.intr_state.dma_done.de),
Expand All @@ -338,16 +335,16 @@ module dma_reg_top (
// F[dma_error]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0),
.Mubi (1'b0)
) u_intr_state_dma_error (
.clk_i (clk_i),
.rst_ni (rst_ni),

// from register interface
.we (intr_state_we),
.wd (intr_state_dma_error_wd),
.we (1'b0),
.wd ('0),

// from internal hardware
.de (hw2reg.intr_state.dma_error.de),
Expand Down Expand Up @@ -3007,11 +3004,6 @@ module dma_reg_top (
end

// Generate write-enables
assign intr_state_we = addr_hit[0] & reg_we & !reg_error;

assign intr_state_dma_done_wd = reg_wdata[0];

assign intr_state_dma_error_wd = reg_wdata[1];
assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;

assign intr_enable_dma_done_wd = reg_wdata[0];
Expand Down Expand Up @@ -3169,7 +3161,7 @@ module dma_reg_top (
// Assign write-enables to checker logic vector.
always_comb begin
reg_we_check = '0;
reg_we_check[0] = intr_state_we;
reg_we_check[0] = 1'b0;
reg_we_check[1] = intr_enable_we;
reg_we_check[2] = intr_test_we;
reg_we_check[3] = alert_test_we;
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