Various DV fixes #167
GregACAnnotations
1 error and 8 warnings
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verible-lint
Process completed with exit code 1.
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verible-lint:
rtl/ibex_core.sv#L1334
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]" location:{path:"./rtl/ibex_core.sv" range:{start:{line:1334 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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verible-lint:
rtl/ibex_core.sv#L1335
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]" location:{path:"./rtl/ibex_core.sv" range:{start:{line:1335 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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verible-lint:
rtl/ibex_core.sv#L1336
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]" location:{path:"./rtl/ibex_core.sv" range:{start:{line:1336 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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verible-lint:
rtl/ibex_core.sv#L1337
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]" location:{path:"./rtl/ibex_core.sv" range:{start:{line:1337 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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verible-lint:
rtl/ibex_core.sv#L1340
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 112 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 112 [Style: line-length] [line-length]" location:{path:"./rtl/ibex_core.sv" range:{start:{line:1340 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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verible-lint:
rtl/ibex_core.sv#L1341
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]" location:{path:"./rtl/ibex_core.sv" range:{start:{line:1341 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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verible-lint:
rtl/ibex_core.sv#L1342
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 112 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 112 [Style: line-length] [line-length]" location:{path:"./rtl/ibex_core.sv" range:{start:{line:1342 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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verible-lint:
rtl/ibex_core.sv#L1343
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]" location:{path:"./rtl/ibex_core.sv" range:{start:{line:1343 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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