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SPEC.txt
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SPEC.txt
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==============================
= JDH-8 SPEC =
==============================
=== OVERVIEW ===
* Minicomputer designed to be implemented with TTL
* 8-bit data width
* 16-bit address bus/64 KiB accessible memory, more with banking
* Memory banking via MB register allowing for 256 possible memory banks
(total 24-bit address space, 16 MiB possible addressable memory)
* Designed for 4 MHz clock speed, ~100-150k instructions/second
* Device communication via dedicated I/O instructions
=== INSTRUCTIONS ===
0: MW reg, imm8/reg -> reg = imm8/reg
1: LW reg, [imm16/HL] -> reg = [HL/imm16]
2: SW [imm16/HL], reg -> [HL/imm16] = reg
3: PUSH imm8/reg -> [SP--] = imm8/reg
4: POP reg -> reg = [++SP]
5: LDA [imm16] -> HL = imm16
6: JNZ imm8/reg -> PC = HL if imm8/reg != 0 else NOP
7: INB reg, imm8/reg -> reg = PORT[imm8/reg]
8: OUTB imm8/reg, reg -> PORT[imm8/reg] = reg
9: ADD^ reg, imm8/reg -> reg = reg + imm8/reg
A: ADC^ reg, imm8/reg -> reg = reg + imm8/reg + c
B: AND reg, imm8/reg -> reg = reg & imm8/reg
C: OR reg, imm8/reg -> reg = reg | imm8/reg
D: NOR reg, imm8/reg -> reg = ~(reg | imm8/reg)
E: CMP^ reg, imm8/reg -> f = compare reg, imm8/reg (see below)
F: SBB^ reg, imm8/reg -> reg = reg - imm8/reg - b
* imm8/16 are the byte(s) immediately following the instruction byte in memory
* with imm8/reg and imm16/HL, the choice is indicated by the y-bit
(see INSTRUCTION LAYOUT)
^ these instructions load the (F)lags register
=== REGISTERS ===
A (0): GP register
B (1): GP register
C (2): GP register
D (3): GP register
L (4): GP register/(L)ow index register
H (5): GP register/(H)igh index register
Z (6): GP register
F (7): flags (LSB to MSB)
LESS
EQUAL
CARRY
BORROW
* Calling convention
* A, B, C, D, Z for arguments
* Use 16-bit pairs AB and CD if arguments are 16-bits wide
* Skip register if necessary to pair registers together into 16 bits
* Remaining arguments pushed to stack in order
* Return value in Z
=== INSTRUCTION LAYOUT ===
Instruction layout is XXXXYZZZ where
X: 4-bit instruction identifier (see INSTRUCTIONS)
Y: 0 if argument is imm(8/16), 1 if argument is reg
Z: 3-bit register identifier of first register argument (see REGISTERS)
* instructions with reg, reg arguments have the second register encoded in the
first three bits of the second instruction byte
* For LW/SW, the Y-bit indicates imm16 (0) and HL (1). Z-bits are ALWAYS reg.
* Instructions can be 1-3 bytes long
* PUSH/POP with one register argument are one byte instructions
* LW/SW with Y=0 (imm16) are 3 bytes each
* LDA is always 3 bytes
=== MEMORY LAYOUT ===
0x0000..0x7FFF: GENERAL PURPOSE ROM
0x8000..0xBFFF: GENERAL PURPOSE RAM (BANKED)
0xC000..0xFDFF: GENERAL PURPOSE RAM
0xFC00..0xFEFF: STACK (RECOMMENDED), else GP RAM
0xFF00..0xFFF9: GENERAL PURPOSE RAM
0xFFFA..0xFFFA: MB/(M)emory (B)ank
0xFFFB..0xFFFB: UNUSED
0xFFFC..0xFFFD: SP/(S)tack (P)ointer
0xFFFE..0xFFFF: PC/(P)rogram (C)ounter
=== MEMORY BANKING ===
0x8000..0xBFFF can be swapped using the MB register, where MB=0 indicates that
the built-in RAM is in use. MB=1 maps to the built-in VRAM.
=== PORTS ===
PORTS are used to communicate with devices or by the JDH-8 itself. See
SPECIAL PORTS for a list of which ports are controlled by the JDH-8 and not
external devices.
=== SPECIAL PORTS ===
0x00: STATUS
=== STATUS REGISTER ===
The status register can be read/written with PORT 0 using the INB and OUTB
instructions. It contains control information about the current JDH-8 state.
Its bits are as follows, from LSB to MSB:
UNUSED (RW)
ERROR (RO)
POWER (RW)
HALT (RW)
=== VIDEO ===
The JDH-8 circuit/emulator include support for a graphics card which outputs
an analog signal at 208x240 not-exactly-square black or white pixels using
the same 4 MHz clock as the rest of the computer. This is done by using memory
bank 1 as shared VRAM so the CPU has fast read/write access. The memory layout
for the image is as follows:
* VRAM starts at 0x8000 (start of banked memory, 0x0000 in the physical chip)
* Each scanline (208 horizontal pixels) of the image spans 32 contiguous bytes
in VRAM
* Scanlines are layed out as follows:
* [0..3] (4 bytes) padding
* [4..29] (26 bytes) data, one bit per pixel
* [30..31] (2 bytes) padding
Note that depending on the screen, not all parts of the scanlines will be
visible, so the "safe" drawing area is pixels 8..199 out of 0..207. All vertical
lines will be visible due to large vertical padding built into the video card.