From 129465fbb2483729deaa8c1e8572b64a87f2d711 Mon Sep 17 00:00:00 2001 From: umarcor Date: Sun, 26 Sep 2021 16:22:07 +0200 Subject: [PATCH 1/2] TEST intersphinx --- ConceptualModel.rst | 18 +++++++++++++++++- conf.py | 4 ++-- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/ConceptualModel.rst b/ConceptualModel.rst index fb16ca2..0e33dfe 100644 --- a/ConceptualModel.rst +++ b/ConceptualModel.rst @@ -41,7 +41,23 @@ Its goal is the interoperability of diverse tools and languages with documented 3 | Language Model Syntax/design Document Object Model (DOM) of the language(s). - See :doc:`vhdlmodel:index`, :doc:`svmodel:index` and :ref:`OSVB: pyVHDLModelUtils `. + + * ``ref | goals`` :ref:`goals` + * ``ref | pyVHDLModel:goals`` :ref:`pyVHDLModel:goals` + * ``ref | pyvhdlmodel:goals`` :ref:`pyvhdlmodel:goals` + + * ``doc | Glossary`` :doc:`Glossary` + * ``doc | pyVHDLModel:Glossary`` :doc:`pyVHDLModel:Glossary` + * ``doc | pyvhdlmodel:Glossary`` :doc:`pyvhdlmodel:Glossary` + + * ``ref | vhdlmodel`` :ref:`vhdlmodel` + * ``ref | pyVHDLModel:vhdlmodel`` :ref:`pyVHDLModel:vhdlmodel` + * ``ref | pyvhdlmodel:vhdlmodel`` :ref:`pyvhdlmodel:vhdlmodel` + + * ``doc | pySVModel:Glossary`` :doc:`pySVModel:Glossary` + * ``ref | pySVModel:svmodel`` :ref:`pySVModel:svmodel` + + See :doc:`pyVHDLModel:index`, :doc:`pySVModel:index` and :ref:`OSVB: pyVHDLModelUtils `. 4 | Project Tool independent information (files/filesets, primary design units, testbenches, `hdl/constraints `__, diff --git a/conf.py b/conf.py index 9b685d7..60e439d 100644 --- a/conf.py +++ b/conf.py @@ -178,8 +178,8 @@ def _LatestTagName(): intersphinx_mapping = { 'python': ('https://docs.python.org/3', None), 'osvb': ('https://umarcor.github.io/osvb', None), - 'vhdlmodel': ('https://vhdl.github.io/pyVHDLModel', None), - 'svmodel': ('https://edaa-org.github.io/pySystemVerilogModel', None), + 'pyVHDLModel': ('https://vhdl.github.io/pyVHDLModel', None), + 'pySVModel': ('https://edaa-org.github.io/pySystemVerilogModel', None), } From b90167d38c2782dbc4d3a3f6360e84dead7b6fdd Mon Sep 17 00:00:00 2001 From: umarcor Date: Sat, 2 Oct 2021 14:09:32 +0200 Subject: [PATCH 2/2] TEST lowercase intersphinx ids --- conf.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/conf.py b/conf.py index 60e439d..d26f6c9 100644 --- a/conf.py +++ b/conf.py @@ -178,8 +178,8 @@ def _LatestTagName(): intersphinx_mapping = { 'python': ('https://docs.python.org/3', None), 'osvb': ('https://umarcor.github.io/osvb', None), - 'pyVHDLModel': ('https://vhdl.github.io/pyVHDLModel', None), - 'pySVModel': ('https://edaa-org.github.io/pySystemVerilogModel', None), + 'pyvhdlmodel': ('https://vhdl.github.io/pyVHDLModel', None), + 'pysvmodel': ('https://edaa-org.github.io/pySystemVerilogModel', None), }