PinSetup.c

//*****************************************************************************
// Copyright (c) 2014 Texas Instruments Incorporated.  All rights reserved.
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//
// This file was automatically generated by the Tiva C Series PinMux Utility
// Version: 1.0.4
//
//*****************************************************************************

#include <stdint.h>
#include <stdbool.h>
#include "PinSetup.h"
#include "inc/hw_types.h"
#include "inc/hw_memmap.h"
#include "inc/hw_gpio.h"
#include "driverlib/sysctl.h"
#include "driverlib/pin_map.h"
#include "driverlib/rom_map.h"
#include "driverlib/gpio.h"

//*****************************************************************************
void
PortFunctionInit(void)
{
    //
    // Enable Peripheral Clocks 
    //
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3);
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1);
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);

    //
    // Enable pin PA2 for GPIOInput
    //
    MAP_GPIOPinTypeGPIOInput(GPIO_PORTA_BASE, GPIO_PIN_2);

    //
    // Enable pin PF3 for SSI1 SSI1FSS
    //
    MAP_GPIOPinConfigure(GPIO_PF3_SSI1FSS);
    MAP_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_3);

    //
    // Enable pin PF0 for SSI1 SSI1RX
    // First open the lock and select the bits we want to modify in the GPIO commit register.
    //
    HWREG(GPIO_PORTF_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;
    HWREG(GPIO_PORTF_BASE + GPIO_O_CR) = 0x1;

    //
    // Now modify the configuration of the pins that we unlocked.
    //
    MAP_GPIOPinConfigure(GPIO_PF0_SSI1RX);
    MAP_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_0);

    //
    // Enable pin PF1 for SSI1 SSI1TX
    //
    MAP_GPIOPinConfigure(GPIO_PF1_SSI1TX);
    MAP_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_1);

    //
    // Enable pin PF2 for SSI1 SSI1CLK
    //
    MAP_GPIOPinConfigure(GPIO_PF2_SSI1CLK);
    MAP_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_2);

    //
    // Enable pin PD3 for SSI3 SSI3TX
    //
    MAP_GPIOPinConfigure(GPIO_PD3_SSI3TX);
    MAP_GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_3);

    //
    // Enable pin PD2 for SSI3 SSI3RX
    //
    MAP_GPIOPinConfigure(GPIO_PD2_SSI3RX);
    MAP_GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_2);

    //
    // Enable pin PD0 for SSI3 SSI3CLK
    //
    MAP_GPIOPinConfigure(GPIO_PD0_SSI3CLK);
    MAP_GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_0);

    //
    // Enable pin PD1 for SSI3 SSI3FSS
    //
    MAP_GPIOPinConfigure(GPIO_PD1_SSI3FSS);
    MAP_GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_1);
}