From ea558107a01540cfd3d369b918a674c3c5f09fc4 Mon Sep 17 00:00:00 2001 From: Alex Swehla Date: Wed, 25 Sep 2024 14:50:15 -0700 Subject: [PATCH 1/6] remove master/slave from amba --- src/main/scala/amba/ahb/AHBLite.scala | 8 +- src/main/scala/amba/ahb/Bundles.scala | 34 +++--- src/main/scala/amba/ahb/Monitor.scala | 16 +-- src/main/scala/amba/ahb/Nodes.scala | 98 ++++++++-------- src/main/scala/amba/ahb/Parameters.scala | 40 +++---- src/main/scala/amba/ahb/RegisterRouter.scala | 4 +- src/main/scala/amba/ahb/SRAM.scala | 4 +- src/main/scala/amba/ahb/Test.scala | 18 +-- src/main/scala/amba/ahb/ToTL.scala | 22 ++-- src/main/scala/amba/ahb/Xbar.scala | 32 +++--- src/main/scala/amba/ahb/package.scala | 12 +- src/main/scala/amba/apb/Bundles.scala | 4 +- src/main/scala/amba/apb/Nodes.scala | 24 ++-- src/main/scala/amba/apb/Parameters.scala | 34 +++--- src/main/scala/amba/apb/RegisterRouter.scala | 4 +- src/main/scala/amba/apb/SRAM.scala | 4 +- src/main/scala/amba/apb/Test.scala | 2 +- src/main/scala/amba/apb/ToTL.scala | 14 +-- src/main/scala/amba/apb/Xbar.scala | 18 +-- src/main/scala/amba/apb/package.scala | 6 +- src/main/scala/amba/axi4/AsyncCrossing.scala | 8 +- src/main/scala/amba/axi4/Buffer.scala | 4 +- src/main/scala/amba/axi4/Credited.scala | 4 +- src/main/scala/amba/axi4/Deinterleaver.scala | 22 ++-- src/main/scala/amba/axi4/Filter.scala | 18 +-- src/main/scala/amba/axi4/Fragmenter.scala | 30 ++--- src/main/scala/amba/axi4/IdIndexer.scala | 22 ++-- src/main/scala/amba/axi4/Nodes.scala | 70 ++++++------ src/main/scala/amba/axi4/Parameters.scala | 70 ++++++------ src/main/scala/amba/axi4/RegisterRouter.scala | 4 +- src/main/scala/amba/axi4/SRAM.scala | 8 +- src/main/scala/amba/axi4/Test.scala | 14 +-- src/main/scala/amba/axi4/ToTL.scala | 30 ++--- src/main/scala/amba/axi4/UserYanker.scala | 26 ++--- src/main/scala/amba/axi4/Xbar.scala | 56 ++++----- src/main/scala/amba/axi4/package.scala | 6 +- src/main/scala/amba/axis/Nodes.scala | 28 ++--- src/main/scala/amba/axis/Parameters.scala | 108 +++++++++--------- src/main/scala/amba/axis/Xbar.scala | 20 ++-- src/main/scala/amba/axis/package.scala | 6 +- src/main/scala/amba/package.scala | 2 +- 41 files changed, 477 insertions(+), 477 deletions(-) diff --git a/src/main/scala/amba/ahb/AHBLite.scala b/src/main/scala/amba/ahb/AHBLite.scala index 7e80611690c..5e439c83e08 100644 --- a/src/main/scala/amba/ahb/AHBLite.scala +++ b/src/main/scala/amba/ahb/AHBLite.scala @@ -7,14 +7,14 @@ import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp} class AHBLite()(implicit p: Parameters) extends LazyModule { - val node = AHBMasterAdapterNode( - masterFn = { mp => mp }, - slaveFn = { sp => sp.copy(lite = false) }) + val node = AHBManagerAdapterNode( + managerFn = { mp => mp }, + subordinateFn = { sp => sp.copy(lite = false) }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => - require (edgeOut.slave.lite) // or else this adapter is pointless + require (edgeOut.subordinate.lite) // or else this adapter is pointless out.hmastlock.get := in.hlock.get in.hgrant.get := true.B diff --git a/src/main/scala/amba/ahb/Bundles.scala b/src/main/scala/amba/ahb/Bundles.scala index 662087aae86..5500ab463b1 100644 --- a/src/main/scala/amba/ahb/Bundles.scala +++ b/src/main/scala/amba/ahb/Bundles.scala @@ -5,10 +5,10 @@ package freechips.rocketchip.amba.ahb import chisel3._ import freechips.rocketchip.util._ -// Signal directions are from the master's point-of-view -class AHBSlaveBundle(val params: AHBBundleParameters) extends Bundle +// Signal directions are from the manager's point-of-view +class AHBSubordinateBundle(val params: AHBBundleParameters) extends Bundle { - // Control signals from the arbiter to slave + // Control signals from the arbiter to subordinate val hmastlock = Output(Bool()) val hsel = Output(Bool()) @@ -16,7 +16,7 @@ class AHBSlaveBundle(val params: AHBBundleParameters) extends Bundle val hready = Output(Bool()) // from arbiter val hreadyout = Input(Bool()) // to arbiter - // A-phase signals from arbiter to slave + // A-phase signals from arbiter to subordinate val htrans = Output(UInt(params.transBits.W)) val hsize = Output(UInt(params.sizeBits.W)) val hburst = Output(UInt(params.burstBits.W)) @@ -25,27 +25,27 @@ class AHBSlaveBundle(val params: AHBBundleParameters) extends Bundle val haddr = Output(UInt(params.addrBits.W)) val hauser = BundleMap(params.requestFields) - // D-phase signals from arbiter to slave + // D-phase signals from arbiter to subordinate val hduser = BundleMap(params.responseFields) val hwdata = Output(UInt(params.dataBits.W)) - // D-phase signals from slave to arbiter + // D-phase signals from subordinate to arbiter val hresp = Input(UInt(params.hrespBits.W)) val hrdata = Input(UInt(params.dataBits.W)) // Split signals - val hmaster = if (params.lite) None else Some(Output(UInt(4.W))) + val hmanager = if (params.lite) None else Some(Output(UInt(4.W))) val hsplit = if (params.lite) None else Some(Input(UInt(16.W))) } -class AHBMasterBundle(val params: AHBBundleParameters) extends Bundle +class AHBManagerBundle(val params: AHBBundleParameters) extends Bundle { - // Control signals from master to arbiter + // Control signals from manager to arbiter val hmastlock = if (params.lite) Some(Output(Bool())) else None val hlock = if (params.lite) None else Some(Output(Bool())) val hbusreq = if (params.lite) None else Some(Output(Bool())) - // Flow control from arbiter to master + // Flow control from arbiter to manager val hgrant = if (params.lite) None else Some(Input(Bool())) val hready = Input(Bool()) @@ -54,7 +54,7 @@ class AHBMasterBundle(val params: AHBBundleParameters) extends Bundle def busreq(): Bool = if (params.lite) WireInit(true.B) else hbusreq.get def grant(): Bool = if (params.lite) WireInit(true.B) else hgrant.get - // A-phase signals from master to arbiter + // A-phase signals from manager to arbiter val htrans = Output(UInt(params.transBits.W)) val hsize = Output(UInt(params.sizeBits.W)) val hburst = Output(UInt(params.burstBits.W)) @@ -63,21 +63,21 @@ class AHBMasterBundle(val params: AHBBundleParameters) extends Bundle val haddr = Output(UInt(params.addrBits.W)) val hauser = BundleMap(params.requestFields) - // D-phase signals from master to arbiter + // D-phase signals from manager to arbiter val hduser = BundleMap(params.responseFields) val hwdata = Output(UInt(params.dataBits.W)) - // D-phase response from arbiter to master + // D-phase response from arbiter to manager val hresp = Input(UInt(params.hrespBits.W)) val hrdata = Input(UInt(params.dataBits.W)) } -object AHBSlaveBundle +object AHBSubordinateBundle { - def apply(params: AHBBundleParameters) = new AHBSlaveBundle(params) + def apply(params: AHBBundleParameters) = new AHBSubordinateBundle(params) } -object AHBMasterBundle +object AHBManagerBundle { - def apply(params: AHBBundleParameters) = new AHBMasterBundle(params) + def apply(params: AHBBundleParameters) = new AHBManagerBundle(params) } diff --git a/src/main/scala/amba/ahb/Monitor.scala b/src/main/scala/amba/ahb/Monitor.scala index 3a2936ab33b..cd4cdc2c501 100644 --- a/src/main/scala/amba/ahb/Monitor.scala +++ b/src/main/scala/amba/ahb/Monitor.scala @@ -4,27 +4,27 @@ package freechips.rocketchip.amba.ahb import chisel3._ -case class AHBSlaveMonitorArgs(edge: AHBEdgeParameters) +case class AHBSubordinateMonitorArgs(edge: AHBEdgeParameters) -abstract class AHBSlaveMonitorBase(args: AHBSlaveMonitorArgs) extends Module +abstract class AHBSubordinateMonitorBase(args: AHBSubordinateMonitorArgs) extends Module { val io = IO(new Bundle { - val in = Input(new AHBSlaveBundle(args.edge.bundle)) + val in = Input(new AHBSubordinateBundle(args.edge.bundle)) }) - def legalize(bundle: AHBSlaveBundle, edge: AHBEdgeParameters, reset: Reset): Unit + def legalize(bundle: AHBSubordinateBundle, edge: AHBEdgeParameters, reset: Reset): Unit legalize(io.in, args.edge, reset) } -case class AHBMasterMonitorArgs(edge: AHBEdgeParameters) +case class AHBManagerMonitorArgs(edge: AHBEdgeParameters) -abstract class AHBMasterMonitorBase(args: AHBMasterMonitorArgs) extends Module +abstract class AHBManagerMonitorBase(args: AHBManagerMonitorArgs) extends Module { val io = IO(new Bundle { - val in = Input(new AHBMasterBundle(args.edge.bundle)) + val in = Input(new AHBManagerBundle(args.edge.bundle)) }) - def legalize(bundle: AHBMasterBundle, edge: AHBEdgeParameters, reset: Reset): Unit + def legalize(bundle: AHBManagerBundle, edge: AHBEdgeParameters, reset: Reset): Unit legalize(io.in, args.edge, reset) } diff --git a/src/main/scala/amba/ahb/Nodes.scala b/src/main/scala/amba/ahb/Nodes.scala index 33c33ccd213..9d6daa043fe 100644 --- a/src/main/scala/amba/ahb/Nodes.scala +++ b/src/main/scala/amba/ahb/Nodes.scala @@ -10,80 +10,80 @@ import org.chipsalliance.cde.config.{Parameters, Field} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.nodes.{SimpleNodeImp, RenderedEdge, OutwardNode, InwardNode, SourceNode, SinkNode, IdentityNode, AdapterNode, MixedNexusNode, NexusNode} -case object AHBSlaveMonitorBuilder extends Field[AHBSlaveMonitorArgs => AHBSlaveMonitorBase] +case object AHBSubordinateMonitorBuilder extends Field[AHBSubordinateMonitorArgs => AHBSubordinateMonitorBase] -// From Arbiter to Slave -object AHBImpSlave extends SimpleNodeImp[AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBSlaveBundle] +// From Arbiter to Subordinate +object AHBImpSubordinate extends SimpleNodeImp[AHBManagerPortParameters, AHBSubordinatePortParameters, AHBEdgeParameters, AHBSubordinateBundle] { - def edge(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = AHBEdgeParameters(pd, pu, p, sourceInfo) - def bundle(e: AHBEdgeParameters) = AHBSlaveBundle(e.bundle) - def render(e: AHBEdgeParameters) = RenderedEdge(colour = "#00ccff" /* bluish */, label = (e.slave.beatBytes * 8).toString) + def edge(pd: AHBManagerPortParameters, pu: AHBSubordinatePortParameters, p: Parameters, sourceInfo: SourceInfo) = AHBEdgeParameters(pd, pu, p, sourceInfo) + def bundle(e: AHBEdgeParameters) = AHBSubordinateBundle(e.bundle) + def render(e: AHBEdgeParameters) = RenderedEdge(colour = "#00ccff" /* bluish */, label = (e.subordinate.beatBytes * 8).toString) - override def monitor(bundle: AHBSlaveBundle, edge: AHBEdgeParameters): Unit = { - edge.params.lift(AHBSlaveMonitorBuilder).foreach { builder => - val monitor = Module(builder(AHBSlaveMonitorArgs(edge))) + override def monitor(bundle: AHBSubordinateBundle, edge: AHBEdgeParameters): Unit = { + edge.params.lift(AHBSubordinateMonitorBuilder).foreach { builder => + val monitor = Module(builder(AHBSubordinateMonitorArgs(edge))) monitor.io.in := bundle } } - override def mixO(pd: AHBMasterPortParameters, node: OutwardNode[AHBMasterPortParameters, AHBSlavePortParameters, AHBSlaveBundle]): AHBMasterPortParameters = - pd.copy(masters = pd.masters.map { c => c.copy (nodePath = node +: c.nodePath) }) - override def mixI(pu: AHBSlavePortParameters, node: InwardNode[AHBMasterPortParameters, AHBSlavePortParameters, AHBSlaveBundle]): AHBSlavePortParameters = - pu.copy(slaves = pu.slaves.map { m => m.copy (nodePath = node +: m.nodePath) }) + override def mixO(pd: AHBManagerPortParameters, node: OutwardNode[AHBManagerPortParameters, AHBSubordinatePortParameters, AHBSubordinateBundle]): AHBManagerPortParameters = + pd.copy(managers = pd.managers.map { c => c.copy (nodePath = node +: c.nodePath) }) + override def mixI(pu: AHBSubordinatePortParameters, node: InwardNode[AHBManagerPortParameters, AHBSubordinatePortParameters, AHBSubordinateBundle]): AHBSubordinatePortParameters = + pu.copy(subordinates = pu.subordinates.map { m => m.copy (nodePath = node +: m.nodePath) }) } -case object AHBMasterMonitorBuilder extends Field[AHBMasterMonitorArgs => AHBMasterMonitorBase] +case object AHBManagerMonitorBuilder extends Field[AHBManagerMonitorArgs => AHBManagerMonitorBase] -// From Master to Arbiter -object AHBImpMaster extends SimpleNodeImp[AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBMasterBundle] +// From Manager to Arbiter +object AHBImpManager extends SimpleNodeImp[AHBManagerPortParameters, AHBSubordinatePortParameters, AHBEdgeParameters, AHBManagerBundle] { - def edge(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = AHBEdgeParameters(pd, pu, p, sourceInfo) - def bundle(e: AHBEdgeParameters) = AHBMasterBundle(e.bundle) - def render(e: AHBEdgeParameters) = RenderedEdge(colour = "#00ccff" /* bluish */, label = (e.slave.beatBytes * 8).toString) + def edge(pd: AHBManagerPortParameters, pu: AHBSubordinatePortParameters, p: Parameters, sourceInfo: SourceInfo) = AHBEdgeParameters(pd, pu, p, sourceInfo) + def bundle(e: AHBEdgeParameters) = AHBManagerBundle(e.bundle) + def render(e: AHBEdgeParameters) = RenderedEdge(colour = "#00ccff" /* bluish */, label = (e.subordinate.beatBytes * 8).toString) - override def monitor(bundle: AHBMasterBundle, edge: AHBEdgeParameters): Unit = { - edge.params.lift(AHBMasterMonitorBuilder).foreach { builder => - val monitor = Module(builder(AHBMasterMonitorArgs(edge))) + override def monitor(bundle: AHBManagerBundle, edge: AHBEdgeParameters): Unit = { + edge.params.lift(AHBManagerMonitorBuilder).foreach { builder => + val monitor = Module(builder(AHBManagerMonitorArgs(edge))) monitor.io.in := bundle } } - override def mixO(pd: AHBMasterPortParameters, node: OutwardNode[AHBMasterPortParameters, AHBSlavePortParameters, AHBMasterBundle]): AHBMasterPortParameters = - pd.copy(masters = pd.masters.map { c => c.copy (nodePath = node +: c.nodePath) }) - override def mixI(pu: AHBSlavePortParameters, node: InwardNode[AHBMasterPortParameters, AHBSlavePortParameters, AHBMasterBundle]): AHBSlavePortParameters = - pu.copy(slaves = pu.slaves.map { m => m.copy (nodePath = node +: m.nodePath) }) + override def mixO(pd: AHBManagerPortParameters, node: OutwardNode[AHBManagerPortParameters, AHBSubordinatePortParameters, AHBManagerBundle]): AHBManagerPortParameters = + pd.copy(managers = pd.managers.map { c => c.copy (nodePath = node +: c.nodePath) }) + override def mixI(pu: AHBSubordinatePortParameters, node: InwardNode[AHBManagerPortParameters, AHBSubordinatePortParameters, AHBManagerBundle]): AHBSubordinatePortParameters = + pu.copy(subordinates = pu.subordinates.map { m => m.copy (nodePath = node +: m.nodePath) }) } // Nodes implemented inside modules -case class AHBMasterSourceNode(portParams: Seq[AHBMasterPortParameters])(implicit valName: ValName) extends SourceNode(AHBImpMaster)(portParams) -case class AHBSlaveSourceNode(portParams: Seq[AHBMasterPortParameters])(implicit valName: ValName) extends SourceNode(AHBImpSlave)(portParams) -case class AHBMasterSinkNode(portParams: Seq[AHBSlavePortParameters])(implicit valName: ValName) extends SinkNode(AHBImpMaster)(portParams) -case class AHBSlaveSinkNode(portParams: Seq[AHBSlavePortParameters])(implicit valName: ValName) extends SinkNode(AHBImpSlave)(portParams) -case class AHBMasterIdentityNode()(implicit valName: ValName) extends IdentityNode(AHBImpMaster)() -case class AHBSlaveIdentityNode()(implicit valName: ValName) extends IdentityNode(AHBImpSlave)() - -case class AHBMasterAdapterNode( - masterFn: AHBMasterPortParameters => AHBMasterPortParameters, - slaveFn: AHBSlavePortParameters => AHBSlavePortParameters)( +case class AHBManagerSourceNode(portParams: Seq[AHBManagerPortParameters])(implicit valName: ValName) extends SourceNode(AHBImpManager)(portParams) +case class AHBSubordinateSourceNode(portParams: Seq[AHBManagerPortParameters])(implicit valName: ValName) extends SourceNode(AHBImpSubordinate)(portParams) +case class AHBManagerSinkNode(portParams: Seq[AHBSubordinatePortParameters])(implicit valName: ValName) extends SinkNode(AHBImpManager)(portParams) +case class AHBSubordinateSinkNode(portParams: Seq[AHBSubordinatePortParameters])(implicit valName: ValName) extends SinkNode(AHBImpSubordinate)(portParams) +case class AHBManagerIdentityNode()(implicit valName: ValName) extends IdentityNode(AHBImpManager)() +case class AHBSubordinateIdentityNode()(implicit valName: ValName) extends IdentityNode(AHBImpSubordinate)() + +case class AHBManagerAdapterNode( + managerFn: AHBManagerPortParameters => AHBManagerPortParameters, + subordinateFn: AHBSubordinatePortParameters => AHBSubordinatePortParameters)( implicit valName: ValName) - extends AdapterNode(AHBImpMaster)(masterFn, slaveFn) + extends AdapterNode(AHBImpManager)(managerFn, subordinateFn) -case class AHBSlaveAdapterNode( - masterFn: AHBMasterPortParameters => AHBMasterPortParameters, - slaveFn: AHBSlavePortParameters => AHBSlavePortParameters)( +case class AHBSubordinateAdapterNode( + managerFn: AHBManagerPortParameters => AHBManagerPortParameters, + subordinateFn: AHBSubordinatePortParameters => AHBSubordinatePortParameters)( implicit valName: ValName) - extends AdapterNode(AHBImpMaster)(masterFn, slaveFn) + extends AdapterNode(AHBImpManager)(managerFn, subordinateFn) -// From Master to Arbiter to Slave +// From Manager to Arbiter to Subordinate case class AHBArbiterNode( - masterFn: Seq[AHBMasterPortParameters] => AHBMasterPortParameters, - slaveFn: Seq[AHBSlavePortParameters] => AHBSlavePortParameters)( + managerFn: Seq[AHBManagerPortParameters] => AHBManagerPortParameters, + subordinateFn: Seq[AHBSubordinatePortParameters] => AHBSubordinatePortParameters)( implicit valName: ValName) - extends MixedNexusNode(AHBImpMaster, AHBImpSlave)(masterFn, slaveFn) + extends MixedNexusNode(AHBImpManager, AHBImpSubordinate)(managerFn, subordinateFn) -// Combine multiple Slaves into one logical Slave (suitable to attach to an Arbiter) +// Combine multiple Subordinates into one logical Subordinate (suitable to attach to an Arbiter) case class AHBFanoutNode( - masterFn: Seq[AHBMasterPortParameters] => AHBMasterPortParameters, - slaveFn: Seq[AHBSlavePortParameters] => AHBSlavePortParameters)( + managerFn: Seq[AHBManagerPortParameters] => AHBManagerPortParameters, + subordinateFn: Seq[AHBSubordinatePortParameters] => AHBSubordinatePortParameters)( implicit valName: ValName) - extends NexusNode(AHBImpSlave)(masterFn, slaveFn) + extends NexusNode(AHBImpSubordinate)(managerFn, subordinateFn) diff --git a/src/main/scala/amba/ahb/Parameters.scala b/src/main/scala/amba/ahb/Parameters.scala index 0039b928b7c..474a811cff3 100644 --- a/src/main/scala/amba/ahb/Parameters.scala +++ b/src/main/scala/amba/ahb/Parameters.scala @@ -15,7 +15,7 @@ import freechips.rocketchip.util.{BundleField, BundleFieldBase, BundleKeyBase} import scala.math.{max, min} -case class AHBSlaveParameters( +case class AHBSubordinateParameters( address: Seq[AddressSet], resources: Seq[Resource] = Nil, regionType: RegionType.T = RegionType.GET_EFFECTS, @@ -47,19 +47,19 @@ case class AHBSlaveParameters( } } -case class AHBSlavePortParameters( - slaves: Seq[AHBSlaveParameters], +case class AHBSubordinatePortParameters( + subordinates: Seq[AHBSubordinateParameters], beatBytes: Int, lite: Boolean, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) { - require (!slaves.isEmpty) + require (!subordinates.isEmpty) require (isPow2(beatBytes)) - val minMaxTransfer = slaves.map(_.minMaxTransfer).min // useful for fragmentation - val maxTransfer = slaves.map(_.maxTransfer).max - val maxAddress = slaves.map(_.maxAddress).max + val minMaxTransfer = subordinates.map(_.minMaxTransfer).min // useful for fragmentation + val maxTransfer = subordinates.map(_.maxTransfer).max + val maxAddress = subordinates.map(_.maxAddress).max // Check the link is not pointlessly wide require (maxTransfer >= beatBytes) @@ -67,19 +67,19 @@ case class AHBSlavePortParameters( require (maxTransfer <= beatBytes * AHBParameters.maxTransfer) // Require disjoint ranges for addresses - slaves.combinations(2).foreach { case Seq(x,y) => + subordinates.combinations(2).foreach { case Seq(x,y) => x.address.foreach { a => y.address.foreach { b => require (!a.overlaps(b)) } } } } -case class AHBMasterParameters( +case class AHBManagerParameters( name: String, nodePath: Seq[BaseNode] = Nil) -case class AHBMasterPortParameters( - masters: Seq[AHBMasterParameters], +case class AHBManagerPortParameters( + managers: Seq[AHBManagerParameters], requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) @@ -118,20 +118,20 @@ object AHBBundleParameters def union(x: Seq[AHBBundleParameters]) = if (x.isEmpty) emptyBundleParams else x.tail.foldLeft(x.head)((x,y) => x.union(y)) - def apply(master: AHBMasterPortParameters, slave: AHBSlavePortParameters) = + def apply(manager: AHBManagerPortParameters, subordinate: AHBSubordinatePortParameters) = new AHBBundleParameters( - addrBits = log2Up(slave.maxAddress+1), - dataBits = slave.beatBytes * 8, - requestFields = BundleField.accept(master.requestFields, slave.requestKeys), - responseFields = BundleField.accept(slave.responseFields, master.responseKeys), - lite = slave.lite) + addrBits = log2Up(subordinate.maxAddress+1), + dataBits = subordinate.beatBytes * 8, + requestFields = BundleField.accept(manager.requestFields, subordinate.requestKeys), + responseFields = BundleField.accept(subordinate.responseFields, manager.responseKeys), + lite = subordinate.lite) } case class AHBEdgeParameters( - master: AHBMasterPortParameters, - slave: AHBSlavePortParameters, + manager: AHBManagerPortParameters, + subordinate: AHBSubordinatePortParameters, params: Parameters, sourceInfo: SourceInfo) { - val bundle = AHBBundleParameters(master, slave) + val bundle = AHBBundleParameters(manager, subordinate) } diff --git a/src/main/scala/amba/ahb/RegisterRouter.scala b/src/main/scala/amba/ahb/RegisterRouter.scala index e2619b66c8c..8cfe0562bb7 100644 --- a/src/main/scala/amba/ahb/RegisterRouter.scala +++ b/src/main/scala/amba/ahb/RegisterRouter.scala @@ -18,8 +18,8 @@ import freechips.rocketchip.util.MaskGen import scala.math.min case class AHBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)(implicit valName: ValName) - extends SinkNode(AHBImpSlave)(Seq(AHBSlavePortParameters( - Seq(AHBSlaveParameters( + extends SinkNode(AHBImpSubordinate)(Seq(AHBSubordinatePortParameters( + Seq(AHBSubordinateParameters( address = Seq(address), executable = executable, supportsWrite = TransferSizes(1, min(address.alignment.toInt, beatBytes * AHBParameters.maxTransfer)), diff --git a/src/main/scala/amba/ahb/SRAM.scala b/src/main/scala/amba/ahb/SRAM.scala index a4a8bdeae3b..082ccbcc6a8 100644 --- a/src/main/scala/amba/ahb/SRAM.scala +++ b/src/main/scala/amba/ahb/SRAM.scala @@ -22,8 +22,8 @@ class AHBRAM( errors: Seq[AddressSet] = Nil) (implicit p: Parameters) extends DiplomaticSRAM(address, beatBytes, devName) { - val node = AHBSlaveSinkNode(Seq(AHBSlavePortParameters( - Seq(AHBSlaveParameters( + val node = AHBSubordinateSinkNode(Seq(AHBSubordinatePortParameters( + Seq(AHBSubordinateParameters( address = List(address) ++ errors, resources = resources, regionType = if (cacheable) RegionType.UNCACHED else RegionType.IDEMPOTENT, diff --git a/src/main/scala/amba/ahb/Test.scala b/src/main/scala/amba/ahb/Test.scala index 43a57977dcc..6c4a0fe89d4 100644 --- a/src/main/scala/amba/ahb/Test.scala +++ b/src/main/scala/amba/ahb/Test.scala @@ -53,12 +53,12 @@ trait HasFuzzTarget { AddressSet(0x900, ~0x900)) // ie: 0x900-0x9ff, 0xb00-0xbff, ... 0xf00-0xfff } -class AHBFuzzMaster(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule with HasFuzzTarget +class AHBFuzzManager(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule with HasFuzzTarget { - val node = AHBSlaveIdentityNode() + val node = AHBSubordinateIdentityNode() val arb = LazyModule(new AHBArbiter) val fuzz = LazyModule(new TLFuzzer(txns, overrideAddress = Some(fuzzAddr))) - val model = LazyModule(new TLRAMModel("AHBFuzzMaster", ignoreCorruptData=false)) + val model = LazyModule(new TLRAMModel("AHBFuzzManager", ignoreCorruptData=false)) (node := arb.node @@ -80,9 +80,9 @@ class AHBFuzzMaster(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L } } -class AHBFuzzSlave()(implicit p: Parameters) extends SimpleLazyModule with HasFuzzTarget +class AHBFuzzSubordinate()(implicit p: Parameters) extends SimpleLazyModule with HasFuzzTarget { - val node = AHBSlaveIdentityNode() + val node = AHBSubordinateIdentityNode() val ram = LazyModule(new TLTestRAM(fuzzAddr, trackCorruption=false)) (ram.node @@ -97,14 +97,14 @@ class AHBFuzzSlave()(implicit p: Parameters) extends SimpleLazyModule with HasFu class AHBFuzzBridge(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule { - val master = LazyModule(new AHBFuzzMaster(aFlow, txns)) - val slave = LazyModule(new AHBFuzzSlave) + val manager = LazyModule(new AHBFuzzManager(aFlow, txns)) + val subordinate = LazyModule(new AHBFuzzSubordinate) - slave.node := master.node + subordinate.node := manager.node lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { - io.finished := master.module.io.finished + io.finished := manager.module.io.finished } } diff --git a/src/main/scala/amba/ahb/ToTL.scala b/src/main/scala/amba/ahb/ToTL.scala index e34d7c262ba..acf40f1618e 100644 --- a/src/main/scala/amba/ahb/ToTL.scala +++ b/src/main/scala/amba/ahb/ToTL.scala @@ -13,19 +13,19 @@ import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp} import freechips.rocketchip.amba.{AMBAProtField, AMBAProt} import freechips.rocketchip.diplomacy.TransferSizes -import freechips.rocketchip.tilelink.{TLImp, TLMasterPortParameters, TLMessages, TLMasterParameters, TLMasterToSlaveTransferSizes} +import freechips.rocketchip.tilelink.{TLImp, TLManagerPortParameters, TLMessages, TLManagerParameters, TLManagerToSubordinateTransferSizes} import freechips.rocketchip.util.{BundleMap, MaskGen, DataToAugmentedData} -case class AHBToTLNode()(implicit valName: ValName) extends MixedAdapterNode(AHBImpSlave, TLImp)( +case class AHBToTLNode()(implicit valName: ValName) extends MixedAdapterNode(AHBImpSubordinate, TLImp)( dFn = { case mp => - TLMasterPortParameters.v2( - masters = mp.masters.map { m => - // This value should be constrained by a data width parameter that flows from masters to slaves + TLManagerPortParameters.v2( + managers = mp.managers.map { m => + // This value should be constrained by a data width parameter that flows from managers to subordinates // AHB fixed length transfer size maximum is 16384 = 1024 * 16 bits, hsize is capped at 111 = 1024 bit transfer size and hburst is capped at 111 = 16 beat burst - TLMasterParameters.v2( + TLManagerParameters.v2( name = m.name, nodePath = m.nodePath, - emits = TLMasterToSlaveTransferSizes( + emits = TLManagerToSubordinateTransferSizes( get = TransferSizes(1, 2048), putFull = TransferSizes(1, 2048) ) @@ -34,8 +34,8 @@ case class AHBToTLNode()(implicit valName: ValName) extends MixedAdapterNode(AHB requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys) }, - uFn = { mp => AHBSlavePortParameters( - slaves = mp.managers.map { m => + uFn = { mp => AHBSubordinatePortParameters( + subordinates = mp.managers.map { m => def adjust(x: TransferSizes) = { if (x.contains(mp.beatBytes)) { TransferSizes(x.min, m.minAlignment.min(mp.beatBytes * AHBParameters.maxTransfer).toInt) @@ -44,7 +44,7 @@ case class AHBToTLNode()(implicit valName: ValName) extends MixedAdapterNode(AHB } } - AHBSlaveParameters( + AHBSubordinateParameters( address = m.address, resources = m.resources, regionType = m.regionType, @@ -148,7 +148,7 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule // We must accept the D-channel beat on the first cycle, as otherwise // the failure might be legally retracted on the second cycle. // Although the AHB spec says: - // "A slave only has to provide valid data when a transfer completes with + // "A subordinate only has to provide valid data when a transfer completes with // an OKAY response. ERROR responses do not require valid read data." // We choose, nevertheless, to provide the read data for the failed request. // Unfortunately, this comes at the cost of a bus-wide register. diff --git a/src/main/scala/amba/ahb/Xbar.scala b/src/main/scala/amba/ahb/Xbar.scala index d685ac1bed9..0415a4b42ca 100644 --- a/src/main/scala/amba/ahb/Xbar.scala +++ b/src/main/scala/amba/ahb/Xbar.scala @@ -14,10 +14,10 @@ import freechips.rocketchip.util.BundleField class AHBFanout()(implicit p: Parameters) extends LazyModule { val node = new AHBFanoutNode( - masterFn = { case Seq(m) => m }, - slaveFn = { seq => + managerFn = { case Seq(m) => m }, + subordinateFn = { seq => seq(0).copy( - slaves = seq.flatMap(_.slaves), + subordinates = seq.flatMap(_.subordinates), requestKeys = seq.flatMap(_.requestKeys).distinct, responseFields = BundleField.union(seq.flatMap(_.responseFields))) } ){ @@ -27,20 +27,20 @@ class AHBFanout()(implicit p: Parameters) extends LazyModule { lazy val module = new Impl class Impl extends LazyModuleImp(this) { if (node.edges.in.size >= 1) { - require (node.edges.in.size == 1, "AHBFanout does not support multiple masters") - require (node.edges.out.size > 0, "AHBFanout requires at least one slave") - node.edges.out.foreach { eo => require (eo.slave.lite, s"AHBFanout only supports AHB-Lite slaves (${eo.slave.slaves.map(_.name)})") } + require (node.edges.in.size == 1, "AHBFanout does not support multiple managers") + require (node.edges.out.size > 0, "AHBFanout requires at least one subordinate") + node.edges.out.foreach { eo => require (eo.subordinate.lite, s"AHBFanout only supports AHB-Lite subordinates (${eo.subordinate.subordinates.map(_.name)})") } // Require consistent bus widths val (io_out, edgesOut) = node.out.unzip - val port0 = edgesOut(0).slave + val port0 = edgesOut(0).subordinate edgesOut.foreach { edge => - val port = edge.slave + val port = edge.subordinate require (port.beatBytes == port0.beatBytes, - s"${port.slaves.map(_.name)} ${port.beatBytes} vs ${port0.slaves.map(_.name)} ${port0.beatBytes}") + s"${port.subordinates.map(_.name)} ${port.beatBytes} vs ${port0.subordinates.map(_.name)} ${port0.beatBytes}") } - val port_addrs = edgesOut.map(_.slave.slaves.map(_.address).flatten) + val port_addrs = edgesOut.map(_.subordinate.subordinates.map(_.address).flatten) val routingMask = AddressDecoder(port_addrs) val route_addrs = port_addrs.map(_.map(_.widen(~routingMask)).distinct) @@ -52,7 +52,7 @@ class AHBFanout()(implicit p: Parameters) extends LazyModule { (a_sel zip io_out) foreach { case (sel, out) => out.squeezeAll :<>= in.squeezeAll out.hsel := in.hsel && sel - out.hmaster.map { _ := 0.U } + out.hmanager.map { _ := 0.U } } in.hreadyout := !Mux1H(d_sel, io_out.map(!_.hreadyout)) @@ -64,14 +64,14 @@ class AHBFanout()(implicit p: Parameters) extends LazyModule { class AHBArbiter()(implicit p: Parameters) extends LazyModule { val node = AHBArbiterNode( - masterFn = { case seq => seq(0).copy(masters = seq.flatMap(_.masters)) }, - slaveFn = { case Seq(s) => s }) + managerFn = { case seq => seq(0).copy(managers = seq.flatMap(_.managers)) }, + subordinateFn = { case Seq(s) => s }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { if (node.edges.in.size >= 1) { - require (node.edges.out.size == 1, "AHBArbiter requires exactly one slave") - require (node.edges.in.size == 1, "TODO: support more than one master") + require (node.edges.out.size == 1, "AHBArbiter requires exactly one subordinate") + require (node.edges.in.size == 1, "TODO: support more than one manager") val (in, _) = node.in(0) val (out, _) = node.out(0) @@ -90,7 +90,7 @@ class AHBArbiter()(implicit p: Parameters) extends LazyModule { in.hrdata := out.hrdata in.hresp := out.hresp // zero-extended in.hgrant.foreach { _ := true.B } - out.hmaster.foreach { _ := 0.U } + out.hmanager.foreach { _ := 0.U } out.hauser :<= in.hauser in.hduser :<= out.hduser } diff --git a/src/main/scala/amba/ahb/package.scala b/src/main/scala/amba/ahb/package.scala index ffcf196951a..79db22bc878 100644 --- a/src/main/scala/amba/ahb/package.scala +++ b/src/main/scala/amba/ahb/package.scala @@ -6,10 +6,10 @@ import org.chipsalliance.diplomacy.nodes.{InwardNodeHandle, OutwardNodeHandle, S package object ahb { - type AHBSlaveOutwardNode = OutwardNodeHandle[AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBSlaveBundle] - type AHBSlaveInwardNode = InwardNodeHandle[AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBSlaveBundle] - type AHBSlaveNode = SimpleNodeHandle[AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBSlaveBundle] - type AHBMasterOutwardNode = OutwardNodeHandle[AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBMasterBundle] - type AHBMasterInwardNode = InwardNodeHandle[AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBMasterBundle] - type AHBMasterNode = SimpleNodeHandle[AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBMasterBundle] + type AHBSubordinateOutwardNode = OutwardNodeHandle[AHBManagerPortParameters, AHBSubordinatePortParameters, AHBEdgeParameters, AHBSubordinateBundle] + type AHBSubordinateInwardNode = InwardNodeHandle[AHBManagerPortParameters, AHBSubordinatePortParameters, AHBEdgeParameters, AHBSubordinateBundle] + type AHBSubordinateNode = SimpleNodeHandle[AHBManagerPortParameters, AHBSubordinatePortParameters, AHBEdgeParameters, AHBSubordinateBundle] + type AHBManagerOutwardNode = OutwardNodeHandle[AHBManagerPortParameters, AHBSubordinatePortParameters, AHBEdgeParameters, AHBManagerBundle] + type AHBManagerInwardNode = InwardNodeHandle[AHBManagerPortParameters, AHBSubordinatePortParameters, AHBEdgeParameters, AHBManagerBundle] + type AHBManagerNode = SimpleNodeHandle[AHBManagerPortParameters, AHBSubordinatePortParameters, AHBEdgeParameters, AHBManagerBundle] } diff --git a/src/main/scala/amba/apb/Bundles.scala b/src/main/scala/amba/apb/Bundles.scala index 59129c15aa5..2236973c1b5 100644 --- a/src/main/scala/amba/apb/Bundles.scala +++ b/src/main/scala/amba/apb/Bundles.scala @@ -5,10 +5,10 @@ package freechips.rocketchip.amba.apb import chisel3._ import freechips.rocketchip.util._ -// Signal directions are from the master's point-of-view +// Signal directions are from the manager's point-of-view class APBBundle(val params: APBBundleParameters) extends Bundle { - // Flow control signals from the master + // Flow control signals from the manager val psel = Output(Bool()) val penable = Output(Bool()) diff --git a/src/main/scala/amba/apb/Nodes.scala b/src/main/scala/amba/apb/Nodes.scala index e2dd9307c74..eaf97f77d2b 100644 --- a/src/main/scala/amba/apb/Nodes.scala +++ b/src/main/scala/amba/apb/Nodes.scala @@ -12,11 +12,11 @@ import org.chipsalliance.diplomacy.nodes.{SimpleNodeImp,RenderedEdge, InwardNode case object APBMonitorBuilder extends Field[APBMonitorArgs => APBMonitorBase] -object APBImp extends SimpleNodeImp[APBMasterPortParameters, APBSlavePortParameters, APBEdgeParameters, APBBundle] +object APBImp extends SimpleNodeImp[APBManagerPortParameters, APBSubordinatePortParameters, APBEdgeParameters, APBBundle] { - def edge(pd: APBMasterPortParameters, pu: APBSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = APBEdgeParameters(pd, pu, p, sourceInfo) + def edge(pd: APBManagerPortParameters, pu: APBSubordinatePortParameters, p: Parameters, sourceInfo: SourceInfo) = APBEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: APBEdgeParameters) = APBBundle(e.bundle) - def render(e: APBEdgeParameters) = RenderedEdge(colour = "#00ccff" /* bluish */, (e.slave.beatBytes * 8).toString) + def render(e: APBEdgeParameters) = RenderedEdge(colour = "#00ccff" /* bluish */, (e.subordinate.beatBytes * 8).toString) override def monitor(bundle: APBBundle, edge: APBEdgeParameters): Unit = { edge.params.lift(APBMonitorBuilder).foreach { builder => @@ -25,18 +25,18 @@ object APBImp extends SimpleNodeImp[APBMasterPortParameters, APBSlavePortParamet } } - override def mixO(pd: APBMasterPortParameters, node: OutwardNode[APBMasterPortParameters, APBSlavePortParameters, APBBundle]): APBMasterPortParameters = - pd.copy(masters = pd.masters.map { c => c.copy (nodePath = node +: c.nodePath) }) - override def mixI(pu: APBSlavePortParameters, node: InwardNode[APBMasterPortParameters, APBSlavePortParameters, APBBundle]): APBSlavePortParameters = - pu.copy(slaves = pu.slaves.map { m => m.copy (nodePath = node +: m.nodePath) }) + override def mixO(pd: APBManagerPortParameters, node: OutwardNode[APBManagerPortParameters, APBSubordinatePortParameters, APBBundle]): APBManagerPortParameters = + pd.copy(managers = pd.managers.map { c => c.copy (nodePath = node +: c.nodePath) }) + override def mixI(pu: APBSubordinatePortParameters, node: InwardNode[APBManagerPortParameters, APBSubordinatePortParameters, APBBundle]): APBSubordinatePortParameters = + pu.copy(subordinates = pu.subordinates.map { m => m.copy (nodePath = node +: m.nodePath) }) } -case class APBMasterNode(portParams: Seq[APBMasterPortParameters])(implicit valName: ValName) extends SourceNode(APBImp)(portParams) -case class APBSlaveNode(portParams: Seq[APBSlavePortParameters])(implicit valName: ValName) extends SinkNode(APBImp)(portParams) +case class APBManagerNode(portParams: Seq[APBManagerPortParameters])(implicit valName: ValName) extends SourceNode(APBImp)(portParams) +case class APBSubordinateNode(portParams: Seq[APBSubordinatePortParameters])(implicit valName: ValName) extends SinkNode(APBImp)(portParams) case class APBNexusNode( - masterFn: Seq[APBMasterPortParameters] => APBMasterPortParameters, - slaveFn: Seq[APBSlavePortParameters] => APBSlavePortParameters)( + managerFn: Seq[APBManagerPortParameters] => APBManagerPortParameters, + subordinateFn: Seq[APBSubordinatePortParameters] => APBSubordinatePortParameters)( implicit valName: ValName) - extends NexusNode(APBImp)(masterFn, slaveFn) + extends NexusNode(APBImp)(managerFn, subordinateFn) case class APBIdentityNode()(implicit valName: ValName) extends IdentityNode(APBImp)() diff --git a/src/main/scala/amba/apb/Parameters.scala b/src/main/scala/amba/apb/Parameters.scala index f39c8b03fef..dbc9ae4678c 100644 --- a/src/main/scala/amba/apb/Parameters.scala +++ b/src/main/scala/amba/apb/Parameters.scala @@ -15,7 +15,7 @@ import freechips.rocketchip.util.{BundleField, BundleKeyBase, BundleFieldBase} import scala.math.max -case class APBSlaveParameters( +case class APBSubordinateParameters( address: Seq[AddressSet], resources: Seq[Resource] = Nil, regionType: RegionType.T = RegionType.GET_EFFECTS, @@ -42,31 +42,31 @@ case class APBSlaveParameters( } } -case class APBSlavePortParameters( - slaves: Seq[APBSlaveParameters], +case class APBSubordinatePortParameters( + subordinates: Seq[APBSubordinateParameters], beatBytes: Int, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) { - require (!slaves.isEmpty) + require (!subordinates.isEmpty) require (isPow2(beatBytes)) - val maxAddress = slaves.map(_.maxAddress).max + val maxAddress = subordinates.map(_.maxAddress).max // Require disjoint ranges for addresses - slaves.combinations(2).foreach { case Seq(x,y) => + subordinates.combinations(2).foreach { case Seq(x,y) => x.address.foreach { a => y.address.foreach { b => require (!a.overlaps(b)) } } } } -case class APBMasterParameters( +case class APBManagerParameters( name: String, nodePath: Seq[BaseNode] = Seq()) -case class APBMasterPortParameters( - masters: Seq[APBMasterParameters], +case class APBManagerPortParameters( + managers: Seq[APBManagerParameters], requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) @@ -96,19 +96,19 @@ object APBBundleParameters val emptyBundleParams = APBBundleParameters(addrBits = 1, dataBits = 8, requestFields = Nil, responseFields = Nil) def union(x: Seq[APBBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) - def apply(master: APBMasterPortParameters, slave: APBSlavePortParameters) = + def apply(manager: APBManagerPortParameters, subordinate: APBSubordinatePortParameters) = new APBBundleParameters( - addrBits = log2Up(slave.maxAddress+1), - dataBits = slave.beatBytes * 8, - requestFields = BundleField.accept(master.requestFields, slave.requestKeys), - responseFields = BundleField.accept(slave.responseFields, master.responseKeys)) + addrBits = log2Up(subordinate.maxAddress+1), + dataBits = subordinate.beatBytes * 8, + requestFields = BundleField.accept(manager.requestFields, subordinate.requestKeys), + responseFields = BundleField.accept(subordinate.responseFields, manager.responseKeys)) } case class APBEdgeParameters( - master: APBMasterPortParameters, - slave: APBSlavePortParameters, + manager: APBManagerPortParameters, + subordinate: APBSubordinatePortParameters, params: Parameters, sourceInfo: SourceInfo) { - val bundle = APBBundleParameters(master, slave) + val bundle = APBBundleParameters(manager, subordinate) } diff --git a/src/main/scala/amba/apb/RegisterRouter.scala b/src/main/scala/amba/apb/RegisterRouter.scala index 07b62a5c67b..c597aea970f 100644 --- a/src/main/scala/amba/apb/RegisterRouter.scala +++ b/src/main/scala/amba/apb/RegisterRouter.scala @@ -15,8 +15,8 @@ import freechips.rocketchip.regmapper.{RegField, RegMapperParams, RegMapperInput import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple} case class APBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)(implicit valName: ValName) - extends SinkNode(APBImp)(Seq(APBSlavePortParameters( - Seq(APBSlaveParameters( + extends SinkNode(APBImp)(Seq(APBSubordinatePortParameters( + Seq(APBSubordinateParameters( address = Seq(address), executable = executable, supportsWrite = true, diff --git a/src/main/scala/amba/apb/SRAM.scala b/src/main/scala/amba/apb/SRAM.scala index 8c5a9c27487..081bc4bb7ec 100644 --- a/src/main/scala/amba/apb/SRAM.scala +++ b/src/main/scala/amba/apb/SRAM.scala @@ -25,8 +25,8 @@ class APBRAM( fuzzError: Boolean = false) (implicit p: Parameters) extends DiplomaticSRAM(address, beatBytes, devName) { - val node = APBSlaveNode(Seq(APBSlavePortParameters( - Seq(APBSlaveParameters( + val node = APBSubordinateNode(Seq(APBSubordinatePortParameters( + Seq(APBSubordinateParameters( address = List(address) ++ errors, resources = resources, regionType = if (cacheable) RegionType.UNCACHED else RegionType.IDEMPOTENT, diff --git a/src/main/scala/amba/apb/Test.scala b/src/main/scala/amba/apb/Test.scala index 0c907079b89..8fb04adf4ad 100644 --- a/src/main/scala/amba/apb/Test.scala +++ b/src/main/scala/amba/apb/Test.scala @@ -24,7 +24,7 @@ class APBRRTest1(address: BigInt)(implicit p: Parameters) class APBFuzzBridge(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) - val model = LazyModule(new TLRAMModel("APBFuzzMaster")) + val model = LazyModule(new TLRAMModel("APBFuzzManager")) val xbar = LazyModule(new APBFanout) val ram = LazyModule(new APBRAM(AddressSet(0x0, 0xff), fuzzReady = true, fuzzError = true)) val gpio = LazyModule(new APBRRTest0(0x100)) diff --git a/src/main/scala/amba/apb/ToTL.scala b/src/main/scala/amba/apb/ToTL.scala index 39d01ab5515..6b9ddaa4ddc 100644 --- a/src/main/scala/amba/apb/ToTL.scala +++ b/src/main/scala/amba/apb/ToTL.scala @@ -13,20 +13,20 @@ import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp} import freechips.rocketchip.amba.{AMBAProt, AMBAProtField} import freechips.rocketchip.diplomacy.TransferSizes -import freechips.rocketchip.tilelink.{TLImp, TLMessages, TLMasterPortParameters, TLMasterParameters} +import freechips.rocketchip.tilelink.{TLImp, TLMessages, TLManagerPortParameters, TLManagerParameters} case class APBToTLNode()(implicit valName: ValName) extends MixedAdapterNode(APBImp, TLImp)( dFn = { mp => - TLMasterPortParameters.v1( - clients = mp.masters.map { m => - TLMasterParameters.v1(name = m.name, nodePath = m.nodePath) + TLManagerPortParameters.v1( + clients = mp.managers.map { m => + TLManagerParameters.v1(name = m.name, nodePath = m.nodePath) }, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys) }, - uFn = { mp => APBSlavePortParameters( - slaves = mp.managers.map { m => - APBSlaveParameters( + uFn = { mp => APBSubordinatePortParameters( + subordinates = mp.managers.map { m => + APBSubordinateParameters( address = m.address, resources = m.resources, regionType = m.regionType, diff --git a/src/main/scala/amba/apb/Xbar.scala b/src/main/scala/amba/apb/Xbar.scala index 3f50fbb4ea1..55a7b77b6ac 100644 --- a/src/main/scala/amba/apb/Xbar.scala +++ b/src/main/scala/amba/apb/Xbar.scala @@ -14,10 +14,10 @@ import freechips.rocketchip.util.BundleField class APBFanout()(implicit p: Parameters) extends LazyModule { val node = new APBNexusNode( - masterFn = { case Seq(m) => m }, - slaveFn = { seq => + managerFn = { case Seq(m) => m }, + subordinateFn = { seq => seq(0).copy( - slaves = seq.flatMap(_.slaves), + subordinates = seq.flatMap(_.subordinates), requestKeys = seq.flatMap(_.requestKeys).distinct, responseFields = BundleField.union(seq.flatMap(_.responseFields))) } ){ @@ -27,21 +27,21 @@ class APBFanout()(implicit p: Parameters) extends LazyModule { lazy val module = new Impl class Impl extends LazyModuleImp(this) { if (node.edges.in.size >= 1) { - require (node.edges.in.size == 1, "APBFanout does not support multiple masters") - require (node.edges.out.size > 0, "APBFanout requires at least one slave") + require (node.edges.in.size == 1, "APBFanout does not support multiple managers") + require (node.edges.out.size > 0, "APBFanout requires at least one subordinate") val (in, _) = node.in(0) // Require consistent bus widths val (io_out, edgesOut) = node.out.unzip - val port0 = edgesOut(0).slave + val port0 = edgesOut(0).subordinate edgesOut.foreach { edge => - val port = edge.slave + val port = edge.subordinate require (port.beatBytes == port0.beatBytes, - s"${port.slaves.map(_.name)} ${port.beatBytes} vs ${port0.slaves.map(_.name)} ${port0.beatBytes}") + s"${port.subordinates.map(_.name)} ${port.beatBytes} vs ${port0.subordinates.map(_.name)} ${port0.beatBytes}") } - val port_addrs = edgesOut.map(_.slave.slaves.map(_.address).flatten) + val port_addrs = edgesOut.map(_.subordinate.subordinates.map(_.address).flatten) val routingMask = AddressDecoder(port_addrs) val route_addrs = port_addrs.map(_.map(_.widen(~routingMask)).distinct) diff --git a/src/main/scala/amba/apb/package.scala b/src/main/scala/amba/apb/package.scala index 872fd22be23..d25ca58fca2 100644 --- a/src/main/scala/amba/apb/package.scala +++ b/src/main/scala/amba/apb/package.scala @@ -6,7 +6,7 @@ import org.chipsalliance.diplomacy.nodes.{InwardNodeHandle, OutwardNodeHandle, S package object apb { - type APBOutwardNode = OutwardNodeHandle[APBMasterPortParameters, APBSlavePortParameters, APBEdgeParameters, APBBundle] - type APBInwardNode = InwardNodeHandle[APBMasterPortParameters, APBSlavePortParameters, APBEdgeParameters, APBBundle] - type APBNode = SimpleNodeHandle[APBMasterPortParameters, APBSlavePortParameters, APBEdgeParameters, APBBundle] + type APBOutwardNode = OutwardNodeHandle[APBManagerPortParameters, APBSubordinatePortParameters, APBEdgeParameters, APBBundle] + type APBInwardNode = InwardNodeHandle[APBManagerPortParameters, APBSubordinatePortParameters, APBEdgeParameters, APBBundle] + type APBNode = SimpleNodeHandle[APBManagerPortParameters, APBSubordinatePortParameters, APBEdgeParameters, APBBundle] } diff --git a/src/main/scala/amba/axi4/AsyncCrossing.scala b/src/main/scala/amba/axi4/AsyncCrossing.scala index b9303e5c108..f3a5831060d 100644 --- a/src/main/scala/amba/axi4/AsyncCrossing.scala +++ b/src/main/scala/amba/axi4/AsyncCrossing.scala @@ -16,7 +16,7 @@ import freechips.rocketchip.subsystem.CrossingWrapper import freechips.rocketchip.util.{ToAsyncBundle, FromAsyncBundle, AsyncQueueParams, Pow2ClockDivider} /** - * Source(Master) side for AXI4 crossing clock domain + * Source(Manager) side for AXI4 crossing clock domain * * @param sync synchronization stages */ @@ -30,8 +30,8 @@ class AXI4AsyncCrossingSource(sync: Option[Int])(implicit p: Parameters) extends lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => - val psync = sync.getOrElse(edgeOut.slave.async.sync) - val params = edgeOut.slave.async.copy(sync = psync) + val psync = sync.getOrElse(edgeOut.subordinate.async.sync) + val params = edgeOut.subordinate.async.copy(sync = psync) out.ar <> ToAsyncBundle(in.ar, params) out.aw <> ToAsyncBundle(in.aw, params) out. w <> ToAsyncBundle(in. w, params) @@ -42,7 +42,7 @@ class AXI4AsyncCrossingSource(sync: Option[Int])(implicit p: Parameters) extends } /** - * Sink(Slave) side for AXI4 crossing clock domain + * Sink(Subordinate) side for AXI4 crossing clock domain * * @param params async queue params */ diff --git a/src/main/scala/amba/axi4/Buffer.scala b/src/main/scala/amba/axi4/Buffer.scala index 2b768e87ca5..c3acdf2bc69 100644 --- a/src/main/scala/amba/axi4/Buffer.scala +++ b/src/main/scala/amba/axi4/Buffer.scala @@ -30,8 +30,8 @@ class AXI4Buffer( def this()(implicit p: Parameters) = this(BufferParams.default) val node = AXI4AdapterNode( - masterFn = { p => p }, - slaveFn = { p => p.copy(minLatency = p.minLatency + min(aw.latency,ar.latency) + min(r.latency,b.latency)) }) + managerFn = { p => p }, + subordinateFn = { p => p.copy(minLatency = p.minLatency + min(aw.latency,ar.latency) + min(r.latency,b.latency)) }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { diff --git a/src/main/scala/amba/axi4/Credited.scala b/src/main/scala/amba/axi4/Credited.scala index 3dbea790f8b..2a7360dd15b 100644 --- a/src/main/scala/amba/axi4/Credited.scala +++ b/src/main/scala/amba/axi4/Credited.scala @@ -17,8 +17,8 @@ import freechips.rocketchip.util._ class AXI4CreditedBuffer(delay: AXI4CreditedDelay)(implicit p: Parameters) extends LazyModule { val node = AXI4CreditedAdapterNode( - masterFn = p => p.copy(delay = delay + p.delay), - slaveFn = p => p.copy(delay = delay + p.delay)) + managerFn = p => p.copy(delay = delay + p.delay), + subordinateFn = p => p.copy(delay = delay + p.delay)) lazy val module = new Impl class Impl extends LazyModuleImp(this) { diff --git a/src/main/scala/amba/axi4/Deinterleaver.scala b/src/main/scala/amba/axi4/Deinterleaver.scala index 461507a5e0c..cba24557f74 100644 --- a/src/main/scala/amba/axi4/Deinterleaver.scala +++ b/src/main/scala/amba/axi4/Deinterleaver.scala @@ -28,27 +28,27 @@ class AXI4Deinterleaver(maxReadBytes: Int, buffer: BufferParams = BufferParams.d require (maxReadBytes >= 1, s"AXI4Deinterleaver: maxReadBytes must be at least 1, not $maxReadBytes") require (isPow2(maxReadBytes), s"AXI4Deinterleaver: maxReadBytes must be a power of two, not $maxReadBytes") - private def maxBeats(slave: AXI4SlavePortParameters): Int = - (maxReadBytes+slave.beatBytes-1) / slave.beatBytes + private def maxBeats(subordinate: AXI4SubordinatePortParameters): Int = + (maxReadBytes+subordinate.beatBytes-1) / subordinate.beatBytes // Nothing to do if R channel only uses a single beat - private def nothingToDeinterleave(slave: AXI4SlavePortParameters): Boolean = - maxBeats(slave) <= 1 + private def nothingToDeinterleave(subordinate: AXI4SubordinatePortParameters): Boolean = + maxBeats(subordinate) <= 1 val node = new AXI4AdapterNode( - masterFn = { mp => mp }, - slaveFn = { sp => sp.copy(slaves = sp.slaves.map(s => s.copy( + managerFn = { mp => mp }, + subordinateFn = { sp => sp.copy(subordinates = sp.subordinates.map(s => s.copy( supportsRead = s.supportsRead.intersect(TransferSizes(1, maxReadBytes)), interleavedId = Some(0)))) }) { - override def circuitIdentity = edges.out.map(_.slave).forall(nothingToDeinterleave) + override def circuitIdentity = edges.out.map(_.subordinate).forall(nothingToDeinterleave) } lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => - val endId = edgeOut.master.endId - val beats = maxBeats(edgeOut.slave) + val endId = edgeOut.manager.endId + val beats = maxBeats(edgeOut.subordinate) // This adapter passes through the AR/AW control + W/B write data channels out.ar :<>= in.ar @@ -57,12 +57,12 @@ class AXI4Deinterleaver(maxReadBytes: Int, buffer: BufferParams = BufferParams.d in.b :<>= out.b // Only the R channel has the possibility of being changed - if (nothingToDeinterleave(edgeOut.slave)) { + if (nothingToDeinterleave(edgeOut.subordinate)) { in.r.asInstanceOf[ReadyValidIO[AXI4BundleR]] :<>= buffer.irrevocable(out.r) } else { // We only care to deinterleave ids that are actually in use val maxFlightPerId = Seq.tabulate(endId) { i => - edgeOut.master.masters.find(_.id.contains(i)).flatMap(_.maxFlight).getOrElse(0) + edgeOut.manager.managers.find(_.id.contains(i)).flatMap(_.maxFlight).getOrElse(0) } // Queues to buffer R responses diff --git a/src/main/scala/amba/axi4/Filter.scala b/src/main/scala/amba/axi4/Filter.scala index 9093aa05448..4523aef03a5 100644 --- a/src/main/scala/amba/axi4/Filter.scala +++ b/src/main/scala/amba/axi4/Filter.scala @@ -9,12 +9,12 @@ import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp} import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} class AXI4Filter( - Sfilter: AXI4SlaveParameters => Option[AXI4SlaveParameters] = AXI4Filter.Sidentity, - Mfilter: AXI4MasterParameters => Option[AXI4MasterParameters] = AXI4Filter.Midentity + Sfilter: AXI4SubordinateParameters => Option[AXI4SubordinateParameters] = AXI4Filter.Sidentity, + Mfilter: AXI4ManagerParameters => Option[AXI4ManagerParameters] = AXI4Filter.Midentity )(implicit p: Parameters) extends LazyModule { val node = AXI4AdapterNode( - slaveFn = { sp => sp.copy(slaves = sp.slaves.flatMap { s => + subordinateFn = { sp => sp.copy(subordinates = sp.subordinates.flatMap { s => val out = Sfilter(s) out.foreach { o => // Confirm the filter only REMOVES capability o.address.foreach { a => require (s.address.map(_.contains(a)).reduce(_||_)) } @@ -26,7 +26,7 @@ class AXI4Filter( } out })}, - masterFn = { mp => mp.copy(masters = mp.masters.flatMap { m => + managerFn = { mp => mp.copy(managers = mp.managers.flatMap { m => val out = Mfilter(m) out.foreach { o => require (m.id.contains(o.id)) } out @@ -42,9 +42,9 @@ class AXI4Filter( object AXI4Filter { - def Midentity: AXI4MasterParameters => Option[AXI4MasterParameters] = { m => Some(m) } - def Sidentity: AXI4SlaveParameters => Option[AXI4SlaveParameters] = { s => Some(s) } - def Smask(select: AddressSet): AXI4SlaveParameters => Option[AXI4SlaveParameters] = { s => + def Midentity: AXI4ManagerParameters => Option[AXI4ManagerParameters] = { m => Some(m) } + def Sidentity: AXI4SubordinateParameters => Option[AXI4SubordinateParameters] = { s => Some(s) } + def Smask(select: AddressSet): AXI4SubordinateParameters => Option[AXI4SubordinateParameters] = { s => val filtered = s.address.map(_.intersect(select)).flatten val alignment = select.alignment /* alignment 0 means 'select' selected everything */ val maxTransfer = 1 << 30 @@ -59,8 +59,8 @@ object AXI4Filter } def apply( - Sfilter: AXI4SlaveParameters => Option[AXI4SlaveParameters] = AXI4Filter.Sidentity, - Mfilter: AXI4MasterParameters => Option[AXI4MasterParameters] = AXI4Filter.Midentity + Sfilter: AXI4SubordinateParameters => Option[AXI4SubordinateParameters] = AXI4Filter.Sidentity, + Mfilter: AXI4ManagerParameters => Option[AXI4ManagerParameters] = AXI4Filter.Midentity )(implicit p: Parameters): AXI4Node = { val axi4filt = LazyModule(new AXI4Filter(Sfilter, Mfilter)) diff --git a/src/main/scala/amba/axi4/Fragmenter.scala b/src/main/scala/amba/axi4/Fragmenter.scala index 85505374088..3d19c81feb1 100644 --- a/src/main/scala/amba/axi4/Fragmenter.scala +++ b/src/main/scala/amba/axi4/Fragmenter.scala @@ -23,28 +23,28 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule val maxBeats = 1 << AXI4Parameters.lenBits def expandTransfer(x: TransferSizes, beatBytes: Int, alignment: BigInt) = if (!x) x else TransferSizes(x.min, alignment.min(maxBeats*beatBytes).intValue) - def mapSlave(s: AXI4SlaveParameters, beatBytes: Int) = s.copy( + def mapSubordinate(s: AXI4SubordinateParameters, beatBytes: Int) = s.copy( supportsWrite = expandTransfer(s.supportsWrite, beatBytes, s.minAlignment), supportsRead = expandTransfer(s.supportsRead, beatBytes, s.minAlignment), interleavedId = None) // this breaks interleaving guarantees - def mapMaster(m: AXI4MasterParameters) = m.copy(aligned = true, maxFlight = None) + def mapManager(m: AXI4ManagerParameters) = m.copy(aligned = true, maxFlight = None) val node = AXI4AdapterNode( - masterFn = { mp => mp.copy(masters = mp.masters.map(m => mapMaster(m)), echoFields = AXI4FragLastField() +: mp.echoFields) }, - slaveFn = { sp => sp.copy(slaves = sp.slaves .map(s => mapSlave(s, sp.beatBytes))) }) + managerFn = { mp => mp.copy(managers = mp.managers.map(m => mapManager(m)), echoFields = AXI4FragLastField() +: mp.echoFields) }, + subordinateFn = { sp => sp.copy(subordinates = sp.subordinates .map(s => mapSubordinate(s, sp.beatBytes))) }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => - val slave = edgeOut.slave - val slaves = slave.slaves - val beatBytes = slave.beatBytes + val subordinate = edgeOut.subordinate + val subordinates = subordinate.subordinates + val beatBytes = subordinate.beatBytes val lgBytes = log2Ceil(beatBytes) - val master = edgeIn.master - val masters = master.masters + val manager = edgeIn.manager + val managers = manager.managers // We don't support fragmenting to sub-beat accesses - slaves.foreach { s => + subordinates.foreach { s => require (!s.supportsRead || s.supportsRead.contains(beatBytes)) require (!s.supportsWrite || s.supportsWrite.contains(beatBytes)) } @@ -78,7 +78,7 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule // We don't care about illegal addresses; bursts or no bursts... whatever circuit is simpler (AXI4ToTL will fix it) // !!! think about this more -- what if illegal? - val sizes1 = (supportedSizes1 zip slave.slaves.map(_.address)).filter(_._1 >= 0).groupBy(_._1).mapValues(_.flatMap(_._2)) + val sizes1 = (supportedSizes1 zip subordinate.subordinates.map(_.address)).filter(_._1 >= 0).groupBy(_._1).mapValues(_.flatMap(_._2)) val reductionMask = AddressDecoder(sizes1.values.toList) val support1 = Mux1H(sizes1.toList.map { case (v, a) => // maximum supported size-1 based on target address (AddressSet.unify(a.map(_.widen(~reductionMask)).distinct).map(_.contains(addr)).reduce(_||_), v.U) @@ -139,8 +139,8 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule } // The size to which we will fragment the access - val readSizes1 = slaves.map(s => s.supportsRead .max/beatBytes-1) - val writeSizes1 = slaves.map(s => s.supportsWrite.max/beatBytes-1) + val readSizes1 = subordinates.map(s => s.supportsRead .max/beatBytes-1) + val writeSizes1 = subordinates.map(s => s.supportsWrite.max/beatBytes-1) // Irrevocable queues in front because we want to accept the request before responses come back val (in_ar, ar_last, _) = fragment(Queue.irrevocable(in.ar, 1, flow=true), readSizes1) @@ -208,9 +208,9 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule out.b.ready := in.b.ready || !b_last // Merge errors from dropped B responses - val error = RegInit(VecInit.fill(edgeIn.master.endId)(0.U(AXI4Parameters.respBits.W))) + val error = RegInit(VecInit.fill(edgeIn.manager.endId)(0.U(AXI4Parameters.respBits.W))) in.b.bits.resp := out.b.bits.resp | error(out.b.bits.id) - (error zip UIntToOH(out.b.bits.id, edgeIn.master.endId).asBools) foreach { case (reg, sel) => + (error zip UIntToOH(out.b.bits.id, edgeIn.manager.endId).asBools) foreach { case (reg, sel) => when (sel && out.b.fire) { reg := Mux(b_last, 0.U, reg | out.b.bits.resp) } } } diff --git a/src/main/scala/amba/axi4/IdIndexer.scala b/src/main/scala/amba/axi4/IdIndexer.scala index 4687d5dc0f8..807cbc6b516 100644 --- a/src/main/scala/amba/axi4/IdIndexer.scala +++ b/src/main/scala/amba/axi4/IdIndexer.scala @@ -28,23 +28,23 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule require (idBits >= 0, s"AXI4IdIndexer: idBits must be > 0, not $idBits") val node = AXI4AdapterNode( - masterFn = { mp => - // Create one new "master" per ID - val masters = Array.tabulate(1 << idBits) { i => AXI4MasterParameters( + managerFn = { mp => + // Create one new "manager" per ID + val managers = Array.tabulate(1 << idBits) { i => AXI4ManagerParameters( name = "", id = IdRange(i, i+1), aligned = true, maxFlight = Some(0)) } - // Accumulate the names of masters we squish + // Accumulate the names of managers we squish val names = Array.fill(1 << idBits) { new scala.collection.mutable.HashSet[String]() } - // Squash the information from original masters into new ID masters - mp.masters.foreach { m => + // Squash the information from original managers into new ID managers + mp.managers.foreach { m => for (i <- m.id.start until m.id.end) { val j = i % (1 << idBits) - val accumulated = masters(j) + val accumulated = managers(j) names(j) += m.name - masters(j) = accumulated.copy( + managers(j) = accumulated.copy( aligned = accumulated.aligned && m.aligned, maxFlight = accumulated.maxFlight.flatMap { o => m.maxFlight.map { n => o+n } }) } @@ -54,9 +54,9 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule val field = if (bits > 0) Seq(AXI4ExtraIdField(bits)) else Nil mp.copy( echoFields = field ++ mp.echoFields, - masters = masters.zip(finalNameStrings).map { case (m, n) => m.copy(name = n) }) + managers = managers.zip(finalNameStrings).map { case (m, n) => m.copy(name = n) }) }, - slaveFn = { sp => sp + subordinateFn = { sp => sp }) lazy val module = new Impl @@ -81,7 +81,7 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll } - val bits = log2Ceil(edgeIn.master.endId) - idBits + val bits = log2Ceil(edgeIn.manager.endId) - idBits if (bits > 0) { // (in.aX.bits.id >> idBits).width = bits > 0 out.ar.bits.echo(AXI4ExtraId) := in.ar.bits.id >> idBits diff --git a/src/main/scala/amba/axi4/Nodes.scala b/src/main/scala/amba/axi4/Nodes.scala index da53aa92ea6..78a2cf491c0 100644 --- a/src/main/scala/amba/axi4/Nodes.scala +++ b/src/main/scala/amba/axi4/Nodes.scala @@ -14,11 +14,11 @@ import freechips.rocketchip.util.AsyncQueueParams case object AXI4MonitorBuilder extends Field[AXI4MonitorArgs => AXI4MonitorBase] -object AXI4Imp extends SimpleNodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4Bundle] +object AXI4Imp extends SimpleNodeImp[AXI4ManagerPortParameters, AXI4SubordinatePortParameters, AXI4EdgeParameters, AXI4Bundle] { - def edge(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = AXI4EdgeParameters(pd, pu, p, sourceInfo) + def edge(pd: AXI4ManagerPortParameters, pu: AXI4SubordinatePortParameters, p: Parameters, sourceInfo: SourceInfo) = AXI4EdgeParameters(pd, pu, p, sourceInfo) def bundle(e: AXI4EdgeParameters) = AXI4Bundle(e.bundle) - def render(e: AXI4EdgeParameters) = RenderedEdge(colour = "#00ccff" /* bluish */, label = (e.slave.beatBytes * 8).toString) + def render(e: AXI4EdgeParameters) = RenderedEdge(colour = "#00ccff" /* bluish */, label = (e.subordinate.beatBytes * 8).toString) override def monitor(bundle: AXI4Bundle, edge: AXI4EdgeParameters): Unit = { edge.params.lift(AXI4MonitorBuilder).foreach { builder => @@ -27,24 +27,24 @@ object AXI4Imp extends SimpleNodeImp[AXI4MasterPortParameters, AXI4SlavePortPara } } - override def mixO(pd: AXI4MasterPortParameters, node: OutwardNode[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]): AXI4MasterPortParameters = - pd.copy(masters = pd.masters.map { c => c.copy (nodePath = node +: c.nodePath) }) - override def mixI(pu: AXI4SlavePortParameters, node: InwardNode[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]): AXI4SlavePortParameters = - pu.copy(slaves = pu.slaves.map { m => m.copy (nodePath = node +: m.nodePath) }) + override def mixO(pd: AXI4ManagerPortParameters, node: OutwardNode[AXI4ManagerPortParameters, AXI4SubordinatePortParameters, AXI4Bundle]): AXI4ManagerPortParameters = + pd.copy(managers = pd.managers.map { c => c.copy (nodePath = node +: c.nodePath) }) + override def mixI(pu: AXI4SubordinatePortParameters, node: InwardNode[AXI4ManagerPortParameters, AXI4SubordinatePortParameters, AXI4Bundle]): AXI4SubordinatePortParameters = + pu.copy(subordinates = pu.subordinates.map { m => m.copy (nodePath = node +: m.nodePath) }) } -case class AXI4MasterNode(portParams: Seq[AXI4MasterPortParameters])(implicit valName: ValName) extends SourceNode(AXI4Imp)(portParams) -case class AXI4SlaveNode(portParams: Seq[AXI4SlavePortParameters])(implicit valName: ValName) extends SinkNode(AXI4Imp)(portParams) +case class AXI4ManagerNode(portParams: Seq[AXI4ManagerPortParameters])(implicit valName: ValName) extends SourceNode(AXI4Imp)(portParams) +case class AXI4SubordinateNode(portParams: Seq[AXI4SubordinatePortParameters])(implicit valName: ValName) extends SinkNode(AXI4Imp)(portParams) case class AXI4NexusNode( - masterFn: Seq[AXI4MasterPortParameters] => AXI4MasterPortParameters, - slaveFn: Seq[AXI4SlavePortParameters] => AXI4SlavePortParameters)( + managerFn: Seq[AXI4ManagerPortParameters] => AXI4ManagerPortParameters, + subordinateFn: Seq[AXI4SubordinatePortParameters] => AXI4SubordinatePortParameters)( implicit valName: ValName) - extends NexusNode(AXI4Imp)(masterFn, slaveFn) + extends NexusNode(AXI4Imp)(managerFn, subordinateFn) case class AXI4AdapterNode( - masterFn: AXI4MasterPortParameters => AXI4MasterPortParameters = { m => m }, - slaveFn: AXI4SlavePortParameters => AXI4SlavePortParameters = { s => s })( + managerFn: AXI4ManagerPortParameters => AXI4ManagerPortParameters = { m => m }, + subordinateFn: AXI4SubordinatePortParameters => AXI4SubordinatePortParameters = { s => s })( implicit valName: ValName) - extends AdapterNode(AXI4Imp)(masterFn, slaveFn) + extends AdapterNode(AXI4Imp)(managerFn, subordinateFn) case class AXI4IdentityNode()(implicit valName: ValName) extends IdentityNode(AXI4Imp)() object AXI4NameNode { @@ -53,27 +53,27 @@ object AXI4NameNode { def apply(name: String): AXI4IdentityNode = apply(Some(name)) } -object AXI4AsyncImp extends SimpleNodeImp[AXI4AsyncMasterPortParameters, AXI4AsyncSlavePortParameters, AXI4AsyncEdgeParameters, AXI4AsyncBundle] +object AXI4AsyncImp extends SimpleNodeImp[AXI4AsyncManagerPortParameters, AXI4AsyncSubordinatePortParameters, AXI4AsyncEdgeParameters, AXI4AsyncBundle] { - def edge(pd: AXI4AsyncMasterPortParameters, pu: AXI4AsyncSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = AXI4AsyncEdgeParameters(pd, pu, p, sourceInfo) + def edge(pd: AXI4AsyncManagerPortParameters, pu: AXI4AsyncSubordinatePortParameters, p: Parameters, sourceInfo: SourceInfo) = AXI4AsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: AXI4AsyncEdgeParameters) = new AXI4AsyncBundle(e.bundle) - def render(e: AXI4AsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.slave.async.depth.toString) + def render(e: AXI4AsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.subordinate.async.depth.toString) - override def mixO(pd: AXI4AsyncMasterPortParameters, node: OutwardNode[AXI4AsyncMasterPortParameters, AXI4AsyncSlavePortParameters, AXI4AsyncBundle]): AXI4AsyncMasterPortParameters = - pd.copy(base = pd.base.copy(masters = pd.base.masters.map { c => c.copy (nodePath = node +: c.nodePath) })) - override def mixI(pu: AXI4AsyncSlavePortParameters, node: InwardNode[AXI4AsyncMasterPortParameters, AXI4AsyncSlavePortParameters, AXI4AsyncBundle]): AXI4AsyncSlavePortParameters = - pu.copy(base = pu.base.copy(slaves = pu.base.slaves.map { m => m.copy (nodePath = node +: m.nodePath) })) + override def mixO(pd: AXI4AsyncManagerPortParameters, node: OutwardNode[AXI4AsyncManagerPortParameters, AXI4AsyncSubordinatePortParameters, AXI4AsyncBundle]): AXI4AsyncManagerPortParameters = + pd.copy(base = pd.base.copy(managers = pd.base.managers.map { c => c.copy (nodePath = node +: c.nodePath) })) + override def mixI(pu: AXI4AsyncSubordinatePortParameters, node: InwardNode[AXI4AsyncManagerPortParameters, AXI4AsyncSubordinatePortParameters, AXI4AsyncBundle]): AXI4AsyncSubordinatePortParameters = + pu.copy(base = pu.base.copy(subordinates = pu.base.subordinates.map { m => m.copy (nodePath = node +: m.nodePath) })) } case class AXI4AsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, AXI4AsyncImp)( - dFn = { p => AXI4AsyncMasterPortParameters(p) }, + dFn = { p => AXI4AsyncManagerPortParameters(p) }, uFn = { p => p.base.copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) case class AXI4AsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(AXI4AsyncImp, AXI4Imp)( dFn = { p => p.base }, - uFn = { p => AXI4AsyncSlavePortParameters(async, p) }) + uFn = { p => AXI4AsyncSubordinatePortParameters(async, p) }) case class AXI4AsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(AXI4AsyncImp)() @@ -83,33 +83,33 @@ object AXI4AsyncNameNode { def apply(name: String): AXI4AsyncIdentityNode = apply(Some(name)) } -object AXI4CreditedImp extends SimpleNodeImp[AXI4CreditedMasterPortParameters, AXI4CreditedSlavePortParameters, AXI4CreditedEdgeParameters, AXI4CreditedBundle] +object AXI4CreditedImp extends SimpleNodeImp[AXI4CreditedManagerPortParameters, AXI4CreditedSubordinatePortParameters, AXI4CreditedEdgeParameters, AXI4CreditedBundle] { - def edge(pd: AXI4CreditedMasterPortParameters, pu: AXI4CreditedSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = AXI4CreditedEdgeParameters(pd, pu, p, sourceInfo) + def edge(pd: AXI4CreditedManagerPortParameters, pu: AXI4CreditedSubordinatePortParameters, p: Parameters, sourceInfo: SourceInfo) = AXI4CreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: AXI4CreditedEdgeParameters) = new AXI4CreditedBundle(e.bundle) def render(e: AXI4CreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, label = e.delay.toString) - override def mixO(pd: AXI4CreditedMasterPortParameters, node: OutwardNode[AXI4CreditedMasterPortParameters, AXI4CreditedSlavePortParameters, AXI4CreditedBundle]): AXI4CreditedMasterPortParameters = - pd.copy(base = pd.base.copy(masters = pd.base.masters.map { c => c.copy (nodePath = node +: c.nodePath) })) - override def mixI(pu: AXI4CreditedSlavePortParameters, node: InwardNode[AXI4CreditedMasterPortParameters, AXI4CreditedSlavePortParameters, AXI4CreditedBundle]): AXI4CreditedSlavePortParameters = - pu.copy(base = pu.base.copy(slaves = pu.base.slaves.map { m => m.copy (nodePath = node +: m.nodePath) })) + override def mixO(pd: AXI4CreditedManagerPortParameters, node: OutwardNode[AXI4CreditedManagerPortParameters, AXI4CreditedSubordinatePortParameters, AXI4CreditedBundle]): AXI4CreditedManagerPortParameters = + pd.copy(base = pd.base.copy(managers = pd.base.managers.map { c => c.copy (nodePath = node +: c.nodePath) })) + override def mixI(pu: AXI4CreditedSubordinatePortParameters, node: InwardNode[AXI4CreditedManagerPortParameters, AXI4CreditedSubordinatePortParameters, AXI4CreditedBundle]): AXI4CreditedSubordinatePortParameters = + pu.copy(base = pu.base.copy(subordinates = pu.base.subordinates.map { m => m.copy (nodePath = node +: m.nodePath) })) } case class AXI4CreditedSourceNode(delay: AXI4CreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, AXI4CreditedImp)( - dFn = { p => AXI4CreditedMasterPortParameters(delay, p) }, + dFn = { p => AXI4CreditedManagerPortParameters(delay, p) }, uFn = { p => p.base.copy(minLatency = 1) }) case class AXI4CreditedSinkNode(delay: AXI4CreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(AXI4CreditedImp, AXI4Imp)( dFn = { p => p.base }, - uFn = { p => AXI4CreditedSlavePortParameters(delay, p) }) + uFn = { p => AXI4CreditedSubordinatePortParameters(delay, p) }) case class AXI4CreditedAdapterNode( - masterFn: AXI4CreditedMasterPortParameters => AXI4CreditedMasterPortParameters = { s => s }, - slaveFn: AXI4CreditedSlavePortParameters => AXI4CreditedSlavePortParameters = { s => s })( + managerFn: AXI4CreditedManagerPortParameters => AXI4CreditedManagerPortParameters = { s => s }, + subordinateFn: AXI4CreditedSubordinatePortParameters => AXI4CreditedSubordinatePortParameters = { s => s })( implicit valName: ValName) - extends AdapterNode(AXI4CreditedImp)(masterFn, slaveFn) + extends AdapterNode(AXI4CreditedImp)(managerFn, subordinateFn) case class AXI4CreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(AXI4CreditedImp)() diff --git a/src/main/scala/amba/axi4/Parameters.scala b/src/main/scala/amba/axi4/Parameters.scala index 088c226d825..267897c60e8 100644 --- a/src/main/scala/amba/axi4/Parameters.scala +++ b/src/main/scala/amba/axi4/Parameters.scala @@ -16,14 +16,14 @@ import freechips.rocketchip.util.{BundleField, BundleFieldBase, BundleKeyBase, A import scala.math.max /** - * Parameters for AXI4 slave + * Parameters for AXI4 subordinate * * @param address base address * @param resources device tree resource * @param regionType memory region type * @param executable whether processor can execute from this memory */ -case class AXI4SlaveParameters( +case class AXI4SubordinateParameters( address: Seq[AddressSet], resources: Seq[Resource] = Nil, regionType: RegionType.T = RegionType.GET_EFFECTS, @@ -56,18 +56,18 @@ case class AXI4SlaveParameters( } } -case class AXI4SlavePortParameters( - slaves: Seq[AXI4SlaveParameters], +case class AXI4SubordinatePortParameters( + subordinates: Seq[AXI4SubordinateParameters], beatBytes: Int, minLatency: Int = 1, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) { - require (!slaves.isEmpty) + require (!subordinates.isEmpty) require (isPow2(beatBytes)) - val maxTransfer = slaves.map(_.maxTransfer).max - val maxAddress = slaves.map(_.maxAddress).max + val maxTransfer = subordinates.map(_.maxTransfer).max + val maxAddress = subordinates.map(_.maxAddress).max // Check the link is not pointlessly wide require (maxTransfer >= beatBytes, @@ -78,14 +78,14 @@ case class AXI4SlavePortParameters( s"maxTransfer ($maxTransfer) cannot be larger than $limit on a $beatBytes*8 width bus") // Require disjoint ranges for addresses - slaves.combinations(2).foreach { case Seq(x,y) => + subordinates.combinations(2).foreach { case Seq(x,y) => x.address.foreach { a => y.address.foreach { b => require (!a.overlaps(b), s"$a and $b overlap") } } } } -case class AXI4MasterParameters( +case class AXI4ManagerParameters( name: String, id: IdRange = IdRange(0, 1), aligned: Boolean = false, @@ -95,17 +95,17 @@ case class AXI4MasterParameters( maxFlight.foreach { m => require (m >= 0) } } -case class AXI4MasterPortParameters( - masters: Seq[AXI4MasterParameters], +case class AXI4ManagerPortParameters( + managers: Seq[AXI4ManagerParameters], echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) { - val endId = masters.map(_.id.end).max + val endId = managers.map(_.id.end).max // Require disjoint ranges for ids - IdRange.overlaps(masters.map(_.id)).foreach { case (x, y) => - require (!x.overlaps(y), s"AXI4MasterParameters.id $x and $y overlap") + IdRange.overlaps(managers.map(_.id)).foreach { case (x, y) => + require (!x.overlaps(y), s"AXI4ManagerParameters.id $x and $y overlap") } } @@ -148,32 +148,32 @@ object AXI4BundleParameters val emptyBundleParams = AXI4BundleParameters(addrBits=1, dataBits=8, idBits=1, echoFields=Nil, requestFields=Nil, responseFields=Nil) def union(x: Seq[AXI4BundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) - def apply(master: AXI4MasterPortParameters, slave: AXI4SlavePortParameters) = + def apply(manager: AXI4ManagerPortParameters, subordinate: AXI4SubordinatePortParameters) = new AXI4BundleParameters( - addrBits = log2Up(slave.maxAddress+1), - dataBits = slave.beatBytes * 8, - idBits = log2Up(master.endId), - echoFields = master.echoFields, - requestFields = BundleField.accept(master.requestFields, slave.requestKeys), - responseFields = BundleField.accept(slave.responseFields, master.responseKeys)) + addrBits = log2Up(subordinate.maxAddress+1), + dataBits = subordinate.beatBytes * 8, + idBits = log2Up(manager.endId), + echoFields = manager.echoFields, + requestFields = BundleField.accept(manager.requestFields, subordinate.requestKeys), + responseFields = BundleField.accept(subordinate.responseFields, manager.responseKeys)) } case class AXI4EdgeParameters( - master: AXI4MasterPortParameters, - slave: AXI4SlavePortParameters, + manager: AXI4ManagerPortParameters, + subordinate: AXI4SubordinatePortParameters, params: Parameters, sourceInfo: SourceInfo) { - val bundle = AXI4BundleParameters(master, slave) + val bundle = AXI4BundleParameters(manager, subordinate) } -case class AXI4AsyncSlavePortParameters(async: AsyncQueueParams, base: AXI4SlavePortParameters) -case class AXI4AsyncMasterPortParameters(base: AXI4MasterPortParameters) +case class AXI4AsyncSubordinatePortParameters(async: AsyncQueueParams, base: AXI4SubordinatePortParameters) +case class AXI4AsyncManagerPortParameters(base: AXI4ManagerPortParameters) case class AXI4AsyncBundleParameters(async: AsyncQueueParams, base: AXI4BundleParameters) -case class AXI4AsyncEdgeParameters(master: AXI4AsyncMasterPortParameters, slave: AXI4AsyncSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) +case class AXI4AsyncEdgeParameters(manager: AXI4AsyncManagerPortParameters, subordinate: AXI4AsyncSubordinatePortParameters, params: Parameters, sourceInfo: SourceInfo) { - val bundle = AXI4AsyncBundleParameters(slave.async, AXI4BundleParameters(master.base, slave.base)) + val bundle = AXI4AsyncBundleParameters(subordinate.async, AXI4BundleParameters(manager.base, subordinate.base)) } case class AXI4BufferParams( @@ -209,19 +209,19 @@ object AXI4CreditedDelay { def apply(delay: CreditedDelay): AXI4CreditedDelay = apply(delay, delay, delay.flip, delay, delay.flip) } -case class AXI4CreditedSlavePortParameters(delay: AXI4CreditedDelay, base: AXI4SlavePortParameters) -case class AXI4CreditedMasterPortParameters(delay: AXI4CreditedDelay, base: AXI4MasterPortParameters) -case class AXI4CreditedEdgeParameters(master: AXI4CreditedMasterPortParameters, slave: AXI4CreditedSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) +case class AXI4CreditedSubordinatePortParameters(delay: AXI4CreditedDelay, base: AXI4SubordinatePortParameters) +case class AXI4CreditedManagerPortParameters(delay: AXI4CreditedDelay, base: AXI4ManagerPortParameters) +case class AXI4CreditedEdgeParameters(manager: AXI4CreditedManagerPortParameters, subordinate: AXI4CreditedSubordinatePortParameters, params: Parameters, sourceInfo: SourceInfo) { - val delay = master.delay + slave.delay - val bundle = AXI4BundleParameters(master.base, slave.base) + val delay = manager.delay + subordinate.delay + val bundle = AXI4BundleParameters(manager.base, subordinate.base) } /** Pretty printing of AXI4 source id maps */ -class AXI4IdMap(axi4: AXI4MasterPortParameters) extends IdMap[AXI4IdMapEntry] { +class AXI4IdMap(axi4: AXI4ManagerPortParameters) extends IdMap[AXI4IdMapEntry] { private val axi4Digits = String.valueOf(axi4.endId-1).length() protected val fmt = s"\t[%${axi4Digits}d, %${axi4Digits}d) %s%s%s" - private val sorted = axi4.masters.sortBy(_.id) + private val sorted = axi4.managers.sortBy(_.id) val mapping: Seq[AXI4IdMapEntry] = sorted.map { case c => // to conservatively state max number of transactions, assume every id has up to c.maxFlight and reuses ids between AW and AR channels diff --git a/src/main/scala/amba/axi4/RegisterRouter.scala b/src/main/scala/amba/axi4/RegisterRouter.scala index be48fa2eaf9..768e1713c94 100644 --- a/src/main/scala/amba/axi4/RegisterRouter.scala +++ b/src/main/scala/amba/axi4/RegisterRouter.scala @@ -20,8 +20,8 @@ case object AXI4RRId extends ControlKey[UInt]("extra_id") case class AXI4RRIdField(width: Int) extends SimpleBundleField(AXI4RRId)(Output(UInt((1 max width).W)), 0.U) case class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)(implicit valName: ValName) - extends SinkNode(AXI4Imp)(Seq(AXI4SlavePortParameters( - Seq(AXI4SlaveParameters( + extends SinkNode(AXI4Imp)(Seq(AXI4SubordinatePortParameters( + Seq(AXI4SubordinateParameters( address = Seq(address), executable = executable, supportsWrite = TransferSizes(1, beatBytes), diff --git a/src/main/scala/amba/axi4/SRAM.scala b/src/main/scala/amba/axi4/SRAM.scala index f4838b73ab0..cb51029622a 100644 --- a/src/main/scala/amba/axi4/SRAM.scala +++ b/src/main/scala/amba/axi4/SRAM.scala @@ -15,10 +15,10 @@ import freechips.rocketchip.resources.{DiplomaticSRAM, HasJustOneSeqMem} import freechips.rocketchip.util.{BundleMap, SeqMemToAugmentedSeqMem} /** - * AXI4 slave device to provide a RAM storage + * AXI4 subordinate device to provide a RAM storage * * Setting wcorrupt=true is not enough to enable the w.user field - * You must also list AMBACorrupt in your master's requestFields + * You must also list AMBACorrupt in your manager's requestFields * * @param address address range * @param cacheable whether this ram is cacheable @@ -39,8 +39,8 @@ class AXI4RAM( wcorrupt: Boolean = true) (implicit p: Parameters) extends DiplomaticSRAM(address, beatBytes, devName) { - val node = AXI4SlaveNode(Seq(AXI4SlavePortParameters( - Seq(AXI4SlaveParameters( + val node = AXI4SubordinateNode(Seq(AXI4SubordinatePortParameters( + Seq(AXI4SubordinateParameters( address = List(address) ++ errors, resources = resources, regionType = if (cacheable) RegionType.UNCACHED else RegionType.IDEMPOTENT, diff --git a/src/main/scala/amba/axi4/Test.scala b/src/main/scala/amba/axi4/Test.scala index ccda7093807..e1101a9446b 100644 --- a/src/main/scala/amba/axi4/Test.scala +++ b/src/main/scala/amba/axi4/Test.scala @@ -100,11 +100,11 @@ trait HasFuzzTarget { AddressSet(0x900, ~0x900)) // ie: 0x900-0x9ff, 0xb00-0xbff, ... 0xf00-0xfff } -class AXI4FuzzMaster(txns: Int)(implicit p: Parameters) extends LazyModule with HasFuzzTarget +class AXI4FuzzManager(txns: Int)(implicit p: Parameters) extends LazyModule with HasFuzzTarget { val node = AXI4IdentityNode() val fuzz = LazyModule(new TLFuzzer(txns, overrideAddress = Some(fuzzAddr))) - val model = LazyModule(new TLRAMModel("AXI4FuzzMaster")) + val model = LazyModule(new TLRAMModel("AXI4FuzzManager")) (node := AXI4UserYanker() @@ -127,7 +127,7 @@ class AXI4FuzzMaster(txns: Int)(implicit p: Parameters) extends LazyModule with } } -class AXI4FuzzSlave()(implicit p: Parameters) extends SimpleLazyModule with HasFuzzTarget +class AXI4FuzzSubordinate()(implicit p: Parameters) extends SimpleLazyModule with HasFuzzTarget { val node = AXI4IdentityNode() val xbar = LazyModule(new TLXbar) @@ -151,14 +151,14 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends SimpleLazyModule with HasF class AXI4FuzzBridge(txns: Int)(implicit p: Parameters) extends LazyModule { - val master = LazyModule(new AXI4FuzzMaster(txns)) - val slave = LazyModule(new AXI4FuzzSlave) + val manager = LazyModule(new AXI4FuzzManager(txns)) + val subordinate = LazyModule(new AXI4FuzzSubordinate) - slave.node := master.node + subordinate.node := manager.node lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { - io.finished := master.module.io.finished + io.finished := manager.module.io.finished } } diff --git a/src/main/scala/amba/axi4/ToTL.scala b/src/main/scala/amba/axi4/ToTL.scala index 833be2e4e28..e59332111fe 100644 --- a/src/main/scala/amba/axi4/ToTL.scala +++ b/src/main/scala/amba/axi4/ToTL.scala @@ -13,7 +13,7 @@ import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp} import freechips.rocketchip.amba.{AMBACorrupt, AMBAProt, AMBAProtField} import freechips.rocketchip.diplomacy.{IdRange, IdMapEntry, TransferSizes} -import freechips.rocketchip.tilelink.{TLImp, TLMasterParameters, TLMasterPortParameters, TLArbiter} +import freechips.rocketchip.tilelink.{TLImp, TLManagerParameters, TLManagerPortParameters, TLArbiter} import freechips.rocketchip.util.{OH1ToUInt, UIntToOH1} case class AXI4ToTLIdMapEntry(tlId: IdRange, axi4Id: IdRange, name: String) @@ -28,12 +28,12 @@ case class AXI4ToTLIdMapEntry(tlId: IdRange, axi4Id: IdRange, name: String) case class AXI4ToTLNode(wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => - mp.masters.foreach { m => require (m.maxFlight.isDefined, "AXI4 must include a transaction maximum per ID to convert to TL") } - val maxFlight = mp.masters.map(_.maxFlight.get).max - TLMasterPortParameters.v1( - clients = mp.masters.filter(_.maxFlight != Some(0)).flatMap { m => + mp.managers.foreach { m => require (m.maxFlight.isDefined, "AXI4 must include a transaction maximum per ID to convert to TL") } + val maxFlight = mp.managers.map(_.maxFlight.get).max + TLManagerPortParameters.v1( + clients = mp.managers.filter(_.maxFlight != Some(0)).flatMap { m => for (id <- m.id.start until m.id.end) - yield TLMasterParameters.v1( + yield TLManagerParameters.v1( name = s"${m.name} ID#${id}", sourceId = IdRange(id * maxFlight*2, (id+1) * maxFlight*2), // R+W ids are distinct nodePath = m.nodePath, @@ -43,10 +43,10 @@ case class AXI4ToTLNode(wcorrupt: Boolean)(implicit valName: ValName) extends Mi requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys) }, - uFn = { mp => AXI4SlavePortParameters( - slaves = mp.managers.map { m => + uFn = { mp => AXI4SubordinatePortParameters( + subordinates = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) - AXI4SlaveParameters( + AXI4SubordinateParameters( address = m.address, resources = m.resources, regionType = m.regionType, @@ -62,12 +62,12 @@ case class AXI4ToTLNode(wcorrupt: Boolean)(implicit valName: ValName) extends Mi }) /** - * Convert AXI4 master to TileLink. + * Convert AXI4 manager to TileLink. * - * You can use this adapter to connect external AXI4 masters to TileLink bus topology. + * You can use this adapter to connect external AXI4 managers to TileLink bus topology. * * Setting wcorrupt=true is insufficient to enable w.user.corrupt. - * One must additionally list it in the AXI4 master's requestFields. + * One must additionally list it in the AXI4 manager's requestFields. * * @param wcorrupt enable AMBACorrupt in w.user */ @@ -78,15 +78,15 @@ class AXI4ToTL(wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => - val numIds = edgeIn.master.endId + val numIds = edgeIn.manager.endId val beatBytes = edgeOut.manager.beatBytes val beatCountBits = AXI4Parameters.lenBits + (1 << AXI4Parameters.sizeBits) - 1 - val maxFlight = edgeIn.master.masters.map(_.maxFlight.get).max + val maxFlight = edgeIn.manager.managers.map(_.maxFlight.get).max val logFlight = log2Ceil(maxFlight) val txnCountBits = log2Ceil(maxFlight+1) // wrap-around must not block b_allow val addedBits = logFlight + 1 // +1 for read vs. write source ID - require (edgeIn.master.masters(0).aligned) + require (edgeIn.manager.managers(0).aligned) edgeOut.manager.requireFifo() // Look for an Error device to redirect bad requests diff --git a/src/main/scala/amba/axi4/UserYanker.scala b/src/main/scala/amba/axi4/UserYanker.scala index 93e69cd4b92..8b325d3dc5b 100644 --- a/src/main/scala/amba/axi4/UserYanker.scala +++ b/src/main/scala/amba/axi4/UserYanker.scala @@ -22,29 +22,29 @@ import freechips.rocketchip.util.BundleMap class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) extends LazyModule { val node = AXI4AdapterNode( - masterFn = { mp => mp.copy( - masters = mp.masters.map { m => m.copy( + managerFn = { mp => mp.copy( + managers = mp.managers.map { m => m.copy( maxFlight = (m.maxFlight, capMaxFlight) match { case (Some(x), Some(y)) => Some(x min y) case (Some(x), None) => Some(x) case (None, Some(y)) => Some(y) case (None, None) => None })}, echoFields = Nil)}, - slaveFn = { sp => sp }) + subordinateFn = { sp => sp }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // Which fields are we stripping? - val echoFields = edgeIn.master.echoFields - val need_bypass = edgeOut.slave.minLatency < 1 + val echoFields = edgeIn.manager.echoFields + val need_bypass = edgeOut.subordinate.minLatency < 1 - edgeOut.master.masters.foreach { m => + edgeOut.manager.managers.foreach { m => require (m.maxFlight.isDefined, "UserYanker needs a flight cap on each ID") } def queue(id: Int) = { - val depth = edgeOut.master.masters.find(_.id.contains(id)).flatMap(_.maxFlight).getOrElse(0) + val depth = edgeOut.manager.managers.find(_.id.contains(id)).flatMap(_.maxFlight).getOrElse(0) if (depth == 0) { Wire(new QueueIO(BundleMap(echoFields), 1)) // unused ID => undefined value } else { @@ -52,8 +52,8 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e } } - val rqueues = Seq.tabulate(edgeIn.master.endId) { i => queue(i) } - val wqueues = Seq.tabulate(edgeIn.master.endId) { i => queue(i) } + val rqueues = Seq.tabulate(edgeIn.manager.endId) { i => queue(i) } + val wqueues = Seq.tabulate(edgeIn.manager.endId) { i => queue(i) } val arid = in.ar.bits.id val ar_ready = VecInit(rqueues.map(_.enq.ready))(arid) @@ -72,8 +72,8 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e } in.r.bits.echo :<= r_bits - val arsel = UIntToOH(arid, edgeIn.master.endId).asBools - val rsel = UIntToOH(rid, edgeIn.master.endId).asBools + val arsel = UIntToOH(arid, edgeIn.manager.endId).asBools + val rsel = UIntToOH(rid, edgeIn.manager.endId).asBools (rqueues zip (arsel zip rsel)) foreach { case (q, (ar, r)) => q.deq.ready := out.r .valid && in .r .ready && r && out.r.bits.last q.deq.valid := DontCare @@ -101,8 +101,8 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e } in.b.bits.echo :<>= b_bits - val awsel = UIntToOH(awid, edgeIn.master.endId).asBools - val bsel = UIntToOH(bid, edgeIn.master.endId).asBools + val awsel = UIntToOH(awid, edgeIn.manager.endId).asBools + val bsel = UIntToOH(bid, edgeIn.manager.endId).asBools (wqueues zip (awsel zip bsel)) foreach { case (q, (aw, b)) => q.deq.ready := out.b .valid && in .b .ready && b q.deq.valid := DontCare diff --git a/src/main/scala/amba/axi4/Xbar.scala b/src/main/scala/amba/axi4/Xbar.scala index 291e92acdbe..e1e01119e55 100644 --- a/src/main/scala/amba/axi4/Xbar.scala +++ b/src/main/scala/amba/axi4/Xbar.scala @@ -15,7 +15,7 @@ import freechips.rocketchip.unittest.{UnitTest, UnitTestModule} import freechips.rocketchip.util.BundleField /** - * AXI4 Crossbar. It connects multiple AXI4 masters to slaves. + * AXI4 Crossbar. It connects multiple AXI4 managers to subordinates. * * @param arbitrationPolicy arbitration policy * @param maxFlightPerId maximum inflight transactions per id @@ -30,25 +30,25 @@ class AXI4Xbar( require (awQueueDepth >= 1) val node = new AXI4NexusNode( - masterFn = { seq => + managerFn = { seq => seq(0).copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, - masters = (AXI4Xbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => - port.masters map { master => master.copy(id = master.id.shift(range.start)) } + managers = (AXI4Xbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => + port.managers map { manager => manager.copy(id = manager.id.shift(range.start)) } } ) }, - slaveFn = { seq => + subordinateFn = { seq => seq(0).copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, - slaves = seq.flatMap { port => + subordinates = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, - s"Xbar data widths don't match: ${port.slaves.map(_.name)} has ${port.beatBytes}B vs ${seq(0).slaves.map(_.name)} has ${seq(0).beatBytes}B") - port.slaves + s"Xbar data widths don't match: ${port.subordinates.map(_.name)} has ${port.beatBytes}B vs ${seq(0).subordinates.map(_.name)} has ${seq(0).beatBytes}B") + port.subordinates } ) } @@ -62,10 +62,10 @@ class AXI4Xbar( val (io_out, edgesOut) = node.out.unzip // Grab the port ID mapping - val inputIdRanges = AXI4Xbar.mapInputIds(edgesIn.map(_.master)) + val inputIdRanges = AXI4Xbar.mapInputIds(edgesIn.map(_.manager)) // Find a good mask for address decoding - val port_addrs = edgesOut.map(_.slave.slaves.map(_.address).flatten) + val port_addrs = edgesOut.map(_.subordinate.subordinates.map(_.address).flatten) val routingMask = AddressDecoder(port_addrs) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) val outputPorts = route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _)) @@ -98,7 +98,7 @@ class AXI4Xbar( // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int) = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) - // Manipulate the AXI IDs to differentiate masters + // Manipulate the AXI IDs to differentiate managers val r = inputIdRanges(i) in(i).aw.bits.id := io_in(i).aw.bits.id | (r.start).U in(i).ar.bits.id := io_in(i).ar.bits.id | (r.start).U @@ -107,7 +107,7 @@ class AXI4Xbar( if (io_out.size > 1) { // Block A[RW] if we switch ports, to ensure responses stay ordered (also: beware the dining philosophers) - val endId = edgesIn(i).master.endId + val endId = edgesIn(i).manager.endId val arFIFOMap = WireDefault(VecInit.fill(endId) { true.B }) val awFIFOMap = WireDefault(VecInit.fill(endId) { true.B }) val arSel = UIntToOH(io_in(i).ar.bits.id, endId) @@ -117,12 +117,12 @@ class AXI4Xbar( val arTag = OHToUInt(requestARIO(i).asUInt, io_out.size) val awTag = OHToUInt(requestAWIO(i).asUInt, io_out.size) - for (master <- edgesIn(i).master.masters) { + for (manager <- edgesIn(i).manager.managers) { def idTracker(port: UInt, req_fire: Bool, resp_fire: Bool) = { - if (master.maxFlight == Some(0)) { + if (manager.maxFlight == Some(0)) { true.B } else { - val legalFlight = master.maxFlight.getOrElse(maxFlightPerId+1) + val legalFlight = manager.maxFlight.getOrElse(maxFlightPerId+1) val flight = legalFlight min maxFlightPerId val canOverflow = legalFlight > flight val count = RegInit(0.U(log2Ceil(flight+1).W)) @@ -137,7 +137,7 @@ class AXI4Xbar( } } - for (id <- master.id.start until master.id.end) { + for (id <- manager.id.start until manager.id.end) { arFIFOMap(id) := idTracker( arTag, arSel(id) && io_in(i).ar.fire, @@ -153,7 +153,7 @@ class AXI4Xbar( in(i).ar.valid := io_in(i).ar.valid && allowAR io_in(i).ar.ready := in(i).ar.ready && allowAR - // Keep in mind that slaves may do this: awready := wvalid, wready := awvalid + // Keep in mind that subordinates may do this: awready := wvalid, wready := awvalid // To not cause a loop, we cannot have: wvalid := awready // Block AW if we cannot record the W destination @@ -242,7 +242,7 @@ object AXI4Xbar axi4xbar.node } - def mapInputIds(ports: Seq[AXI4MasterPortParameters]) = TLXbar.assignRanges(ports.map(_.endId)) + def mapInputIds(ports: Seq[AXI4ManagerPortParameters]) = TLXbar.assignRanges(ports.map(_.endId)) // Replicate an input port to each output port def fanout[T <: AXI4BundleBase](input: IrrevocableIO[T], select: Seq[Bool]) = { @@ -311,33 +311,33 @@ object AXI4Arbiter } } -class AXI4XbarFuzzTest(name: String, txns: Int, nMasters: Int, nSlaves: Int)(implicit p: Parameters) extends LazyModule +class AXI4XbarFuzzTest(name: String, txns: Int, nManagers: Int, nSubordinates: Int)(implicit p: Parameters) extends LazyModule { val xbar = AXI4Xbar() - val slaveSize = 0x1000 - val masterBandSize = slaveSize >> log2Ceil(nMasters) - def filter(i: Int) = TLFilter.mSelectIntersect(AddressSet(i * masterBandSize, ~BigInt(slaveSize - masterBandSize))) + val subordinateSize = 0x1000 + val managerBandSize = subordinateSize >> log2Ceil(nManagers) + def filter(i: Int) = TLFilter.mSelectIntersect(AddressSet(i * managerBandSize, ~BigInt(subordinateSize - managerBandSize))) - val slaves = Seq.tabulate(nSlaves) { i => LazyModule(new AXI4RAM(AddressSet(slaveSize * i, slaveSize-1))) } - slaves.foreach { s => (s.node + val subordinates = Seq.tabulate(nSubordinates) { i => LazyModule(new AXI4RAM(AddressSet(subordinateSize * i, subordinateSize-1))) } + subordinates.foreach { s => (s.node := AXI4Fragmenter() := AXI4Buffer(BufferParams.flow) := AXI4Buffer(BufferParams.flow) := AXI4Delayer(0.25) := xbar) } - val masters = Seq.fill(nMasters) { LazyModule(new TLFuzzer(txns, 4, nOrdered = Some(1))) } - masters.zipWithIndex.foreach { case (m, i) => (xbar + val managers = Seq.fill(nManagers) { LazyModule(new TLFuzzer(txns, 4, nOrdered = Some(1))) } + managers.zipWithIndex.foreach { case (m, i) => (xbar := AXI4Delayer(0.25) := AXI4Deinterleaver(4096) := TLToAXI4() := TLFilter(filter(i)) - := TLRAMModel(s"${name} Master $i") + := TLRAMModel(s"${name} Manager $i") := m.node) } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { - io.finished := masters.map(_.module.io.finished).reduce(_ || _) + io.finished := managers.map(_.module.io.finished).reduce(_ || _) } } diff --git a/src/main/scala/amba/axi4/package.scala b/src/main/scala/amba/axi4/package.scala index 57a5e8759e1..0e47469df47 100644 --- a/src/main/scala/amba/axi4/package.scala +++ b/src/main/scala/amba/axi4/package.scala @@ -12,9 +12,9 @@ import freechips.rocketchip.prci.{HasClockDomainCrossing, HasResetDomainCrossing */ package object axi4 { - type AXI4Node = SimpleNodeHandle[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4Bundle] - type AXI4OutwardNode = OutwardNodeHandle[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4Bundle] - type AXI4InwardNode = InwardNodeHandle[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4Bundle] + type AXI4Node = SimpleNodeHandle[AXI4ManagerPortParameters, AXI4SubordinatePortParameters, AXI4EdgeParameters, AXI4Bundle] + type AXI4OutwardNode = OutwardNodeHandle[AXI4ManagerPortParameters, AXI4SubordinatePortParameters, AXI4EdgeParameters, AXI4Bundle] + type AXI4InwardNode = InwardNodeHandle[AXI4ManagerPortParameters, AXI4SubordinatePortParameters, AXI4EdgeParameters, AXI4Bundle] implicit class AXI4ClockDomainCrossing(private val x: HasClockDomainCrossing) extends AnyVal { def crossIn (n: AXI4InwardNode) (implicit valName: ValName) = AXI4InwardClockCrossingHelper(valName.value, x, n) diff --git a/src/main/scala/amba/axis/Nodes.scala b/src/main/scala/amba/axis/Nodes.scala index 133f79985a9..589d1b576df 100644 --- a/src/main/scala/amba/axis/Nodes.scala +++ b/src/main/scala/amba/axis/Nodes.scala @@ -8,29 +8,29 @@ import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.nodes.{SimpleNodeImp, SourceNode, SinkNode, NexusNode, AdapterNode, OutwardNode, IdentityNode, RenderedEdge, InwardNode} -object AXISImp extends SimpleNodeImp[AXISMasterPortParameters, AXISSlavePortParameters, AXISEdgeParameters, AXISBundle] +object AXISImp extends SimpleNodeImp[AXISManagerPortParameters, AXISSubordinatePortParameters, AXISEdgeParameters, AXISBundle] { - def edge(pd: AXISMasterPortParameters, pu: AXISSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = AXISEdgeParameters.v1(pd, pu, p, sourceInfo) + def edge(pd: AXISManagerPortParameters, pu: AXISSubordinatePortParameters, p: Parameters, sourceInfo: SourceInfo) = AXISEdgeParameters.v1(pd, pu, p, sourceInfo) def bundle(e: AXISEdgeParameters) = AXISBundle(e.bundle) def render(e: AXISEdgeParameters) = RenderedEdge(colour = "#00ccff" /* bluish */, (e.beatBytes * 8).toString) - override def mixO(pd: AXISMasterPortParameters, node: OutwardNode[AXISMasterPortParameters, AXISSlavePortParameters, AXISBundle]): AXISMasterPortParameters = - pd.v1copy(masters = pd.masters.map { c => c.v1copy (nodePath = node +: c.nodePath) }) - override def mixI(pu: AXISSlavePortParameters, node: InwardNode[AXISMasterPortParameters, AXISSlavePortParameters, AXISBundle]): AXISSlavePortParameters = - pu.v1copy(slaves = pu.slaves.map { m => m.v1copy (nodePath = node +: m.nodePath) }) + override def mixO(pd: AXISManagerPortParameters, node: OutwardNode[AXISManagerPortParameters, AXISSubordinatePortParameters, AXISBundle]): AXISManagerPortParameters = + pd.v1copy(managers = pd.managers.map { c => c.v1copy (nodePath = node +: c.nodePath) }) + override def mixI(pu: AXISSubordinatePortParameters, node: InwardNode[AXISManagerPortParameters, AXISSubordinatePortParameters, AXISBundle]): AXISSubordinatePortParameters = + pu.v1copy(subordinates = pu.subordinates.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } -case class AXISMasterNode(portParams: Seq[AXISMasterPortParameters])(implicit valName: ValName) extends SourceNode(AXISImp)(portParams) -case class AXISSlaveNode(portParams: Seq[AXISSlavePortParameters])(implicit valName: ValName) extends SinkNode(AXISImp)(portParams) +case class AXISManagerNode(portParams: Seq[AXISManagerPortParameters])(implicit valName: ValName) extends SourceNode(AXISImp)(portParams) +case class AXISSubordinateNode(portParams: Seq[AXISSubordinatePortParameters])(implicit valName: ValName) extends SinkNode(AXISImp)(portParams) case class AXISNexusNode( - masterFn: Seq[AXISMasterPortParameters] => AXISMasterPortParameters, - slaveFn: Seq[AXISSlavePortParameters] => AXISSlavePortParameters)( + managerFn: Seq[AXISManagerPortParameters] => AXISManagerPortParameters, + subordinateFn: Seq[AXISSubordinatePortParameters] => AXISSubordinatePortParameters)( implicit valName: ValName) - extends NexusNode(AXISImp)(masterFn, slaveFn) + extends NexusNode(AXISImp)(managerFn, subordinateFn) case class AXISAdapterNode( - masterFn: AXISMasterPortParameters => AXISMasterPortParameters = { m => m }, - slaveFn: AXISSlavePortParameters => AXISSlavePortParameters = { s => s })( + managerFn: AXISManagerPortParameters => AXISManagerPortParameters = { m => m }, + subordinateFn: AXISSubordinatePortParameters => AXISSubordinatePortParameters = { s => s })( implicit valName: ValName) - extends AdapterNode(AXISImp)(masterFn, slaveFn) + extends AdapterNode(AXISImp)(managerFn, subordinateFn) case class AXISIdentityNode()(implicit valName: ValName) extends IdentityNode(AXISImp)() diff --git a/src/main/scala/amba/axis/Parameters.scala b/src/main/scala/amba/axis/Parameters.scala index bcc928bf36e..66118c94af9 100644 --- a/src/main/scala/amba/axis/Parameters.scala +++ b/src/main/scala/amba/axis/Parameters.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.resources.{Resource} import freechips.rocketchip.util.{BundleFieldBase, BundleField} -class AXISSlaveParameters private ( +class AXISSubordinateParameters private ( val name: String, val supportsSizes: TransferSizes, val destinationId: Int, @@ -29,7 +29,7 @@ class AXISSlaveParameters private ( resources: Seq[Resource] = resources, nodePath: Seq[BaseNode] = nodePath) = { - new AXISSlaveParameters( + new AXISSubordinateParameters( name = name, supportsSizes = supportsSizes, destinationId = destinationId, @@ -38,7 +38,7 @@ class AXISSlaveParameters private ( } } -object AXISSlaveParameters { +object AXISSubordinateParameters { def v1( name: String, supportsSizes: TransferSizes, @@ -46,7 +46,7 @@ object AXISSlaveParameters { resources: Seq[Resource] = Nil, nodePath: Seq[BaseNode] = Nil) = { - new AXISSlaveParameters( + new AXISSubordinateParameters( name = name, supportsSizes = supportsSizes, destinationId = destinationId, @@ -55,48 +55,48 @@ object AXISSlaveParameters { } } -class AXISSlavePortParameters private ( - val slaves: Seq[AXISSlaveParameters], +class AXISSubordinatePortParameters private ( + val subordinates: Seq[AXISSubordinateParameters], val reqAligned: Boolean, /* 'Position byte's are unsupported */ val reqContinuous: Boolean, /* 'Null byte's inside transfers unsupported */ val beatBytes: Option[Int]) { - require (!slaves.isEmpty) + require (!subordinates.isEmpty) beatBytes.foreach { b => require(isPow2(b)) } - val endDestinationId = slaves.map(_.destinationId).max + 1 - val supportsMinCover = TransferSizes.mincover(slaves.map(_.supportsSizes)) + val endDestinationId = subordinates.map(_.destinationId).max + 1 + val supportsMinCover = TransferSizes.mincover(subordinates.map(_.supportsSizes)) def v1copy( - slaves: Seq[AXISSlaveParameters] = slaves, + subordinates: Seq[AXISSubordinateParameters] = subordinates, reqAligned: Boolean = reqAligned, reqContinuous: Boolean = reqContinuous, beatBytes: Option[Int] = beatBytes) = { - new AXISSlavePortParameters( - slaves = slaves, + new AXISSubordinatePortParameters( + subordinates = subordinates, reqAligned = reqAligned, reqContinuous = reqContinuous, beatBytes = beatBytes) } } -object AXISSlavePortParameters { +object AXISSubordinatePortParameters { def v1( - slaves: Seq[AXISSlaveParameters], + subordinates: Seq[AXISSubordinateParameters], reqAligned: Boolean = false, reqContinuous: Boolean = false, beatBytes: Option[Int] = None) = { - new AXISSlavePortParameters( - slaves = slaves, + new AXISSubordinatePortParameters( + subordinates = subordinates, reqAligned = reqAligned, reqContinuous = reqContinuous, beatBytes = beatBytes) } } -class AXISMasterParameters private ( +class AXISManagerParameters private ( val name: String, val emitsSizes: TransferSizes, val sourceId: IdRange, @@ -113,7 +113,7 @@ class AXISMasterParameters private ( resources: Seq[Resource] = resources, nodePath: Seq[BaseNode] = nodePath) = { - new AXISMasterParameters( + new AXISManagerParameters( name = name, emitsSizes = emitsSizes, sourceId = sourceId, @@ -122,7 +122,7 @@ class AXISMasterParameters private ( } } -object AXISMasterParameters { +object AXISManagerParameters { def v1( name: String, emitsSizes: TransferSizes, @@ -130,7 +130,7 @@ object AXISMasterParameters { resources: Seq[Resource] = Nil, nodePath: Seq[BaseNode] = Nil) = { - new AXISMasterParameters( + new AXISManagerParameters( name = name, emitsSizes = emitsSizes, sourceId = sourceId, @@ -139,28 +139,28 @@ object AXISMasterParameters { } } -class AXISMasterPortParameters private ( - val masters: Seq[AXISMasterParameters], +class AXISManagerPortParameters private ( + val managers: Seq[AXISManagerParameters], val userFields: Seq[BundleFieldBase], val isAligned: Boolean, /* there are no 'Position byte's in transfers */ val isContinuous: Boolean, /* there are no 'Null byte's except at the end of a transfer */ val beatBytes: Option[Int]) { - require (!masters.isEmpty) + require (!managers.isEmpty) beatBytes.foreach { b => require(isPow2(b)) } - val endSourceId = masters.map(_.sourceId.end).max - val emitsMinCover = TransferSizes.mincover(masters.map(_.emitsSizes)) + val endSourceId = managers.map(_.sourceId.end).max + val emitsMinCover = TransferSizes.mincover(managers.map(_.emitsSizes)) def v1copy( - masters: Seq[AXISMasterParameters] = masters, + managers: Seq[AXISManagerParameters] = managers, userFields: Seq[BundleFieldBase] = userFields, isAligned: Boolean = isAligned, isContinuous: Boolean = isContinuous, beatBytes: Option[Int] = beatBytes) = { - new AXISMasterPortParameters( - masters = masters, + new AXISManagerPortParameters( + managers = managers, userFields = userFields, isAligned = isAligned, isContinuous = isContinuous, @@ -168,16 +168,16 @@ class AXISMasterPortParameters private ( } } -object AXISMasterPortParameters { +object AXISManagerPortParameters { def v1( - masters: Seq[AXISMasterParameters], + managers: Seq[AXISManagerParameters], userFields: Seq[BundleFieldBase] = Nil, isAligned: Boolean = false, isContinuous: Boolean = false, beatBytes: Option[Int] = None) = { - new AXISMasterPortParameters( - masters = masters, + new AXISManagerPortParameters( + managers = managers, userFields = userFields, isAligned = isAligned, isContinuous = isContinuous, @@ -263,38 +263,38 @@ object AXISBundleParameters { } class AXISEdgeParameters private ( - val master: AXISMasterPortParameters, - val slave: AXISSlavePortParameters, + val manager: AXISManagerPortParameters, + val subordinate: AXISSubordinatePortParameters, val params: Parameters, val sourceInfo: SourceInfo) { - require (!slave.beatBytes.isEmpty || !master.beatBytes.isEmpty, - s"Neither master nor slave port specify a bus width (insert an AXISBusBinder between them?) at ${sourceInfo}") - require (slave.beatBytes.isEmpty || master.beatBytes.isEmpty || slave.beatBytes == master.beatBytes, - s"Master and slave ports specify incompatible bus widths (insert an AXISWidthWidget between them?) at ${sourceInfo}") - require (!slave.reqAligned || master.isAligned, s"Slave port requires aligned stream data at ${sourceInfo}") - require (!slave.reqContinuous || master.isContinuous, s"Slave port requires continuous stream data at ${sourceInfo}") + require (!subordinate.beatBytes.isEmpty || !manager.beatBytes.isEmpty, + s"Neither manager nor subordinate port specify a bus width (insert an AXISBusBinder between them?) at ${sourceInfo}") + require (subordinate.beatBytes.isEmpty || manager.beatBytes.isEmpty || subordinate.beatBytes == manager.beatBytes, + s"Manager and subordinate ports specify incompatible bus widths (insert an AXISWidthWidget between them?) at ${sourceInfo}") + require (!subordinate.reqAligned || manager.isAligned, s"Subordinate port requires aligned stream data at ${sourceInfo}") + require (!subordinate.reqContinuous || manager.isContinuous, s"Subordinate port requires continuous stream data at ${sourceInfo}") - val beatBytes = slave.beatBytes.getOrElse(master.beatBytes.get) - val transferSizes = master.emitsMinCover intersect slave.supportsMinCover + val beatBytes = subordinate.beatBytes.getOrElse(manager.beatBytes.get) + val transferSizes = manager.emitsMinCover intersect subordinate.supportsMinCover val bundle = AXISBundleParameters.v1( - idBits = log2Ceil(master.endSourceId), - destBits = log2Ceil(slave.endDestinationId), + idBits = log2Ceil(manager.endSourceId), + destBits = log2Ceil(subordinate.endDestinationId), dataBits = beatBytes * 8, - userFields = master.userFields, + userFields = manager.userFields, oneBeat = transferSizes.max <= beatBytes, - aligned = master.isAligned) + aligned = manager.isAligned) def v1copy( - master: AXISMasterPortParameters = master, - slave: AXISSlavePortParameters = slave, + manager: AXISManagerPortParameters = manager, + subordinate: AXISSubordinatePortParameters = subordinate, params: Parameters = params, sourceInfo: SourceInfo = sourceInfo) = { new AXISEdgeParameters( - master = master, - slave = slave, + manager = manager, + subordinate = subordinate, params = params, sourceInfo = sourceInfo) } @@ -302,14 +302,14 @@ class AXISEdgeParameters private ( object AXISEdgeParameters { def v1( - master: AXISMasterPortParameters, - slave: AXISSlavePortParameters, + manager: AXISManagerPortParameters, + subordinate: AXISSubordinatePortParameters, params: Parameters, sourceInfo: SourceInfo) = { new AXISEdgeParameters( - master = master, - slave = slave, + manager = manager, + subordinate = subordinate, params = params, sourceInfo = sourceInfo) } diff --git a/src/main/scala/amba/axis/Xbar.scala b/src/main/scala/amba/axis/Xbar.scala index cf154028f9c..383afa191c2 100644 --- a/src/main/scala/amba/axis/Xbar.scala +++ b/src/main/scala/amba/axis/Xbar.scala @@ -13,17 +13,17 @@ import freechips.rocketchip.tilelink.{TLXbar, TLArbiter} class AXISXbar(beatBytes: Int, policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters) extends LazyModule { val node = AXISNexusNode( - masterFn = { seq => + managerFn = { seq => seq.foreach { port => require(port.userFields == seq(0).userFields) } seq(0).v1copy( beatBytes = Some(beatBytes), - masters = (AXISXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => - port.masters map { master => master.v1copy(sourceId = master.sourceId.shift(range.start))}})}, - slaveFn = { seq => + managers = (AXISXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => + port.managers map { manager => manager.v1copy(sourceId = manager.sourceId.shift(range.start))}})}, + subordinateFn = { seq => seq(0).v1copy( beatBytes = Some(beatBytes), - slaves = (AXISXbar.mapOutputIds(seq) zip seq) flatMap { case (range, port) => - port.slaves.map { slave => slave.v1copy(destinationId = slave.destinationId + range.start)}})}) + subordinates = (AXISXbar.mapOutputIds(seq) zip seq) flatMap { case (range, port) => + port.subordinates.map { subordinate => subordinate.v1copy(destinationId = subordinate.destinationId + range.start)}})}) lazy val module = new Impl class Impl extends LazyModuleImp(this) { @@ -31,8 +31,8 @@ class AXISXbar(beatBytes: Int, policy: TLArbiter.Policy = TLArbiter.roundRobin)( val (io_out, edgesOut) = node.out.unzip // Grab the port ID mapping - val inputIdRanges = AXISXbar.mapInputIds(edgesIn.map(_.master)) - val outputIdRanges = AXISXbar.mapOutputIds(edgesOut.map(_.slave)) + val inputIdRanges = AXISXbar.mapInputIds(edgesIn.map(_.manager)) + val outputIdRanges = AXISXbar.mapOutputIds(edgesOut.map(_.subordinate)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = AXISBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) @@ -71,8 +71,8 @@ object AXISXbar xbar.node } - def mapInputIds (ports: Seq[AXISMasterPortParameters]) = TLXbar.assignRanges(ports.map(_.endSourceId)) - def mapOutputIds(ports: Seq[AXISSlavePortParameters]) = TLXbar.assignRanges(ports.map(_.endDestinationId)) + def mapInputIds (ports: Seq[AXISManagerPortParameters]) = TLXbar.assignRanges(ports.map(_.endSourceId)) + def mapOutputIds(ports: Seq[AXISSubordinatePortParameters]) = TLXbar.assignRanges(ports.map(_.endDestinationId)) def arbitrate(policy: TLArbiter.Policy)(sink: AXISBundle, sources: Seq[AXISBundle]): Unit = { if (sources.isEmpty) { diff --git a/src/main/scala/amba/axis/package.scala b/src/main/scala/amba/axis/package.scala index 00500055acd..f39ba445b42 100644 --- a/src/main/scala/amba/axis/package.scala +++ b/src/main/scala/amba/axis/package.scala @@ -6,7 +6,7 @@ import org.chipsalliance.diplomacy.nodes.{InwardNodeHandle, OutwardNodeHandle, N package object axis { - type AXISInwardNode = InwardNodeHandle[AXISMasterPortParameters, AXISSlavePortParameters, AXISEdgeParameters, AXISBundle] - type AXISOutwardNode = OutwardNodeHandle[AXISMasterPortParameters, AXISSlavePortParameters, AXISEdgeParameters, AXISBundle] - type AXISNode = NodeHandle[AXISMasterPortParameters, AXISSlavePortParameters, AXISEdgeParameters, AXISBundle, AXISMasterPortParameters, AXISSlavePortParameters, AXISEdgeParameters, AXISBundle] + type AXISInwardNode = InwardNodeHandle[AXISManagerPortParameters, AXISSubordinatePortParameters, AXISEdgeParameters, AXISBundle] + type AXISOutwardNode = OutwardNodeHandle[AXISManagerPortParameters, AXISSubordinatePortParameters, AXISEdgeParameters, AXISBundle] + type AXISNode = NodeHandle[AXISManagerPortParameters, AXISSubordinatePortParameters, AXISEdgeParameters, AXISBundle, AXISManagerPortParameters, AXISSubordinatePortParameters, AXISEdgeParameters, AXISBundle] } diff --git a/src/main/scala/amba/package.scala b/src/main/scala/amba/package.scala index 75a971c7f75..efe29592c73 100644 --- a/src/main/scala/amba/package.scala +++ b/src/main/scala/amba/package.scala @@ -13,7 +13,7 @@ package object amba { val readalloc = Bool() val writealloc = Bool() val privileged = Bool() // machine_mode=true, user_mode=false - val secure = Bool() // secure_master=true, normal=false + val secure = Bool() // secure_manager=true, normal=false val fetch = Bool() // instruct_fetch=true, load/store=false } From 2b7a8c169f7fe352e30b3a26d2d4c2d1c418a71b Mon Sep 17 00:00:00 2001 From: Alex Swehla Date: Wed, 25 Sep 2024 20:10:28 -0700 Subject: [PATCH 2/6] remove master/slave from tilelink --- src/main/scala/amba/ahb/ToTL.scala | 10 +- src/main/scala/amba/apb/ToTL.scala | 6 +- src/main/scala/amba/axi4/ToTL.scala | 6 +- src/main/scala/tilelink/AddressAdjuster.scala | 18 +- src/main/scala/tilelink/AtomicAutomata.scala | 2 +- src/main/scala/tilelink/BankBinder.scala | 4 +- src/main/scala/tilelink/Broadcast.scala | 4 +- src/main/scala/tilelink/BusWrapper.scala | 68 +-- src/main/scala/tilelink/CacheCork.scala | 2 +- src/main/scala/tilelink/FIFOFixer.scala | 8 +- src/main/scala/tilelink/Filter.scala | 6 +- src/main/scala/tilelink/Fragmenter.scala | 26 +- src/main/scala/tilelink/Fuzzer.scala | 6 +- src/main/scala/tilelink/HintHandler.scala | 4 +- src/main/scala/tilelink/Map.scala | 4 +- src/main/scala/tilelink/Monitor.scala | 44 +- src/main/scala/tilelink/Nodes.scala | 26 +- src/main/scala/tilelink/Parameters.scala | 574 +++++++++--------- src/main/scala/tilelink/PatternPusher.scala | 2 +- src/main/scala/tilelink/ProbePicker.scala | 6 +- .../scala/tilelink/RegionReplication.scala | 4 +- src/main/scala/tilelink/RegisterRouter.scala | 4 +- src/main/scala/tilelink/SRAM.scala | 4 +- src/main/scala/tilelink/SourceShrinker.scala | 4 +- src/main/scala/tilelink/ToAHB.scala | 20 +- src/main/scala/tilelink/ToAPB.scala | 14 +- src/main/scala/tilelink/ToAXI4.scala | 50 +- src/main/scala/tilelink/WidthWidget.scala | 4 +- src/main/scala/tilelink/Xbar.scala | 10 +- src/main/scala/tilelink/package.scala | 10 +- 30 files changed, 464 insertions(+), 486 deletions(-) diff --git a/src/main/scala/amba/ahb/ToTL.scala b/src/main/scala/amba/ahb/ToTL.scala index acf40f1618e..421117e3b8c 100644 --- a/src/main/scala/amba/ahb/ToTL.scala +++ b/src/main/scala/amba/ahb/ToTL.scala @@ -13,19 +13,19 @@ import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp} import freechips.rocketchip.amba.{AMBAProtField, AMBAProt} import freechips.rocketchip.diplomacy.TransferSizes -import freechips.rocketchip.tilelink.{TLImp, TLManagerPortParameters, TLMessages, TLManagerParameters, TLManagerToSubordinateTransferSizes} +import freechips.rocketchip.tilelink.{TLImp, TLClientPortParameters, TLMessages, TLClientParameters, TLClientToManagerTransferSizes} import freechips.rocketchip.util.{BundleMap, MaskGen, DataToAugmentedData} case class AHBToTLNode()(implicit valName: ValName) extends MixedAdapterNode(AHBImpSubordinate, TLImp)( dFn = { case mp => - TLManagerPortParameters.v2( - managers = mp.managers.map { m => + TLClientPortParameters.v2( + clients = mp.managers.map { m => // This value should be constrained by a data width parameter that flows from managers to subordinates // AHB fixed length transfer size maximum is 16384 = 1024 * 16 bits, hsize is capped at 111 = 1024 bit transfer size and hburst is capped at 111 = 16 beat burst - TLManagerParameters.v2( + TLClientParameters.v2( name = m.name, nodePath = m.nodePath, - emits = TLManagerToSubordinateTransferSizes( + emits = TLClientToManagerTransferSizes( get = TransferSizes(1, 2048), putFull = TransferSizes(1, 2048) ) diff --git a/src/main/scala/amba/apb/ToTL.scala b/src/main/scala/amba/apb/ToTL.scala index 6b9ddaa4ddc..89300b88608 100644 --- a/src/main/scala/amba/apb/ToTL.scala +++ b/src/main/scala/amba/apb/ToTL.scala @@ -13,13 +13,13 @@ import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp} import freechips.rocketchip.amba.{AMBAProt, AMBAProtField} import freechips.rocketchip.diplomacy.TransferSizes -import freechips.rocketchip.tilelink.{TLImp, TLMessages, TLManagerPortParameters, TLManagerParameters} +import freechips.rocketchip.tilelink.{TLImp, TLMessages, TLClientPortParameters, TLClientParameters} case class APBToTLNode()(implicit valName: ValName) extends MixedAdapterNode(APBImp, TLImp)( dFn = { mp => - TLManagerPortParameters.v1( + TLClientPortParameters.v1( clients = mp.managers.map { m => - TLManagerParameters.v1(name = m.name, nodePath = m.nodePath) + TLClientParameters.v1(name = m.name, nodePath = m.nodePath) }, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys) diff --git a/src/main/scala/amba/axi4/ToTL.scala b/src/main/scala/amba/axi4/ToTL.scala index e59332111fe..53e64a839e7 100644 --- a/src/main/scala/amba/axi4/ToTL.scala +++ b/src/main/scala/amba/axi4/ToTL.scala @@ -13,7 +13,7 @@ import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp} import freechips.rocketchip.amba.{AMBACorrupt, AMBAProt, AMBAProtField} import freechips.rocketchip.diplomacy.{IdRange, IdMapEntry, TransferSizes} -import freechips.rocketchip.tilelink.{TLImp, TLManagerParameters, TLManagerPortParameters, TLArbiter} +import freechips.rocketchip.tilelink.{TLImp, TLClientParameters, TLClientPortParameters, TLArbiter} import freechips.rocketchip.util.{OH1ToUInt, UIntToOH1} case class AXI4ToTLIdMapEntry(tlId: IdRange, axi4Id: IdRange, name: String) @@ -30,10 +30,10 @@ case class AXI4ToTLNode(wcorrupt: Boolean)(implicit valName: ValName) extends Mi dFn = { case mp => mp.managers.foreach { m => require (m.maxFlight.isDefined, "AXI4 must include a transaction maximum per ID to convert to TL") } val maxFlight = mp.managers.map(_.maxFlight.get).max - TLManagerPortParameters.v1( + TLClientPortParameters.v1( clients = mp.managers.filter(_.maxFlight != Some(0)).flatMap { m => for (id <- m.id.start until m.id.end) - yield TLManagerParameters.v1( + yield TLClientParameters.v1( name = s"${m.name} ID#${id}", sourceId = IdRange(id * maxFlight*2, (id+1) * maxFlight*2), // R+W ids are distinct nodePath = m.nodePath, diff --git a/src/main/scala/tilelink/AddressAdjuster.scala b/src/main/scala/tilelink/AddressAdjuster.scala index c9de5710ed2..d3b1a6e2cf5 100644 --- a/src/main/scala/tilelink/AddressAdjuster.scala +++ b/src/main/scala/tilelink/AddressAdjuster.scala @@ -39,7 +39,7 @@ class AddressAdjuster( // Address Adjustment requires many things about the downstream devices, captured here as helper functions: // Report whether a region of addresses fully contains a particular manager - def isDeviceContainedBy(region: Seq[AddressSet], m: TLSlaveParameters): Boolean = { + def isDeviceContainedBy(region: Seq[AddressSet], m: TLManagerParameters): Boolean = { val addr = prefix0(m.address) val any_in = region.exists { f => addr.exists { a => f.overlaps(a) } } val any_out = region.exists { f => addr.exists { a => !f.contains(a) } } @@ -50,7 +50,7 @@ class AddressAdjuster( } // Confirm that bits of an address are repeated according to the mask - def requireMaskRepetition(managers: Seq[TLSlaveParameters]): Unit = managers.map { m => + def requireMaskRepetition(managers: Seq[TLManagerParameters]): Unit = managers.map { m => val sorted = m.address.sorted bits.foreach { b => val flipped = m.address.map(a => AddressSet((a.base ^ b) & ~a.mask, a.mask)).sorted @@ -59,7 +59,7 @@ class AddressAdjuster( } // Confirm that everything supported by the remote PMA (which will be the final PMA) can be taken to the error device - def requireErrorSupport(errorDev: TLSlaveParameters, managers: Seq[TLSlaveParameters]): Unit = managers.map { m => + def requireErrorSupport(errorDev: TLManagerParameters, managers: Seq[TLManagerParameters]): Unit = managers.map { m => require (errorDev.supportsAcquireT .contains(m.supportsAcquireT ), s"Error device cannot cover ${m.name}'s AcquireT") require (errorDev.supportsAcquireB .contains(m.supportsAcquireB ), s"Error device cannot cover ${m.name}'s AcquireB") require (errorDev.supportsArithmetic.contains(m.supportsArithmetic), s"Error device cannot cover ${m.name}'s Arithmetic") @@ -70,7 +70,7 @@ class AddressAdjuster( require (errorDev.supportsHint .contains(m.supportsHint ), s"Error device cannot cover ${m.name}'s Hint") } - def sameSupport(local: Seq[TLSlaveParameters], remote: Seq[TLSlaveParameters]): (Boolean, Seq[AddressSet]) = { + def sameSupport(local: Seq[TLManagerParameters], remote: Seq[TLManagerParameters]): (Boolean, Seq[AddressSet]) = { val ra = prefix0(remote.flatMap(_.address)) val la = prefix0(local .flatMap(_.address)) val holes = la.foldLeft(ra) { case (holes, la) => holes.flatMap(_.subtract(la)) } @@ -93,14 +93,14 @@ class AddressAdjuster( } /** Confirm that a subset of managers have homogeneous FIFO ids */ - def requireFifoHomogeneity(managers: Seq[TLSlaveParameters]): Unit = managers.map { m => + def requireFifoHomogeneity(managers: Seq[TLManagerParameters]): Unit = managers.map { m => require(m.fifoId.isDefined && m.fifoId == managers.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, " + s"which was not homogeneous (${managers.map(s => (s.name, s.fifoId))}) ") } /** Confirm that a particular manager r can successfully handle all operations targeting another manager l */ - def requireContainerSupport(l: TLSlaveParameters, r: TLSlaveParameters): Unit = { + def requireContainerSupport(l: TLManagerParameters, r: TLManagerParameters): Unit = { require (l.regionType >= r.regionType, s"Device ${l.name} cannot be ${l.regionType} when ${r.name} is ${r.regionType}") require (!l.executable || r.executable, s"Device ${l.name} cannot be executable if ${r.name} is not") require (!l.mayDenyPut || r.mayDenyPut, s"Device ${l.name} cannot deny Put if ${r.name} does not") @@ -118,7 +118,7 @@ class AddressAdjuster( } // Utility debug printer - def printManagers(kind: String, managers: Seq[TLSlaveParameters]): Unit = { + def printManagers(kind: String, managers: Seq[TLManagerParameters]): Unit = { println(s"$kind:") println(managers.map(m => s"\t${m.name} ${m.address.head} ${m.fifoId}").mkString("\n")) } @@ -215,7 +215,7 @@ class AddressAdjuster( // Relable the FIFO domains for certain manager subsets val fifoIdFactory = TLXbar.relabeler() - def relabelFifo(managers: Seq[TLSlaveParameters]): Seq[TLSlaveParameters] = { + def relabelFifo(managers: Seq[TLManagerParameters]): Seq[TLManagerParameters] = { val fifoIdMapper = fifoIdFactory() managers.map(m => m.v1copy(fifoId = m.fifoId.map(fifoIdMapper(_)))) } @@ -259,7 +259,7 @@ class AddressAdjuster( assert (params.isLegalPrefix(local_prefix)) def containsAddress(region: Seq[AddressSet], addr: UInt): Bool = region.foldLeft(false.B)(_ || _.contains(addr)) - val totalContainment = parentEdge.slave.slaves.forall(_.address.forall(params.region contains _)) + val totalContainment = parentEdge.manager.managers.forall(_.address.forall(params.region contains _)) def isAdjustable(addr: UInt) = params.region.contains(addr) || totalContainment.B def isDynamicallyLocal(addr: UInt) = (local_prefix & mask.U) === (addr & mask.U) || containsAddress(forceLocal, addr) val staticLocal = AddressSet.unify(fixedLocalManagers.flatMap(_.address)) diff --git a/src/main/scala/tilelink/AtomicAutomata.scala b/src/main/scala/tilelink/AtomicAutomata.scala index 5f0fc655fdc..3cf13ff37e4 100644 --- a/src/main/scala/tilelink/AtomicAutomata.scala +++ b/src/main/scala/tilelink/AtomicAutomata.scala @@ -66,7 +66,7 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc // Don't overprovision the CAM val camSize = min(domainsNeedingHelp.size, concurrency) // Compact the fifoIds to only those we care about - def camFifoId(m: TLSlaveParameters) = m.fifoId.map(id => max(0, domainsNeedingHelp.indexOf(id))).getOrElse(0) + def camFifoId(m: TLManagerParameters) = m.fifoId.map(id => max(0, domainsNeedingHelp.indexOf(id))).getOrElse(0) // CAM entry state machine val FREE = 0.U // unused waiting on Atomic from A diff --git a/src/main/scala/tilelink/BankBinder.scala b/src/main/scala/tilelink/BankBinder.scala index 21b32729a3d..868dbd93121 100644 --- a/src/main/scala/tilelink/BankBinder.scala +++ b/src/main/scala/tilelink/BankBinder.scala @@ -23,7 +23,7 @@ case class BankBinderNode(mask: BigInt)(implicit valName: ValName) extends TLCus (iStar, oStar) } - def mapParamsD(n: Int, p: Seq[TLMasterPortParameters]): Seq[TLMasterPortParameters] = + def mapParamsD(n: Int, p: Seq[TLClientPortParameters]): Seq[TLClientPortParameters] = (p zip ids) map { case (cp, id) => cp.v1copy(clients = cp.clients.map { c => c.v1copy( visibility = c.visibility.flatMap { a => a.intersect(AddressSet(id, ~mask))}, supportsProbe = c.supports.probe intersect maxXfer, @@ -34,7 +34,7 @@ case class BankBinderNode(mask: BigInt)(implicit valName: ValName) extends TLCus supportsPutPartial = c.supports.putPartial intersect maxXfer, supportsHint = c.supports.hint intersect maxXfer)})} - def mapParamsU(n: Int, p: Seq[TLSlavePortParameters]): Seq[TLSlavePortParameters] = + def mapParamsU(n: Int, p: Seq[TLManagerPortParameters]): Seq[TLManagerPortParameters] = (p zip ids) map { case (mp, id) => mp.v1copy(managers = mp.managers.flatMap { m => val addresses = m.address.flatMap(a => a.intersect(AddressSet(id, ~mask))) if (addresses.nonEmpty) diff --git a/src/main/scala/tilelink/Broadcast.scala b/src/main/scala/tilelink/Broadcast.scala index f73cdb97cd0..59f6fe02834 100644 --- a/src/main/scala/tilelink/Broadcast.scala +++ b/src/main/scala/tilelink/Broadcast.scala @@ -42,7 +42,7 @@ class TLBroadcast(params: TLBroadcastParams)(implicit p: Parameters) extends Laz val node = TLAdapterNode( clientFn = { cp => - cp.v1copy(clients = Seq(TLMasterParameters.v1( + cp.v1copy(clients = Seq(TLClientParameters.v1( name = "TLBroadcast", sourceId = IdRange(0, 1 << log2Ceil(cp.endSourceId*4))))) }, @@ -304,7 +304,7 @@ class TLBroadcast(params: TLBroadcastParams)(implicit p: Parameters) extends Laz // addressMask is set for those bits which can actually toggle in an address; ie: // - offset bits are 0 // - bank bits are 0 -// - bits unused by any actual slave are 0 +// - bits unused by any actual manager are 0 case class ProbeFilterParams(mshrs: Int, caches: Int, maxAddress: BigInt, addressMask: BigInt) { require (mshrs >= 0) diff --git a/src/main/scala/tilelink/BusWrapper.scala b/src/main/scala/tilelink/BusWrapper.scala index c95a572de1e..467d50c3e49 100644 --- a/src/main/scala/tilelink/BusWrapper.scala +++ b/src/main/scala/tilelink/BusWrapper.scala @@ -129,42 +129,42 @@ trait TLBusWrapperInstantiationLike { trait TLBusWrapperConnectionLike { val xType: ClockCrossingType - def connect(context: HasTileLinkLocations, master: Location[TLBusWrapper], slave: Location[TLBusWrapper])(implicit p: Parameters): Unit + def connect(context: HasTileLinkLocations, client: Location[TLBusWrapper], manager: Location[TLBusWrapper])(implicit p: Parameters): Unit } object TLBusWrapperConnection { - /** Backwards compatibility factory for master driving clock and slave setting cardinality */ + /** Backwards compatibility factory for client driving clock and manager setting cardinality */ def crossTo( xType: ClockCrossingType, - driveClockFromMaster: Option[Boolean] = Some(true), + driveClockFromClient: Option[Boolean] = Some(true), nodeBinding: NodeBinding = BIND_STAR, flipRendering: Boolean = false) = { - apply(xType, driveClockFromMaster, nodeBinding, flipRendering)( - slaveNodeView = { case(w, p) => w.crossInHelper(xType)(p) }) + apply(xType, driveClockFromClient, nodeBinding, flipRendering)( + managerNodeView = { case(w, p) => w.crossInHelper(xType)(p) }) } - /** Backwards compatibility factory for slave driving clock and master setting cardinality */ + /** Backwards compatibility factory for manager driving clock and client setting cardinality */ def crossFrom( xType: ClockCrossingType, - driveClockFromMaster: Option[Boolean] = Some(false), + driveClockFromClient: Option[Boolean] = Some(false), nodeBinding: NodeBinding = BIND_QUERY, flipRendering: Boolean = true) = { - apply(xType, driveClockFromMaster, nodeBinding, flipRendering)( - masterNodeView = { case(w, p) => w.crossOutHelper(xType)(p) }) + apply(xType, driveClockFromClient, nodeBinding, flipRendering)( + clientNodeView = { case(w, p) => w.crossOutHelper(xType)(p) }) } /** Factory for making generic connections between TLBusWrappers */ def apply (xType: ClockCrossingType = NoCrossing, - driveClockFromMaster: Option[Boolean] = None, + driveClockFromClient: Option[Boolean] = None, nodeBinding: NodeBinding = BIND_ONCE, flipRendering: Boolean = false)( - slaveNodeView: (TLBusWrapper, Parameters) => TLInwardNode = { case(w, _) => w.inwardNode }, - masterNodeView: (TLBusWrapper, Parameters) => TLOutwardNode = { case(w, _) => w.outwardNode }, + managerNodeView: (TLBusWrapper, Parameters) => TLInwardNode = { case(w, _) => w.inwardNode }, + clientNodeView: (TLBusWrapper, Parameters) => TLOutwardNode = { case(w, _) => w.outwardNode }, inject: Parameters => TLNode = { _ => TLTempNode() }) = { new TLBusWrapperConnection( - xType, driveClockFromMaster, nodeBinding, flipRendering)( - slaveNodeView, masterNodeView, inject) + xType, driveClockFromClient, nodeBinding, flipRendering)( + managerNodeView, clientNodeView, inject) } } @@ -172,50 +172,50 @@ object TLBusWrapperConnection { * It has the following serializable parameters: * - xType: What type of TL clock crossing adapter to insert between the buses. * The appropriate half of the crossing adapter ends up inside each bus. - * - driveClockFromMaster: if None, don't bind the bus's diplomatic clockGroupNode, - * otherwise have either the master or the slave bus bind the other one's clockGroupNode, + * - driveClockFromClient: if None, don't bind the bus's diplomatic clockGroupNode, + * otherwise have either the client or the manager bus bind the other one's clockGroupNode, * assuming the inserted crossing type is not asynchronous. * - nodeBinding: fine-grained control of multi-edge cardinality resolution for diplomatic bindings within the connection. * - flipRendering: fine-grained control of the graphML rendering of the connection. * If has the following non-serializable parameters: - * - slaveNodeView: programmatic control of the specific attachment point within the slave bus. - * - masterNodeView: programmatic control of the specific attachment point within the master bus. + * - managerNodeView: programmatic control of the specific attachment point within the manager bus. + * - clientNodeView: programmatic control of the specific attachment point within the client bus. * - injectNode: programmatic injection of additional nodes into the middle of the connection. * The connect method applies all these parameters to create a diplomatic connection between two Location[TLBusWrapper]s. */ class TLBusWrapperConnection (val xType: ClockCrossingType, - val driveClockFromMaster: Option[Boolean], + val driveClockFromClient: Option[Boolean], val nodeBinding: NodeBinding, val flipRendering: Boolean) - (slaveNodeView: (TLBusWrapper, Parameters) => TLInwardNode, - masterNodeView: (TLBusWrapper, Parameters) => TLOutwardNode, + (managerNodeView: (TLBusWrapper, Parameters) => TLInwardNode, + clientNodeView: (TLBusWrapper, Parameters) => TLOutwardNode, inject: Parameters => TLNode) extends TLBusWrapperConnectionLike { - def connect(context: HasTileLinkLocations, master: Location[TLBusWrapper], slave: Location[TLBusWrapper])(implicit p: Parameters): Unit = { - val masterTLBus = context.locateTLBusWrapper(master) - val slaveTLBus = context.locateTLBusWrapper(slave) - def bindClocks(implicit p: Parameters) = driveClockFromMaster match { - case Some(true) => slaveTLBus.clockGroupNode := asyncMux(xType, context.allClockGroupsNode, masterTLBus.clockGroupNode) - case Some(false) => masterTLBus.clockGroupNode := asyncMux(xType, context.allClockGroupsNode, slaveTLBus.clockGroupNode) + def connect(context: HasTileLinkLocations, client: Location[TLBusWrapper], manager: Location[TLBusWrapper])(implicit p: Parameters): Unit = { + val clientTLBus = context.locateTLBusWrapper(client) + val managerTLBus = context.locateTLBusWrapper(manager) + def bindClocks(implicit p: Parameters) = driveClockFromClient match { + case Some(true) => managerTLBus.clockGroupNode := asyncMux(xType, context.allClockGroupsNode, clientTLBus.clockGroupNode) + case Some(false) => clientTLBus.clockGroupNode := asyncMux(xType, context.allClockGroupsNode, managerTLBus.clockGroupNode) case None => } def bindTLNodes(implicit p: Parameters) = nodeBinding match { - case BIND_ONCE => slaveNodeView(slaveTLBus, p) := TLWidthWidget(masterTLBus.beatBytes) := inject(p) := masterNodeView(masterTLBus, p) - case BIND_QUERY => slaveNodeView(slaveTLBus, p) :=* TLWidthWidget(masterTLBus.beatBytes) :=* inject(p) :=* masterNodeView(masterTLBus, p) - case BIND_STAR => slaveNodeView(slaveTLBus, p) :*= TLWidthWidget(masterTLBus.beatBytes) :*= inject(p) :*= masterNodeView(masterTLBus, p) - case BIND_FLEX => slaveNodeView(slaveTLBus, p) :*=* TLWidthWidget(masterTLBus.beatBytes) :*=* inject(p) :*=* masterNodeView(masterTLBus, p) + case BIND_ONCE => managerNodeView(managerTLBus, p) := TLWidthWidget(clientTLBus.beatBytes) := inject(p) := clientNodeView(clientTLBus, p) + case BIND_QUERY => managerNodeView(managerTLBus, p) :=* TLWidthWidget(clientTLBus.beatBytes) :=* inject(p) :=* clientNodeView(clientTLBus, p) + case BIND_STAR => managerNodeView(managerTLBus, p) :*= TLWidthWidget(clientTLBus.beatBytes) :*= inject(p) :*= clientNodeView(clientTLBus, p) + case BIND_FLEX => managerNodeView(managerTLBus, p) :*=* TLWidthWidget(clientTLBus.beatBytes) :*=* inject(p) :*=* clientNodeView(clientTLBus, p) } if (flipRendering) { FlipRendering { implicit p => bindClocks(implicitly[Parameters]) - slaveTLBus.from(s"bus_named_${masterTLBus.busName}") { + managerTLBus.from(s"bus_named_${clientTLBus.busName}") { bindTLNodes(implicitly[Parameters]) } } } else { bindClocks(implicitly[Parameters]) - masterTLBus.to (s"bus_named_${slaveTLBus.busName}") { + clientTLBus.to (s"bus_named_${managerTLBus.busName}") { bindTLNodes(implicitly[Parameters]) } } @@ -232,7 +232,7 @@ class TLBusWrapperTopology( instantiations.foreach { case (loc, params) => context { params.instantiate(context, loc) } } } def connect(context: HasTileLinkLocations)(implicit p: Parameters): Unit = { - connections.foreach { case (master, slave, params) => context { params.connect(context, master, slave) } } + connections.foreach { case (client, manager, params) => context { params.connect(context, client, manager) } } } } diff --git a/src/main/scala/tilelink/CacheCork.scala b/src/main/scala/tilelink/CacheCork.scala index a8518d97dee..3dcf290f83b 100644 --- a/src/main/scala/tilelink/CacheCork.scala +++ b/src/main/scala/tilelink/CacheCork.scala @@ -68,7 +68,7 @@ class TLCacheCork(params: TLCacheCorkParams = TLCacheCorkParams())(implicit p: P // The CacheCork can potentially send the same source twice if a client sends // simultaneous Release and AMO/Get with the same source. It will still correctly // decode the messages based on the D.opcode, but the double use violates the spec. - // Fortunately, no masters we know of behave this way! + // Fortunately, no clients we know of behave this way! // Take requests from A to A or D (if BtoT Acquire) val a_a = Wire(chiselTypeOf(out.a)) diff --git a/src/main/scala/tilelink/FIFOFixer.scala b/src/main/scala/tilelink/FIFOFixer.scala index efa0e966b46..b30b486a976 100644 --- a/src/main/scala/tilelink/FIFOFixer.scala +++ b/src/main/scala/tilelink/FIFOFixer.scala @@ -14,7 +14,7 @@ import freechips.rocketchip.util.property class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule { - private def fifoMap(seq: Seq[TLSlaveParameters]) = { + private def fifoMap(seq: Seq[TLManagerParameters]) = { val (flatManagers, keepManagers) = seq.partition(policy) // We need to be careful if one flatManager and one keepManager share an existing domain // Erring on the side of caution, we will also flatten the keepManager in this case @@ -138,9 +138,9 @@ class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Para object TLFIFOFixer { - // Which slaves should have their FIFOness combined? - // NOTE: this transformation is still only applied for masters with requestFifo - type Policy = TLSlaveParameters => Boolean + // Which managers should have their FIFOness combined? + // NOTE: this transformation is still only applied for clients with requestFifo + type Policy = TLManagerParameters => Boolean import RegionType._ val all: Policy = m => true diff --git a/src/main/scala/tilelink/Filter.scala b/src/main/scala/tilelink/Filter.scala index cd6ab212d2a..f2c94fc6bf2 100644 --- a/src/main/scala/tilelink/Filter.scala +++ b/src/main/scala/tilelink/Filter.scala @@ -76,8 +76,8 @@ class TLFilter( object TLFilter { - type ManagerFilter = TLSlaveParameters => Option[TLSlaveParameters] - type ClientFilter = TLMasterParameters => Option[TLMasterParameters] + type ManagerFilter = TLManagerParameters => Option[TLManagerParameters] + type ClientFilter = TLClientParameters => Option[TLClientParameters] // preserve manager visibility def mIdentity: ManagerFilter = { m => Some(m) } @@ -103,7 +103,7 @@ object TLFilter } // adjust supported transfer sizes based on filtered intersection - private def transferSizeHelper(m: TLSlaveParameters, filtered: Seq[AddressSet], alignment: BigInt): Option[TLSlaveParameters] = { + private def transferSizeHelper(m: TLManagerParameters, filtered: Seq[AddressSet], alignment: BigInt): Option[TLManagerParameters] = { val maxTransfer = 1 << 30 val capTransfer = if (alignment == 0 || alignment > maxTransfer) maxTransfer else alignment.toInt val cap = TransferSizes(1, capTransfer) diff --git a/src/main/scala/tilelink/Fragmenter.scala b/src/main/scala/tilelink/Fragmenter.scala index 68eae711aa2..11bfff9525a 100644 --- a/src/main/scala/tilelink/Fragmenter.scala +++ b/src/main/scala/tilelink/Fragmenter.scala @@ -55,7 +55,7 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none - private def mapManager(m: TLSlaveParameters) = m.v1copy( + private def mapManager(m: TLManagerParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), @@ -65,25 +65,25 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = val node = new TLAdapterNode( // We require that all the responses are mutually FIFO - // Thus we need to compact all of the masters into one big master + // Thus we need to compact all of the clients into one big client clientFn = { c => (if (noChangeRequired) c else c.v2copy( - masters = Seq(TLMasterParameters.v2( + clients = Seq(TLClientParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, - emits = TLMasterToSlaveTransferSizes( - acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), - acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), - arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), - logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), - get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), - putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), - putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), - hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) + emits = TLClientToManagerTransferSizes( + acquireT = shrinkTransfer(c.clients.map(_.emits.acquireT) .reduce(_ mincover _)), + acquireB = shrinkTransfer(c.clients.map(_.emits.acquireB) .reduce(_ mincover _)), + arithmetic = shrinkTransfer(c.clients.map(_.emits.arithmetic).reduce(_ mincover _)), + logical = shrinkTransfer(c.clients.map(_.emits.logical) .reduce(_ mincover _)), + get = shrinkTransfer(c.clients.map(_.emits.get) .reduce(_ mincover _)), + putFull = shrinkTransfer(c.clients.map(_.emits.putFull) .reduce(_ mincover _)), + putPartial = shrinkTransfer(c.clients.map(_.emits.putPartial).reduce(_ mincover _)), + hint = shrinkTransfer(c.clients.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, - managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } + managerFn = { m => if (noChangeRequired) m else m.v2copy(managers = m.managers.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } diff --git a/src/main/scala/tilelink/Fuzzer.scala b/src/main/scala/tilelink/Fuzzer.scala index 0dbf21fc831..9f71341119b 100644 --- a/src/main/scala/tilelink/Fuzzer.scala +++ b/src/main/scala/tilelink/Fuzzer.scala @@ -101,18 +101,18 @@ class TLFuzzer( require(n > 0, s"nOrdered must be > 0, not $n") require((inFlight % n) == 0, s"inFlight (${inFlight}) must be evenly divisible by nOrdered (${nOrdered}).") Seq.tabulate(n) {i => - TLMasterParameters.v1(name =s"OrderedFuzzer$i", + TLClientParameters.v1(name =s"OrderedFuzzer$i", sourceId = IdRange(i * (inFlight/n), (i + 1)*(inFlight/n)), requestFifo = true) } } else { - Seq(TLMasterParameters.v1( + Seq(TLClientParameters.v1( name = "Fuzzer", sourceId = IdRange(0,inFlight) )) } - val node = TLClientNode(Seq(TLMasterPortParameters.v1(clientParams))) + val node = TLClientNode(Seq(TLClientPortParameters.v1(clientParams))) lazy val module = new Impl class Impl extends LazyModuleImp(this) { diff --git a/src/main/scala/tilelink/HintHandler.scala b/src/main/scala/tilelink/HintHandler.scala index 982a1461d81..38ad4380268 100644 --- a/src/main/scala/tilelink/HintHandler.scala +++ b/src/main/scala/tilelink/HintHandler.scala @@ -37,8 +37,8 @@ class TLHintHandler(passthrough: Boolean = true)(implicit p: Parameters) extends } val isHint = in.a.bits.opcode === TLMessages.Hint - def usePP (m: TLSlaveParameters) = !(passthrough && m.supportsHint) && m.supportsPutPartial - def useGet(m: TLSlaveParameters) = !(passthrough && m.supportsHint) && !m.supportsPutPartial + def usePP (m: TLManagerParameters) = !(passthrough && m.supportsHint) && m.supportsPutPartial + def useGet(m: TLManagerParameters) = !(passthrough && m.supportsHint) && !m.supportsPutPartial // Does the HintHandler help using PutPartial with this message? val helpPP = isHint && edgeOut.manager.fastProperty(in.a.bits.address, usePP, (b:Boolean) => b.B) diff --git a/src/main/scala/tilelink/Map.scala b/src/main/scala/tilelink/Map.scala index b3578c05a0f..4215bcfeff7 100644 --- a/src/main/scala/tilelink/Map.scala +++ b/src/main/scala/tilelink/Map.scala @@ -9,8 +9,8 @@ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet -// Moves the AddressSets of slave devices around -// Combine with TLFilter to remove slaves or reduce their size +// Moves the AddressSets of manager devices around +// Combine with TLFilter to remove managers or reduce their size class TLMap(fn: AddressSet => BigInt)(implicit p: Parameters) extends LazyModule { val node = TLAdapterNode( diff --git a/src/main/scala/tilelink/Monitor.scala b/src/main/scala/tilelink/Monitor.scala index 0c5586cd583..38835dea124 100644 --- a/src/main/scala/tilelink/Monitor.scala +++ b/src/main/scala/tilelink/Monitor.scala @@ -82,8 +82,8 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { - monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) - monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) + monAssert (edge.client.emitsAcquireB(bundle.source, bundle.size) && edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) + monAssert (edge.client.supportsProbe(edge.source(bundle), bundle.size) && edge.manager.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) @@ -93,8 +93,8 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec } when (bundle.opcode === TLMessages.AcquirePerm) { - monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) - monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) + monAssert (edge.client.emitsAcquireB(bundle.source, bundle.size) && edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) + monAssert (edge.client.supportsProbe(edge.source(bundle), bundle.size) && edge.manager.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) @@ -105,8 +105,8 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec } when (bundle.opcode === TLMessages.Get) { - monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) - monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) + monAssert (edge.client.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which client claims it can't emit" + diplomacyInfo + extra) + monAssert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which manager claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) @@ -115,7 +115,7 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec } when (bundle.opcode === TLMessages.PutFullData) { - monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) + monAssert (edge.client.emitsPutFull(bundle.source, bundle.size) && edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) @@ -123,7 +123,7 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec } when (bundle.opcode === TLMessages.PutPartialData) { - monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) + monAssert (edge.client.emitsPutPartial(bundle.source, bundle.size) && edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) @@ -131,7 +131,7 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec } when (bundle.opcode === TLMessages.ArithmeticData) { - monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) + monAssert (edge.client.emitsArithmetic(bundle.source, bundle.size) && edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) @@ -139,7 +139,7 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec } when (bundle.opcode === TLMessages.LogicalData) { - monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) + monAssert (edge.client.emitsLogical(bundle.source, bundle.size) && edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) @@ -147,7 +147,7 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec } when (bundle.opcode === TLMessages.Hint) { - monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) + monAssert (edge.client.emitsHint(bundle.source, bundle.size) && edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) @@ -168,7 +168,7 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { - assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) + assume (edge.client.supportsProbe(edge.source(bundle), bundle.size) && edge.manager.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) @@ -178,7 +178,7 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec } when (bundle.opcode === TLMessages.Get) { - monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) + monAssert (edge.client.supportsGet(edge.source(bundle), bundle.size) && edge.manager.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) @@ -188,7 +188,7 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec } when (bundle.opcode === TLMessages.PutFullData) { - monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) + monAssert (edge.client.supportsPutFull(edge.source(bundle), bundle.size) && edge.manager.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) @@ -197,7 +197,7 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec } when (bundle.opcode === TLMessages.PutPartialData) { - monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) + monAssert (edge.client.supportsPutPartial(edge.source(bundle), bundle.size) && edge.manager.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) @@ -206,7 +206,7 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec } when (bundle.opcode === TLMessages.ArithmeticData) { - monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) + monAssert (edge.client.supportsArithmetic(edge.source(bundle), bundle.size) && edge.manager.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by client" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) @@ -215,7 +215,7 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec } when (bundle.opcode === TLMessages.LogicalData) { - monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) + monAssert (edge.client.supportsLogical(edge.source(bundle), bundle.size) && edge.manager.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) @@ -224,7 +224,7 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec } when (bundle.opcode === TLMessages.Hint) { - monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) + monAssert (edge.client.supportsHint(edge.source(bundle), bundle.size) && edge.manager.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) @@ -260,8 +260,8 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec } when (bundle.opcode === TLMessages.Release) { - monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) - monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) + monAssert (edge.client.emitsAcquireB(edge.source(bundle), bundle.size) && edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) + monAssert (edge.client.supportsProbe(edge.source(bundle), bundle.size) && edge.manager.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) @@ -270,8 +270,8 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec } when (bundle.opcode === TLMessages.ReleaseData) { - monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) - monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) + monAssert (edge.client.emitsAcquireB(edge.source(bundle), bundle.size) && edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) + monAssert (edge.client.supportsProbe(edge.source(bundle), bundle.size) && edge.manager.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) diff --git a/src/main/scala/tilelink/Nodes.scala b/src/main/scala/tilelink/Nodes.scala index 6b193f8ec0b..9f569c54970 100644 --- a/src/main/scala/tilelink/Nodes.scala +++ b/src/main/scala/tilelink/Nodes.scala @@ -13,10 +13,10 @@ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) -object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] +object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { - def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) - def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) + def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) + def edgeI(pd: TLClientPortParameters, pu: TLManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) @@ -28,27 +28,27 @@ object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEd monitor.io.in := bundle } - override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = + override def mixO(pd: TLClientPortParameters, node: OutwardNode[TLClientPortParameters, TLManagerPortParameters, TLBundle]): TLClientPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) - override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = + override def mixI(pu: TLManagerPortParameters, node: InwardNode[TLClientPortParameters, TLManagerPortParameters, TLBundle]): TLManagerPortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] -case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode -case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode +case class TLClientNode(portParams: Seq[TLClientPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode +case class TLManagerNode(portParams: Seq[TLManagerPortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( - clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, - managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( + clientFn: TLClientPortParameters => TLClientPortParameters = { s => s }, + managerFn: TLManagerPortParameters => TLManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( - clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], - managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( + clientFn: Seq[TLClientPortParameters] => Seq[TLClientPortParameters], + managerFn: Seq[TLManagerPortParameters] => Seq[TLManagerPortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode @@ -67,8 +67,8 @@ object TLTempNode { } case class TLNexusNode( - clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, - managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( + clientFn: Seq[TLClientPortParameters] => TLClientPortParameters, + managerFn: Seq[TLManagerPortParameters] => TLManagerPortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode diff --git a/src/main/scala/tilelink/Parameters.scala b/src/main/scala/tilelink/Parameters.scala index 66748a1bd68..3641b5fe611 100644 --- a/src/main/scala/tilelink/Parameters.scala +++ b/src/main/scala/tilelink/Parameters.scala @@ -21,8 +21,8 @@ import freechips.rocketchip.util.{ import scala.math.max -//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel -case class TLMasterToSlaveTransferSizes( +//These transfer sizes describe requests issued from clients on the A channel that will be responded by managers on the D channel +case class TLClientToManagerTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, @@ -33,7 +33,7 @@ case class TLMasterToSlaveTransferSizes( putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { - def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( + def intersect(rhs: TLClientToManagerTransferSizes) = TLClientToManagerTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), @@ -42,7 +42,7 @@ case class TLMasterToSlaveTransferSizes( putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) - def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( + def mincover(rhs: TLClientToManagerTransferSizes) = TLClientToManagerTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), @@ -80,8 +80,8 @@ case class TLMasterToSlaveTransferSizes( } } -object TLMasterToSlaveTransferSizes { - def unknownEmits = TLMasterToSlaveTransferSizes( +object TLClientToManagerTransferSizes { + def unknownEmits = TLClientToManagerTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), @@ -90,11 +90,11 @@ object TLMasterToSlaveTransferSizes { putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) - def unknownSupports = TLMasterToSlaveTransferSizes() + def unknownSupports = TLClientToManagerTransferSizes() } -//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel -case class TLSlaveToMasterTransferSizes( +//These transfer sizes describe requests issued from managers on the B channel that will be responded by clients on the C channel +case class TLManagerToClientTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, @@ -103,7 +103,7 @@ case class TLSlaveToMasterTransferSizes( putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { - def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( + def intersect(rhs: TLManagerToClientTransferSizes) = TLManagerToClientTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), @@ -112,7 +112,7 @@ case class TLSlaveToMasterTransferSizes( putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) - def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( + def mincover(rhs: TLManagerToClientTransferSizes) = TLManagerToClientTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), @@ -148,8 +148,8 @@ case class TLSlaveToMasterTransferSizes( } } -object TLSlaveToMasterTransferSizes { - def unknownEmits = TLSlaveToMasterTransferSizes( +object TLManagerToClientTransferSizes { + def unknownEmits = TLManagerToClientTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), @@ -157,7 +157,7 @@ object TLSlaveToMasterTransferSizes { putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) - def unknownSupports = TLSlaveToMasterTransferSizes() + def unknownSupports = TLManagerToClientTransferSizes() } trait TLCommonTransferSizes { @@ -169,7 +169,7 @@ trait TLCommonTransferSizes { def hint: TransferSizes } -class TLSlaveParameters private( +class TLManagerParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], @@ -177,20 +177,20 @@ class TLSlaveParameters private( val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], - val supports: TLMasterToSlaveTransferSizes, - val emits: TLSlaveToMasterTransferSizes, - // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) + val supports: TLClientToManagerTransferSizes, + val emits: TLManagerToClientTransferSizes, + // By default, managers are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order - // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo + // Note: you can only rely on this FIFO behaviour if your TLClientParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted - override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] - override def productPrefix = "TLSlaveParameters" + override def canEqual(that: Any): Boolean = that.isInstanceOf[TLManagerParameters] + override def productPrefix = "TLManagerParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { @@ -266,8 +266,8 @@ class TLSlaveParameters private( def isTree = findTreeViolation() == None def infoString = { - s"""Slave Name = ${name} - |Slave Address = ${address} + s"""Manager Name = ${name} + |Manager Address = ${address} |supports = ${supports.infoString} | |""".stripMargin @@ -292,14 +292,14 @@ class TLSlaveParameters private( alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { - new TLSlaveParameters( + new TLManagerParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, - supports = TLMasterToSlaveTransferSizes( + supports = TLClientToManagerTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, @@ -323,13 +323,13 @@ class TLSlaveParameters private( regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, - supports: TLMasterToSlaveTransferSizes = supports, - emits: TLSlaveToMasterTransferSizes = emits, + supports: TLClientToManagerTransferSizes = supports, + emits: TLManagerToClientTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { - new TLSlaveParameters( + new TLManagerParameters( nodePath = nodePath, resources = resources, setName = name, @@ -385,7 +385,46 @@ class TLSlaveParameters private( } } -object TLSlaveParameters { +object TLManagerParameters { + @deprecated("Use TLManagerParameters.v1 instead of TLManagerParameters","") + def apply( + address: Seq[AddressSet], + resources: Seq[Resource] = Seq(), + regionType: RegionType.T = RegionType.GET_EFFECTS, + executable: Boolean = false, + nodePath: Seq[BaseNode] = Seq(), + supportsAcquireT: TransferSizes = TransferSizes.none, + supportsAcquireB: TransferSizes = TransferSizes.none, + supportsArithmetic: TransferSizes = TransferSizes.none, + supportsLogical: TransferSizes = TransferSizes.none, + supportsGet: TransferSizes = TransferSizes.none, + supportsPutFull: TransferSizes = TransferSizes.none, + supportsPutPartial: TransferSizes = TransferSizes.none, + supportsHint: TransferSizes = TransferSizes.none, + mayDenyGet: Boolean = false, + mayDenyPut: Boolean = false, + alwaysGrantsT: Boolean = false, + fifoId: Option[Int] = None) = + TLManagerParameters.v1( + address, + resources, + regionType, + executable, + nodePath, + supportsAcquireT, + supportsAcquireB, + supportsArithmetic, + supportsLogical, + supportsGet, + supportsPutFull, + supportsPutPartial, + supportsHint, + mayDenyGet, + mayDenyPut, + alwaysGrantsT, + fifoId, + ) + def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), @@ -405,14 +444,14 @@ object TLSlaveParameters { alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { - new TLSlaveParameters( + new TLManagerParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, - supports = TLMasterToSlaveTransferSizes( + supports = TLClientToManagerTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, @@ -421,7 +460,7 @@ object TLSlaveParameters { putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), - emits = TLSlaveToMasterTransferSizes.unknownEmits, + emits = TLManagerToClientTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, @@ -436,13 +475,13 @@ object TLSlaveParameters { regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, - supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, - emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, + supports: TLClientToManagerTransferSizes = TLClientToManagerTransferSizes.unknownSupports, + emits: TLManagerToClientTransferSizes = TLManagerToClientTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { - new TLSlaveParameters( + new TLManagerParameters( nodePath = nodePath, resources = resources, setName = name, @@ -458,47 +497,6 @@ object TLSlaveParameters { } } -object TLManagerParameters { - @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") - def apply( - address: Seq[AddressSet], - resources: Seq[Resource] = Seq(), - regionType: RegionType.T = RegionType.GET_EFFECTS, - executable: Boolean = false, - nodePath: Seq[BaseNode] = Seq(), - supportsAcquireT: TransferSizes = TransferSizes.none, - supportsAcquireB: TransferSizes = TransferSizes.none, - supportsArithmetic: TransferSizes = TransferSizes.none, - supportsLogical: TransferSizes = TransferSizes.none, - supportsGet: TransferSizes = TransferSizes.none, - supportsPutFull: TransferSizes = TransferSizes.none, - supportsPutPartial: TransferSizes = TransferSizes.none, - supportsHint: TransferSizes = TransferSizes.none, - mayDenyGet: Boolean = false, - mayDenyPut: Boolean = false, - alwaysGrantsT: Boolean = false, - fifoId: Option[Int] = None) = - TLSlaveParameters.v1( - address, - resources, - regionType, - executable, - nodePath, - supportsAcquireT, - supportsAcquireB, - supportsArithmetic, - supportsLogical, - supportsGet, - supportsPutFull, - supportsPutPartial, - supportsHint, - mayDenyGet, - mayDenyPut, - alwaysGrantsT, - fifoId, - ) -} - case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) @@ -520,20 +518,20 @@ object TLChannelBeatBytes{ None) } -class TLSlavePortParameters private( - val slaves: Seq[TLSlaveParameters], +class TLManagerPortParameters private( + val managers: Seq[TLManagerParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { - def sortedSlaves = slaves.sortBy(_.sortedAddress.head) - override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] - override def productPrefix = "TLSlavePortParameters" + def sortedManagers = managers.sortBy(_.sortedAddress.head) + override def canEqual(that: Any): Boolean = that.isInstanceOf[TLManagerPortParameters] + override def productPrefix = "TLManagerPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { - case 0 => slaves + case 0 => managers case 1 => channelBytes case 2 => endSinkId case 3 => minLatency @@ -542,7 +540,7 @@ class TLSlavePortParameters private( case _ => throw new IndexOutOfBoundsException(n.toString) } - require (!slaves.isEmpty, "Slave ports must have slaves") + require (!managers.isEmpty, "Manager ports must have managers") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") @@ -554,33 +552,30 @@ class TLSlavePortParameters private( channelBytes.a.get } - // TODO this should be deprecated - def managers = slaves - def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { - val relevant = slaves.filter(m => policy(m)) + val relevant = managers.filter(m => policy(m)) relevant.foreach { m => - require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") + require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${managers.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes - def maxAddress = slaves.map(_.maxAddress).max - def maxTransfer = slaves.map(_.maxTransfer).max - def mayDenyGet = slaves.exists(_.mayDenyGet) - def mayDenyPut = slaves.exists(_.mayDenyPut) + def maxAddress = managers.map(_.maxAddress).max + def maxTransfer = managers.map(_.maxTransfer).max + def mayDenyGet = managers.exists(_.mayDenyGet) + def mayDenyPut = managers.exists(_.mayDenyPut) - // Diplomatically determined operation sizes emitted by all outward Slaves + // Diplomatically determined operation sizes emitted by all outward Managers // as opposed to emits* which generate circuitry to check which specific addresses - val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) + val allEmitClaims = managers.map(_.emits).reduce( _ intersect _) - // Operation Emitted by at least one outward Slaves + // Operation Emitted by at least one outward Managers // as opposed to emits* which generate circuitry to check which specific addresses - val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) + val anyEmitClaims = managers.map(_.emits).reduce(_ mincover _) - // Diplomatically determined operation sizes supported by all outward Slaves + // Diplomatically determined operation sizes supported by all outward Managers // as opposed to supports* which generate circuitry to check which specific addresses - val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) + val allSupportClaims = managers.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic @@ -590,9 +585,9 @@ class TLSlavePortParameters private( val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint - // Operation supported by at least one outward Slaves + // Operation supported by at least one outward Managers // as opposed to supports* which generate circuitry to check which specific addresses - val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) + val anySupportClaims = managers.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none @@ -605,27 +600,27 @@ class TLSlavePortParameters private( // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) - // These return Option[TLSlaveParameters] for your convenience - def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) + // These return Option[TLManagerParameters] for your convenience + def find(address: BigInt) = managers.find(_.address.exists(_.contains(address))) // The safe version will check the entire address - def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) + def findSafe(address: UInt) = VecInit(sortedManagers.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { - val routingMask = AddressDecoder(slaves.map(_.address)) - VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) + val routingMask = AddressDecoder(managers.map(_.address)) + VecInit(sortedManagers.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key - def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { - val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => + def fastPropertyGroup[K](p: TLManagerParameters => K): Seq[(K, Seq[AddressSet])] = { + val groups = groupByIntoSeq(sortedManagers.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property - def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = + def fastProperty[K, D <: Data](address: UInt, p: TLManagerParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None @@ -639,7 +634,7 @@ class TLSlavePortParameters private( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported - member: TLSlaveParameters => TransferSizes, + member: TLManagerParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity @@ -647,19 +642,19 @@ class TLSlavePortParameters private( // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism - // groupByIntoSeq is turning slaves into trimmed membership sizes - // We are grouping all the slaves by their transfer size where + // groupByIntoSeq is turning managers into trimmed membership sizes + // We are grouping all the managers by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about - // you are filtering the slaves based on both whether they support a particular opcode and the size - // Grouping the slaves based on the actual transfer size range they support + // you are filtering the managers based on both whether they support a particular opcode and the size + // Grouping the managers based on the actual transfer size range they support // intersecting the range and checking their membership - // FOR SUPPORTCASES instead of returning the list of slaves, + // FOR SUPPORTCASES instead of returning the list of managers, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size - // find all the slaves that support a certain type of operation and then group their addresses by the supported size + // find all the managers that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes @@ -670,7 +665,7 @@ class TLSlavePortParameters private( // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. - val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => + val supportCases = groupByIntoSeq(managers)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLManagerParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, @@ -712,21 +707,21 @@ class TLSlavePortParameters private( def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) - def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption - def isTree = !slaves.exists(!_.isTree) + def findTreeViolation() = managers.flatMap(_.findTreeViolation()).headOption + def isTree = !managers.exists(!_.isTree) - def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString + def infoString = "Manager Port Beatbytes = " + beatBytes + "\n" + "Manager Port MinLatency = " + minLatency + "\n\n" + managers.map(_.infoString).mkString def v1copy( - managers: Seq[TLSlaveParameters] = slaves, + managers: Seq[TLManagerParameters] = managers, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { - new TLSlavePortParameters( - slaves = managers, + new TLManagerPortParameters( + managers = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, @@ -735,15 +730,15 @@ class TLSlavePortParameters private( } def v2copy( - slaves: Seq[TLSlaveParameters] = slaves, + managers: Seq[TLManagerParameters] = managers, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { - new TLSlavePortParameters( - slaves = slaves, + new TLManagerPortParameters( + managers = managers, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, @@ -753,7 +748,7 @@ class TLSlavePortParameters private( @deprecated("Use v1copy instead of copy","") def copy( - managers: Seq[TLSlaveParameters] = slaves, + managers: Seq[TLManagerParameters] = managers, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, @@ -770,37 +765,17 @@ class TLSlavePortParameters private( } } -object TLSlavePortParameters { - def v1( - managers: Seq[TLSlaveParameters], - beatBytes: Int, - endSinkId: Int = 0, - minLatency: Int = 0, - responseFields: Seq[BundleFieldBase] = Nil, - requestKeys: Seq[BundleKeyBase] = Nil) = - { - new TLSlavePortParameters( - slaves = managers, - channelBytes = TLChannelBeatBytes(beatBytes), - endSinkId = endSinkId, - minLatency = minLatency, - responseFields = responseFields, - requestKeys = requestKeys) - } - -} - object TLManagerPortParameters { - @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") + @deprecated("Use TLManagerPortParameters.v1 instead of TLManagerPortParameters","") def apply( - managers: Seq[TLSlaveParameters], + managers: Seq[TLManagerParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { - TLSlavePortParameters.v1( + TLManagerPortParameters.v1( managers, beatBytes, endSinkId, @@ -808,9 +783,26 @@ object TLManagerPortParameters { responseFields, requestKeys) } + + def v1( + managers: Seq[TLManagerParameters], + beatBytes: Int, + endSinkId: Int = 0, + minLatency: Int = 0, + responseFields: Seq[BundleFieldBase] = Nil, + requestKeys: Seq[BundleKeyBase] = Nil) = + { + new TLManagerPortParameters( + managers = managers, + channelBytes = TLChannelBeatBytes(beatBytes), + endSinkId = endSinkId, + minLatency = minLatency, + responseFields = responseFields, + requestKeys = requestKeys) + } } -class TLMasterParameters private( +class TLClientParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, @@ -818,13 +810,13 @@ class TLMasterParameters private( val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. - val supports: TLSlaveToMasterTransferSizes, - val emits: TLMasterToSlaveTransferSizes, + val supports: TLManagerToClientTransferSizes, + val emits: TLClientToManagerTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { - override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] - override def productPrefix = "TLMasterParameters" + override def canEqual(that: Any): Boolean = that.isInstanceOf[TLClientParameters] + override def productPrefix = "TLClientParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { @@ -863,7 +855,7 @@ class TLMasterParameters private( supports.putPartial.max).max def infoString = { - s"""Master Name = ${name} + s"""Client Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} @@ -885,7 +877,7 @@ class TLMasterParameters private( supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { - new TLMasterParameters( + new TLClientParameters( nodePath = nodePath, resources = this.resources, name = name, @@ -893,7 +885,7 @@ class TLMasterParameters private( unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, - supports = TLSlaveToMasterTransferSizes( + supports = TLManagerToClientTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, @@ -914,12 +906,12 @@ class TLMasterParameters private( unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, - supports: TLSlaveToMasterTransferSizes = supports, - emits: TLMasterToSlaveTransferSizes = emits, + supports: TLManagerToClientTransferSizes = supports, + emits: TLClientToManagerTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { - new TLMasterParameters( + new TLClientParameters( nodePath = nodePath, resources = resources, name = name, @@ -964,7 +956,37 @@ class TLMasterParameters private( } } -object TLMasterParameters { +object TLClientParameters { + @deprecated("Use TLClientParameters.v1 instead of TLClientParameters","") + def apply( + name: String, + sourceId: IdRange = IdRange(0,1), + nodePath: Seq[BaseNode] = Seq(), + requestFifo: Boolean = false, + visibility: Seq[AddressSet] = Seq(AddressSet.everything), + supportsProbe: TransferSizes = TransferSizes.none, + supportsArithmetic: TransferSizes = TransferSizes.none, + supportsLogical: TransferSizes = TransferSizes.none, + supportsGet: TransferSizes = TransferSizes.none, + supportsPutFull: TransferSizes = TransferSizes.none, + supportsPutPartial: TransferSizes = TransferSizes.none, + supportsHint: TransferSizes = TransferSizes.none) = + { + TLClientParameters.v1( + name = name, + sourceId = sourceId, + nodePath = nodePath, + requestFifo = requestFifo, + visibility = visibility, + supportsProbe = supportsProbe, + supportsArithmetic = supportsArithmetic, + supportsLogical = supportsLogical, + supportsGet = supportsGet, + supportsPutFull = supportsPutFull, + supportsPutPartial = supportsPutPartial, + supportsHint = supportsHint) + } + def v1( name: String, sourceId: IdRange = IdRange(0,1), @@ -979,7 +1001,7 @@ object TLMasterParameters { supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { - new TLMasterParameters( + new TLClientParameters( nodePath = nodePath, resources = Nil, name = name, @@ -987,7 +1009,7 @@ object TLMasterParameters { unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, - supports = TLSlaveToMasterTransferSizes( + supports = TLManagerToClientTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, @@ -995,7 +1017,7 @@ object TLMasterParameters { putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), - emits = TLMasterToSlaveTransferSizes.unknownEmits, + emits = TLClientToManagerTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } @@ -1008,12 +1030,12 @@ object TLMasterParameters { unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, - supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, - emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, + supports: TLManagerToClientTransferSizes = TLManagerToClientTransferSizes.unknownSupports, + emits: TLClientToManagerTransferSizes = TLClientToManagerTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { - new TLMasterParameters( + new TLClientParameters( nodePath = nodePath, resources = resources, name = name, @@ -1028,51 +1050,19 @@ object TLMasterParameters { } } -object TLClientParameters { - @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") - def apply( - name: String, - sourceId: IdRange = IdRange(0,1), - nodePath: Seq[BaseNode] = Seq(), - requestFifo: Boolean = false, - visibility: Seq[AddressSet] = Seq(AddressSet.everything), - supportsProbe: TransferSizes = TransferSizes.none, - supportsArithmetic: TransferSizes = TransferSizes.none, - supportsLogical: TransferSizes = TransferSizes.none, - supportsGet: TransferSizes = TransferSizes.none, - supportsPutFull: TransferSizes = TransferSizes.none, - supportsPutPartial: TransferSizes = TransferSizes.none, - supportsHint: TransferSizes = TransferSizes.none) = - { - TLMasterParameters.v1( - name = name, - sourceId = sourceId, - nodePath = nodePath, - requestFifo = requestFifo, - visibility = visibility, - supportsProbe = supportsProbe, - supportsArithmetic = supportsArithmetic, - supportsLogical = supportsLogical, - supportsGet = supportsGet, - supportsPutFull = supportsPutFull, - supportsPutPartial = supportsPutPartial, - supportsHint = supportsHint) - } -} - -class TLMasterPortParameters private( - val masters: Seq[TLMasterParameters], +class TLClientPortParameters private( + val clients: Seq[TLClientParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { - override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] - override def productPrefix = "TLMasterPortParameters" + override def canEqual(that: Any): Boolean = that.isInstanceOf[TLClientPortParameters] + override def productPrefix = "TLClientPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { - case 0 => masters + case 0 => clients case 1 => channelBytes case 2 => minLatency case 3 => echoFields @@ -1081,73 +1071,71 @@ class TLMasterPortParameters private( case _ => throw new IndexOutOfBoundsException(n.toString) } - require (!masters.isEmpty) + require (!clients.isEmpty) require (minLatency >= 0) - def clients = masters - // Require disjoint ranges for Ids - IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => + IdRange.overlaps(clients.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes - def endSourceId = masters.map(_.sourceId.end).max - def maxTransfer = masters.map(_.maxTransfer).max + def endSourceId = clients.map(_.sourceId.end).max + def maxTransfer = clients.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { - val usedSources = masters.map(_.sourceId).sortBy(_.start) + val usedSources = clients.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } - // Diplomatically determined operation sizes emitted by all inward Masters + // Diplomatically determined operation sizes emitted by all inward Clients // as opposed to emits* which generate circuitry to check which specific addresses - val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) + val allEmitClaims = clients.map(_.emits).reduce( _ intersect _) - // Diplomatically determined operation sizes Emitted by at least one inward Masters + // Diplomatically determined operation sizes Emitted by at least one inward Clients // as opposed to emits* which generate circuitry to check which specific addresses - val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) + val anyEmitClaims = clients.map(_.emits).reduce(_ mincover _) - // Diplomatically determined operation sizes supported by all inward Masters + // Diplomatically determined operation sizes supported by all inward Clients // as opposed to supports* which generate circuitry to check which specific addresses - val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) - val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) - val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) - val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) - val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) - val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) - val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) - - // Diplomatically determined operation sizes supported by at least one master + val allSupportProbe = clients.map(_.supports.probe) .reduce(_ intersect _) + val allSupportArithmetic = clients.map(_.supports.arithmetic).reduce(_ intersect _) + val allSupportLogical = clients.map(_.supports.logical) .reduce(_ intersect _) + val allSupportGet = clients.map(_.supports.get) .reduce(_ intersect _) + val allSupportPutFull = clients.map(_.supports.putFull) .reduce(_ intersect _) + val allSupportPutPartial = clients.map(_.supports.putPartial).reduce(_ intersect _) + val allSupportHint = clients.map(_.supports.hint) .reduce(_ intersect _) + + // Diplomatically determined operation sizes supported by at least one client // as opposed to supports* which generate circuitry to check which specific addresses - val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) - val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) - val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) - val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) - val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) - val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) - val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) + val anySupportProbe = clients.map(!_.supports.probe.none) .reduce(_ || _) + val anySupportArithmetic = clients.map(!_.supports.arithmetic.none).reduce(_ || _) + val anySupportLogical = clients.map(!_.supports.logical.none) .reduce(_ || _) + val anySupportGet = clients.map(!_.supports.get.none) .reduce(_ || _) + val anySupportPutFull = clients.map(!_.supports.putFull.none) .reduce(_ || _) + val anySupportPutPartial = clients.map(!_.supports.putPartial.none).reduce(_ || _) + val anySupportHint = clients.map(!_.supports.hint.none) .reduce(_ || _) - // These return Option[TLMasterParameters] for your convenience - def find(id: Int) = masters.find(_.sourceId.contains(id)) + // These return Option[TLClientParameters] for your convenience + def find(id: Int) = clients.find(_.sourceId.contains(id)) // Synthesizable lookup methods - def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) + def find(id: UInt) = VecInit(clients.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) - def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) + def requestFifo(id: UInt) = Mux1H(find(id), clients.map(c => c.requestFifo.B)) - // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters - private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { - val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) + // Available during RTL runtime, checks to see if (id, size) is supported by the client's (client's) diplomatic parameters + private def sourceIdHelper(member: TLClientParameters => TransferSizes)(id: UInt, lgSize: UInt) = { + val allSame = clients.map(member(_) == member(clients(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. - if (allSame) member(masters(0)).containsLg(lgSize) else { - // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize - Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) + if (allSame) member(clients(0)).containsLg(lgSize) else { + // Find the client associated with ID and returns whether that particular client is able to receive transaction of lgSize + Mux1H(find(id), clients.map(member(_).containsLg(lgSize))) } } @@ -1162,12 +1150,12 @@ class TLMasterPortParameters private( // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( - member: TLMasterParameters => TransferSizes, + member: TLClientParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { - // Because sourceIds are uniquely owned by each master, we use them to group the + // Because sourceIds are uniquely owned by each client, we use them to group the // cases that have to be checked. - val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => + val emitCases = groupByIntoSeq(clients)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => @@ -1186,17 +1174,17 @@ class TLMasterPortParameters private( def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) - def infoString = masters.map(_.infoString).mkString + def infoString = clients.map(_.infoString).mkString def v1copy( - clients: Seq[TLMasterParameters] = masters, + clients: Seq[TLClientParameters] = clients, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { - new TLMasterPortParameters( - masters = clients, + new TLClientPortParameters( + clients = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, @@ -1205,15 +1193,15 @@ class TLMasterPortParameters private( } def v2copy( - masters: Seq[TLMasterParameters] = masters, + clients: Seq[TLClientParameters] = clients, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { - new TLMasterPortParameters( - masters = masters, + new TLClientPortParameters( + clients = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, @@ -1223,7 +1211,7 @@ class TLMasterPortParameters private( @deprecated("Use v1copy instead of copy","") def copy( - clients: Seq[TLMasterParameters] = masters, + clients: Seq[TLClientParameters] = clients, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, @@ -1239,33 +1227,31 @@ class TLMasterPortParameters private( } object TLClientPortParameters { - @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") + @deprecated("Use TLClientPortParameters.v1 instead of TLClientPortParameters","") def apply( - clients: Seq[TLMasterParameters], + clients: Seq[TLClientParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { - TLMasterPortParameters.v1( + TLClientPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } -} -object TLMasterPortParameters { def v1( - clients: Seq[TLMasterParameters], + clients: Seq[TLClientParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { - new TLMasterPortParameters( - masters = clients, + new TLClientPortParameters( + clients = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, @@ -1273,15 +1259,15 @@ object TLMasterPortParameters { responseKeys = responseKeys) } def v2( - masters: Seq[TLMasterParameters], + clients: Seq[TLClientParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { - new TLMasterPortParameters( - masters = masters, + new TLClientPortParameters( + clients = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, @@ -1343,39 +1329,35 @@ object TLBundleParameters def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) - def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = + def apply(client: TLClientPortParameters, manager: TLManagerPortParameters) = new TLBundleParameters( - addressBits = log2Up(slave.maxAddress + 1), - dataBits = slave.beatBytes * 8, - sourceBits = log2Up(master.endSourceId), - sinkBits = log2Up(slave.endSinkId), - sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), - echoFields = master.echoFields, - requestFields = BundleField.accept(master.requestFields, slave.requestKeys), - responseFields = BundleField.accept(slave.responseFields, master.responseKeys), - hasBCE = master.anySupportProbe && slave.anySupportAcquireB) + addressBits = log2Up(manager.maxAddress + 1), + dataBits = manager.beatBytes * 8, + sourceBits = log2Up(client.endSourceId), + sinkBits = log2Up(manager.endSinkId), + sizeBits = log2Up(log2Ceil(max(client.maxTransfer, manager.maxTransfer))+1), + echoFields = client.echoFields, + requestFields = BundleField.accept(client.requestFields, manager.requestKeys), + responseFields = BundleField.accept(manager.responseFields, client.responseKeys), + hasBCE = client.anySupportProbe && manager.anySupportAcquireB) } case class TLEdgeParameters( - master: TLMasterPortParameters, - slave: TLSlavePortParameters, + client: TLClientPortParameters, + manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { - // legacy names: - def manager = slave - def client = master - - val maxTransfer = max(master.maxTransfer, slave.maxTransfer) + val maxTransfer = max(client.maxTransfer, manager.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... - require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") + require (maxTransfer >= manager.beatBytes, s"Link's max transfer (${maxTransfer}) < ${manager.managers.map(_.name)}'s beatBytes (${manager.beatBytes})") - def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) + def diplomaticClaimsClientToManager = client.anyEmitClaims.intersect(manager.anySupportClaims) - val bundle = TLBundleParameters(master, slave) - def formatEdge = master.infoString + "\n" + slave.infoString + val bundle = TLBundleParameters(client, manager) + def formatEdge = client.infoString + "\n" + manager.infoString } case class TLCreditedDelay( @@ -1399,8 +1381,8 @@ object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } -case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} -case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} +case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLManagerPortParameters) {def infoString = base.infoString} +case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLClientPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay @@ -1408,8 +1390,8 @@ case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, mana def formatEdge = client.infoString + "\n" + manager.infoString } -case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} -case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} +case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLManagerPortParameters) {def infoString = base.infoString} +case class TLAsyncClientPortParameters(base: TLClientPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { @@ -1417,8 +1399,8 @@ case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: T def formatEdge = client.infoString + "\n" + manager.infoString } -case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} -case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} +case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLManagerPortParameters) {def infoString = base.infoString} +case class TLRationalClientPortParameters(base: TLClientPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { @@ -1442,7 +1424,7 @@ case class ManagerUnificationKey( object ManagerUnificationKey { - def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( + def apply(x: TLManagerParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, @@ -1458,8 +1440,8 @@ object ManagerUnificationKey object ManagerUnification { - def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { - slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => + def apply(managers: Seq[TLManagerParameters]): List[TLManagerParameters] = { + managers.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), @@ -1481,10 +1463,10 @@ case class TLBufferParams( } /** Pretty printing of TL source id maps */ -class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { +class TLSourceIdMap(tl: TLClientPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" - private val sorted = tl.masters.sortBy(_.sourceId) + private val sorted = tl.clients.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) diff --git a/src/main/scala/tilelink/PatternPusher.scala b/src/main/scala/tilelink/PatternPusher.scala index 08e9eaba740..1aabaeb6ea8 100644 --- a/src/main/scala/tilelink/PatternPusher.scala +++ b/src/main/scala/tilelink/PatternPusher.scala @@ -37,7 +37,7 @@ case class ReadExpectPattern(address: BigInt, size: Int, data: BigInt) extends P class TLPatternPusher(name: String, pattern: Seq[Pattern])(implicit p: Parameters) extends LazyModule { - val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(name = name))))) + val node = TLClientNode(Seq(TLClientPortParameters.v1(Seq(TLClientParameters.v1(name = name))))) lazy val module = new Impl class Impl extends LazyModuleImp(this) { diff --git a/src/main/scala/tilelink/ProbePicker.scala b/src/main/scala/tilelink/ProbePicker.scala index abb4e70f583..3b63e3d36ee 100644 --- a/src/main/scala/tilelink/ProbePicker.scala +++ b/src/main/scala/tilelink/ProbePicker.scala @@ -17,12 +17,12 @@ class ProbePicker(implicit p: Parameters) extends LazyModule clientFn = { p => // The ProbePicker assembles multiple clients based on the assumption they are contiguous in the clients list // This should be true for custers of xbar :=* BankBinder connections - def combine(next: TLMasterParameters, pair: (TLMasterParameters, Seq[TLMasterParameters])) = { + def combine(next: TLClientParameters, pair: (TLClientParameters, Seq[TLClientParameters])) = { val (head, output) = pair if (head.visibility.exists(x => next.visibility.exists(_.overlaps(x)))) { (next, head +: output) // pair is not banked, push head without merging } else { - def redact(x: TLMasterParameters) = x.v1copy(sourceId = IdRange(0,1), nodePath = Nil, visibility = Seq(AddressSet(0, ~0))) + def redact(x: TLClientParameters) = x.v1copy(sourceId = IdRange(0,1), nodePath = Nil, visibility = Seq(AddressSet(0, ~0))) require (redact(next) == redact(head), s"${redact(next)} != ${redact(head)}") val merge = head.v1copy( sourceId = IdRange( @@ -32,7 +32,7 @@ class ProbePicker(implicit p: Parameters) extends LazyModule (merge, output) } } - val myNil: Seq[TLMasterParameters] = Nil + val myNil: Seq[TLClientParameters] = Nil val (head, output) = p.clients.init.foldRight((p.clients.last, myNil))(combine) p.v1copy(clients = head +: output) }, diff --git a/src/main/scala/tilelink/RegionReplication.scala b/src/main/scala/tilelink/RegionReplication.scala index 396f5052562..33d4129dde2 100644 --- a/src/main/scala/tilelink/RegionReplication.scala +++ b/src/main/scala/tilelink/RegionReplication.scala @@ -46,8 +46,8 @@ class RegionReplicator(val params: ReplicatedRegion)(implicit p: Parameters) ext (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out <> in - // Is every slave contained by the replication region? - val totalContainment = edgeIn.slave.slaves.forall(_.address.forall(params.region contains _)) + // Is every manager contained by the replication region? + val totalContainment = edgeIn.manager.managers.forall(_.address.forall(params.region contains _)) // Which address within the mask routes to local devices? val local_prefix = RegNext(prefix.bundle) diff --git a/src/main/scala/tilelink/RegisterRouter.scala b/src/main/scala/tilelink/RegisterRouter.scala index f66a018bf23..49156c3c410 100644 --- a/src/main/scala/tilelink/RegisterRouter.scala +++ b/src/main/scala/tilelink/RegisterRouter.scala @@ -42,8 +42,8 @@ case class TLRegisterNode( undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) - extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( - Seq(TLSlaveParameters.v1( + extends SinkNode(TLImp)(Seq(TLManagerPortParameters.v1( + Seq(TLManagerParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, diff --git a/src/main/scala/tilelink/SRAM.scala b/src/main/scala/tilelink/SRAM.scala index 6703bac3c37..ea2bbdf19c8 100644 --- a/src/main/scala/tilelink/SRAM.scala +++ b/src/main/scala/tilelink/SRAM.scala @@ -40,8 +40,8 @@ class TLRAM( require (beatBytes >= 1 && isPow2(beatBytes)) require (eccBytes <= beatBytes, s"TLRAM eccBytes (${eccBytes}) > beatBytes (${beatBytes}). Use a WidthWidget=>Fragmenter=>SRAM if you need high density and narrow ECC; it will do bursts efficiently") - val node = TLManagerNode(Seq(TLSlavePortParameters.v1( - Seq(TLSlaveParameters.v1( + val node = TLManagerNode(Seq(TLManagerPortParameters.v1( + Seq(TLManagerParameters.v1( address = List(address), resources = resources, regionType = if (cacheable) RegionType.UNCACHED else RegionType.IDEMPOTENT, diff --git a/src/main/scala/tilelink/SourceShrinker.scala b/src/main/scala/tilelink/SourceShrinker.scala index c72d42f3e85..7e7db1e314d 100644 --- a/src/main/scala/tilelink/SourceShrinker.scala +++ b/src/main/scala/tilelink/SourceShrinker.scala @@ -19,13 +19,13 @@ class TLSourceShrinker(maxInFlight: Int)(implicit p: Parameters) extends LazyMod private def noShrinkRequired(client: TLClientPortParameters) = maxInFlight >= client.endSourceId // The SourceShrinker completely destroys all FIFO property guarantees - private val client = TLMasterParameters.v1( + private val client = TLClientParameters.v1( name = "TLSourceShrinker", sourceId = IdRange(0, maxInFlight)) val node = (new TLAdapterNode( clientFn = { cp => if (noShrinkRequired(cp)) { cp } else { // We erase all client information since we crush the source Ids - TLMasterPortParameters.v1( + TLClientPortParameters.v1( clients = Seq(client.v1copy(requestFifo = cp.clients.exists(_.requestFifo))), echoFields = cp.echoFields, requestFields = cp.requestFields, diff --git a/src/main/scala/tilelink/ToAHB.scala b/src/main/scala/tilelink/ToAHB.scala index a5267704295..cc849ede146 100644 --- a/src/main/scala/tilelink/ToAHB.scala +++ b/src/main/scala/tilelink/ToAHB.scala @@ -11,21 +11,21 @@ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.amba.{AMBAProt, AMBAProtField} -import freechips.rocketchip.amba.ahb.{AHBImpMaster, AHBParameters, AHBMasterParameters, AHBMasterPortParameters} +import freechips.rocketchip.amba.ahb.{AHBImpManager, AHBParameters, AHBManagerParameters, AHBManagerPortParameters} import freechips.rocketchip.amba.ahb.AHBParameters.{BURST_INCR, BURST_SINGLE, TRANS_NONSEQ, TRANS_SEQ, TRANS_IDLE, TRANS_BUSY, PROT_DEFAULT} import freechips.rocketchip.diplomacy.TransferSizes import freechips.rocketchip.util.{BundleMap, UIntToOH1} -case class TLToAHBNode(supportHints: Boolean)(implicit valName: ValName) extends MixedAdapterNode(TLImp, AHBImpMaster)( +case class TLToAHBNode(supportHints: Boolean)(implicit valName: ValName) extends MixedAdapterNode(TLImp, AHBImpManager)( dFn = { cp => - AHBMasterPortParameters( - masters = cp.clients.map { case c => AHBMasterParameters(name = c.name, nodePath = c.nodePath) }, + AHBManagerPortParameters( + managers = cp.clients.map { case c => AHBManagerParameters(name = c.name, nodePath = c.nodePath) }, requestFields = cp.requestFields.filter(!_.isInstanceOf[AMBAProtField]), responseKeys = cp.responseKeys) }, uFn = { case sp => - val managers = sp.slaves.map { case s => - TLSlaveParameters.v1( + val managers = sp.subordinates.map { case s => + TLManagerParameters.v1( address = s.address, resources = s.resources, regionType = s.regionType, @@ -40,7 +40,7 @@ case class TLToAHBNode(supportHints: Boolean)(implicit valName: ValName) extends fifoId = Some(0), mayDenyPut = true) } - TLSlavePortParameters.v1( + TLManagerPortParameters.v1( managers = managers, beatBytes = sp.beatBytes, endSinkId = 0, @@ -76,8 +76,8 @@ class TLToAHB(val aFlow: Boolean = false, val supportHints: Boolean = true, val lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => - val beatBytes = edgeOut.slave.beatBytes - val maxTransfer = edgeOut.slave.maxTransfer + val beatBytes = edgeOut.subordinate.beatBytes + val maxTransfer = edgeOut.subordinate.maxTransfer val lgMax = log2Ceil(maxTransfer) val lgBytes = log2Ceil(beatBytes) @@ -248,7 +248,7 @@ class TLToAHB(val aFlow: Boolean = false, val supportHints: Boolean = true, val assert (!d_valid || d_flow || !a_flow); // (d_valid && !d_flow) => !a_flow // On RETRY, we stall the pipeline and bypass the D-phase state back to A-phase - if (edgeOut.slave.lite) { + if (edgeOut.subordinate.lite) { retry := false.B } else if (!supportsRETRY) { assert (!d_flow || !out.hresp(1), "TLToAHB not configured with support for SPLIT/RETRY responses") diff --git a/src/main/scala/tilelink/ToAPB.scala b/src/main/scala/tilelink/ToAPB.scala index 8b045144fd3..95138108e82 100644 --- a/src/main/scala/tilelink/ToAPB.scala +++ b/src/main/scala/tilelink/ToAPB.scala @@ -12,19 +12,19 @@ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.TransferSizes import freechips.rocketchip.amba.{AMBAProt, AMBAProtField} -import freechips.rocketchip.amba.apb.{APBImp, APBMasterParameters, APBMasterPortParameters} +import freechips.rocketchip.amba.apb.{APBImp, APBManagerParameters, APBManagerPortParameters} import freechips.rocketchip.amba.apb.APBParameters.PROT_DEFAULT case class TLToAPBNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, APBImp)( dFn = { cp => - APBMasterPortParameters( - masters = cp.clients.map { case c => APBMasterParameters(name = c.name, nodePath = c.nodePath) }, + APBManagerPortParameters( + managers = cp.clients.map { case c => APBManagerParameters(name = c.name, nodePath = c.nodePath) }, requestFields = cp.requestFields.filter(!_.isInstanceOf[AMBAProtField]), responseKeys = cp.responseKeys) }, uFn = { sp => - val managers = sp.slaves.map { case s => - TLSlaveParameters.v1( + val managers = sp.subordinates.map { case s => + TLManagerParameters.v1( address = s.address, resources = s.resources, regionType = s.regionType, @@ -36,7 +36,7 @@ case class TLToAPBNode()(implicit valName: ValName) extends MixedAdapterNode(TLI fifoId = Some(0), // a common FIFO domain mayDenyPut = true) } - TLSlavePortParameters.v1( + TLManagerPortParameters.v1( managers = managers, beatBytes = sp.beatBytes, endSinkId = 0, @@ -54,7 +54,7 @@ class TLToAPB(val aFlow: Boolean = true)(implicit p: Parameters) extends LazyMod lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => - val beatBytes = edgeOut.slave.beatBytes + val beatBytes = edgeOut.subordinate.beatBytes val lgBytes = log2Ceil(beatBytes) // APB has no cache coherence diff --git a/src/main/scala/tilelink/ToAXI4.scala b/src/main/scala/tilelink/ToAXI4.scala index a01ad75cf7a..22f129246b9 100644 --- a/src/main/scala/tilelink/ToAXI4.scala +++ b/src/main/scala/tilelink/ToAXI4.scala @@ -11,7 +11,7 @@ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.amba.{AMBACorrupt, AMBACorruptField, AMBAProt, AMBAProtField} -import freechips.rocketchip.amba.axi4.{AXI4BundleARW, AXI4MasterParameters, AXI4MasterPortParameters, AXI4Parameters, AXI4Imp} +import freechips.rocketchip.amba.axi4.{AXI4BundleARW, AXI4ManagerParameters, AXI4ManagerPortParameters, AXI4Parameters, AXI4Imp} import freechips.rocketchip.diplomacy.{IdMap, IdMapEntry, IdRange} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, UIntToOH1} @@ -30,16 +30,16 @@ case class AXI4TLStateField(sourceBits: Int) extends BundleField[AXI4TLStateBund /** TLtoAXI4IdMap serves as a record for the translation performed between id spaces. * - * Its member [axi4Masters] is used as the new AXI4MasterParameters in diplomacy. + * Its member [axi4Managers] is used as the new AXI4ManagerParameters in diplomacy. * Its member [mapping] is used as the template for the circuit generated in TLToAXI4Node.module. */ -class TLtoAXI4IdMap(tlPort: TLMasterPortParameters) extends IdMap[TLToAXI4IdMapEntry] +class TLtoAXI4IdMap(tlPort: TLClientPortParameters) extends IdMap[TLToAXI4IdMapEntry] { - val tlMasters = tlPort.masters.sortBy(_.sourceId).sortWith(TLToAXI4.sortByType) - private val axi4IdSize = tlMasters.map { tl => if (tl.requestFifo) 1 else tl.sourceId.size } + val tlClients = tlPort.clients.sortBy(_.sourceId).sortWith(TLToAXI4.sortByType) + private val axi4IdSize = tlClients.map { tl => if (tl.requestFifo) 1 else tl.sourceId.size } private val axi4IdStart = axi4IdSize.scanLeft(0)(_+_).init - val axi4Masters = axi4IdStart.zip(axi4IdSize).zip(tlMasters).map { case ((start, size), tl) => - AXI4MasterParameters( + val axi4Managers = axi4IdStart.zip(axi4IdSize).zip(tlClients).map { case ((start, size), tl) => + AXI4ManagerParameters( name = tl.name, id = IdRange(start, start+size), aligned = true, @@ -47,12 +47,12 @@ class TLtoAXI4IdMap(tlPort: TLMasterPortParameters) extends IdMap[TLToAXI4IdMapE nodePath = tl.nodePath) } - private val axi4IdEnd = axi4Masters.map(_.id.end).max + private val axi4IdEnd = axi4Managers.map(_.id.end).max private val axiDigits = String.valueOf(axi4IdEnd-1).length() private val tlDigits = String.valueOf(tlPort.endSourceId-1).length() protected val fmt = s"\t[%${axiDigits}d, %${axiDigits}d) <= [%${tlDigits}d, %${tlDigits}d) %s%s%s" - val mapping: Seq[TLToAXI4IdMapEntry] = tlMasters.zip(axi4Masters).map { case (tl, axi) => + val mapping: Seq[TLToAXI4IdMapEntry] = tlClients.zip(axi4Managers).map { case (tl, axi) => TLToAXI4IdMapEntry(axi.id, tl.sourceId, tl.name, tl.supports.probe, tl.requestFifo) } } @@ -67,15 +67,15 @@ case class TLToAXI4IdMapEntry(axi4Id: IdRange, tlId: IdRange, name: String, isCa case class TLToAXI4Node(wcorrupt: Boolean = true)(implicit valName: ValName) extends MixedAdapterNode(TLImp, AXI4Imp)( dFn = { p => - AXI4MasterPortParameters( - masters = (new TLtoAXI4IdMap(p)).axi4Masters, + AXI4ManagerPortParameters( + managers = (new TLtoAXI4IdMap(p)).axi4Managers, requestFields = (if (wcorrupt) Seq(AMBACorruptField()) else Seq()) ++ p.requestFields.filter(!_.isInstanceOf[AMBAProtField]), echoFields = AXI4TLStateField(log2Ceil(p.endSourceId)) +: p.echoFields, responseKeys = p.responseKeys) }, - uFn = { p => TLSlavePortParameters.v1( - managers = p.slaves.map { case s => - TLSlaveParameters.v1( + uFn = { p => TLManagerPortParameters.v1( + managers = p.subordinates.map { case s => + TLManagerParameters.v1( address = s.address, resources = s.resources, regionType = s.regionType, @@ -93,7 +93,7 @@ case class TLToAXI4Node(wcorrupt: Boolean = true)(implicit valName: ValName) ext requestKeys = AMBAProt +: p.requestKeys) }) -// wcorrupt alone is not enough; a slave must include AMBACorrupt in the slave port's requestKeys +// wcorrupt alone is not enough; a subordinate must include AMBACorrupt in the subordinate port's requestKeys class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String] = None, val stripBits: Int = 0, val wcorrupt: Boolean = true)(implicit p: Parameters) extends LazyModule { require(stripBits == 0, "stripBits > 0 is no longer supported on TLToAXI4") @@ -102,18 +102,18 @@ class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => - val slaves = edgeOut.slave.slaves + val subordinates = edgeOut.subordinate.subordinates - // All pairs of slaves must promise that they will never interleave data - require (slaves(0).interleavedId.isDefined) - slaves.foreach { s => require (s.interleavedId == slaves(0).interleavedId) } + // All pairs of subordinates must promise that they will never interleave data + require (subordinates(0).interleavedId.isDefined) + subordinates.foreach { s => require (s.interleavedId == subordinates(0).interleavedId) } // Construct the source=>ID mapping table val map = new TLtoAXI4IdMap(edgeIn.client) val sourceStall = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(false.B)) val sourceTable = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(0.U.asTypeOf(out.aw.bits.id))) - val idStall = WireDefault(VecInit.fill(edgeOut.master.endId)(false.B)) - var idCount = Array.fill(edgeOut.master.endId) { None:Option[Int] } + val idStall = WireDefault(VecInit.fill(edgeOut.manager.endId)(false.B)) + var idCount = Array.fill(edgeOut.manager.endId) { None:Option[Int] } map.mapping.foreach { case TLToAXI4IdMapEntry(axi4Id, tlId, _, _, fifo) => for (i <- 0 until tlId.size) { @@ -257,8 +257,8 @@ class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String // We need to track if any reads or writes are inflight for a given ID. // If the opposite type arrives, we must stall until it completes. - val a_sel = UIntToOH(arw.id, edgeOut.master.endId).asBools - val d_sel = UIntToOH(Mux(r_wins, out.r.bits.id, out.b.bits.id), edgeOut.master.endId).asBools + val a_sel = UIntToOH(arw.id, edgeOut.manager.endId).asBools + val d_sel = UIntToOH(Mux(r_wins, out.r.bits.id, out.b.bits.id), edgeOut.manager.endId).asBools val d_last = Mux(r_wins, out.r.bits.last, true.B) // If FIFO was requested, ensure that R+W ordering is preserved (a_sel zip d_sel zip idStall zip idCount) foreach { case (((as, ds), s), n) => @@ -266,7 +266,7 @@ class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String // are in the middle of receiving a read burst and then issue a write, // the write might affect the read burst. This violates FIFO behaviour. // To solve this, we must wait until the last beat of a burst, but this - // means that a TileLink master which performs early source reuse can + // means that a TileLink manager which performs early source reuse can // have one more transaction inflight than we promised AXI; stall it too. val maxCount = n.getOrElse(1) val count = RegInit(0.U(log2Ceil(maxCount + 1).W)) @@ -302,7 +302,7 @@ object TLToAXI4 tl2axi4.node } - def sortByType(a: TLMasterParameters, b: TLMasterParameters): Boolean = { + def sortByType(a: TLClientParameters, b: TLClientParameters): Boolean = { if ( a.supports.probe && !b.supports.probe) return false if (!a.supports.probe && b.supports.probe) return true if ( a.requestFifo && !b.requestFifo ) return false diff --git a/src/main/scala/tilelink/WidthWidget.scala b/src/main/scala/tilelink/WidthWidget.scala index e8b21026f0c..3461eb49955 100644 --- a/src/main/scala/tilelink/WidthWidget.scala +++ b/src/main/scala/tilelink/WidthWidget.scala @@ -172,12 +172,12 @@ class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyMod (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => - // If the master is narrower than the slave, the D channel must be narrowed. + // If the client is narrower than the manager, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where - // you connect a narrow master to the system bus, so there are few sources. + // you connect a narrow client to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits diff --git a/src/main/scala/tilelink/Xbar.scala b/src/main/scala/tilelink/Xbar.scala index 4d6c9ef7b63..e22dff8a545 100644 --- a/src/main/scala/tilelink/Xbar.scala +++ b/src/main/scala/tilelink/Xbar.scala @@ -11,7 +11,7 @@ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField -// Trades off slave port proximity against routing resource cost +// Trades off manager port proximity against routing resource cost object ForceFanout { def apply[T]( @@ -74,7 +74,7 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") - println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") + println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Clients and ${node.out.size} Managers.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) @@ -85,9 +85,9 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option object TLXbar { - def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) + def mapInputIds(ports: Seq[TLClientPortParameters]) = assignRanges(ports.map(_.endSourceId)) - def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) + def mapOutputIds(ports: Seq[TLManagerPortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } @@ -117,7 +117,7 @@ object TLXbar val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip - // Not every master need connect to every slave on every channel; determine which connections are necessary + // Not every client need connect to every manager on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => diff --git a/src/main/scala/tilelink/package.scala b/src/main/scala/tilelink/package.scala index 317d4052b08..ea6c674cce0 100644 --- a/src/main/scala/tilelink/package.scala +++ b/src/main/scala/tilelink/package.scala @@ -9,13 +9,9 @@ import freechips.rocketchip.prci.{HasResetDomainCrossing, HasClockDomainCrossing package object tilelink { - type TLInwardNode = InwardNodeHandle[TLMasterPortParameters, TLSlavePortParameters, TLEdgeIn, TLBundle] - type TLOutwardNode = OutwardNodeHandle[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLBundle] - type TLNode = NodeHandle[TLMasterPortParameters, TLSlavePortParameters, TLEdgeIn, TLBundle, TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLBundle] - type TLManagerParameters = TLSlaveParameters - type TLManagerPortParameters = TLSlavePortParameters - type TLClientParameters = TLMasterParameters - type TLClientPortParameters = TLMasterPortParameters + type TLInwardNode = InwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLEdgeIn, TLBundle] + type TLOutwardNode = OutwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLBundle] + type TLNode = NodeHandle[TLClientPortParameters, TLManagerPortParameters, TLEdgeIn, TLBundle, TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLBundle] implicit class TLClockDomainCrossing(private val x: HasClockDomainCrossing) extends AnyVal { def crossIn (n: TLInwardNode) (implicit valName: ValName) = TLInwardClockCrossingHelper (valName.name, x, n) From a071f82cc3eb54b380012715a488ceb1332a9159 Mon Sep 17 00:00:00 2001 From: Alex Swehla Date: Thu, 26 Sep 2024 13:27:49 -0700 Subject: [PATCH 3/6] remove master/slave from devices --- src/main/scala/devices/debug/DMI.scala | 6 ++-- src/main/scala/devices/debug/Debug.scala | 8 ++--- src/main/scala/devices/debug/Periphery.scala | 18 +++++----- src/main/scala/devices/debug/SBA.scala | 6 ++-- .../scala/devices/debug/dm_registers.scala | 22 ++++++------ src/main/scala/devices/tilelink/BootROM.scala | 6 ++-- .../scala/devices/tilelink/BusBypass.scala | 10 +++--- src/main/scala/devices/tilelink/CLINT.scala | 4 +-- .../scala/devices/tilelink/Deadlock.scala | 2 +- src/main/scala/devices/tilelink/DevNull.scala | 6 ++-- src/main/scala/devices/tilelink/Error.scala | 2 +- src/main/scala/devices/tilelink/MaskROM.scala | 6 ++-- .../scala/devices/tilelink/MasterMux.scala | 36 +++++++++---------- src/main/scala/devices/tilelink/Plic.scala | 4 +-- src/main/scala/devices/tilelink/TestRAM.scala | 6 ++-- 15 files changed, 72 insertions(+), 70 deletions(-) diff --git a/src/main/scala/devices/debug/DMI.scala b/src/main/scala/devices/debug/DMI.scala index eeffdc2917c..8e0f2138c42 100644 --- a/src/main/scala/devices/debug/DMI.scala +++ b/src/main/scala/devices/debug/DMI.scala @@ -9,7 +9,7 @@ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.TransferSizes -import freechips.rocketchip.tilelink.{TLClientNode, TLMasterParameters, TLMasterPortParameters, TLMasterToSlaveTransferSizes} +import freechips.rocketchip.tilelink.{TLClientNode, TLClientParameters, TLClientPortParameters, TLClientToManagerTransferSizes} import freechips.rocketchip.util.ParameterizedBundle /** Constant values used by both Debug Bus Response & Request @@ -80,9 +80,9 @@ class ClockedDMIIO(implicit val p: Parameters) extends ParameterizedBundle()(p){ */ class DMIToTL(implicit p: Parameters) extends LazyModule { - val node = TLClientNode(Seq(TLMasterPortParameters.v2(Seq(TLMasterParameters.v2( + val node = TLClientNode(Seq(TLClientPortParameters.v2(Seq(TLClientParameters.v2( name = "debug", - emits = TLMasterToSlaveTransferSizes( + emits = TLClientToManagerTransferSizes( get = TransferSizes(4,4), putFull = TransferSizes(4,4))))))) diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala index efaf345fb5f..31e76dad148 100755 --- a/src/main/scala/devices/debug/Debug.scala +++ b/src/main/scala/devices/debug/Debug.scala @@ -96,7 +96,7 @@ object DebugAbstractCommandType extends scala.Enumeration { * @param nDMIAddrSize Size of the Debug Bus Address * @param nAbstractDataWords Number of 32-bit words for Abstract Commands * @param nProgamBufferWords Number of 32-bit words for Program Buffer - * @param hasBusMaster Whether or not a bus master should be included + * @param hasBusDriver Whether or not a bus driver should be included * @param clockGate Whether or not to use dmactive as the clockgate for debug module * @param maxSupportedSBAccess Maximum transaction size supported by System Bus Access logic. * @param supportQuickAccess Whether or not to support the quick access command. @@ -114,7 +114,7 @@ case class DebugModuleParams ( nProgramBufferWords: Int = 16, nAbstractDataWords : Int = 4, nScratch : Int = 1, - hasBusMaster : Boolean = false, + hasBusDriver : Boolean = false, clockGate : Boolean = true, maxSupportedSBAccess : Int = 32, supportQuickAccess : Boolean = false, @@ -254,7 +254,7 @@ class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends Par /** Parameterized version of the Debug Module defined in the * RISC-V Debug Specification * - * DebugModule is a slave to two asynchronous masters: + * DebugModule is a receiver to two asynchronous drivers: * The Debug Bus (DMI) -- This is driven by an external debugger * * The System Bus -- This services requests from the cores. Generally @@ -779,7 +779,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I executable=true ) - val sb2tlOpt = cfg.hasBusMaster.option(LazyModule(new SBToTL())) + val sb2tlOpt = cfg.hasBusDriver.option(LazyModule(new SBToTL())) // If we want to support custom registers read through Abstract Commands, // provide a place to bring them into the debug module. What this connects diff --git a/src/main/scala/devices/debug/Periphery.scala b/src/main/scala/devices/debug/Periphery.scala index 8aa3214af9b..ecef87e7a59 100644 --- a/src/main/scala/devices/debug/Periphery.scala +++ b/src/main/scala/devices/debug/Periphery.scala @@ -9,7 +9,7 @@ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ -import freechips.rocketchip.amba.apb.{APBBundle, APBBundleParameters, APBMasterNode, APBMasterParameters, APBMasterPortParameters} +import freechips.rocketchip.amba.apb.{APBBundle, APBBundleParameters, APBManagerNode, APBManagerParameters, APBManagerPortParameters} import freechips.rocketchip.interrupts.{IntSyncXbar, NullIntSyncSource} import freechips.rocketchip.jtag.JTAGIO import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters} @@ -30,8 +30,8 @@ case object APB extends DebugExportProtocol case class DebugAttachParams( protocols: Set[DebugExportProtocol] = Set(DMI), externalDisable: Boolean = false, - masterWhere: TLBusWrapperLocation = FBUS, - slaveWhere: TLBusWrapperLocation = CBUS + clientWhere: TLBusWrapperLocation = FBUS, + managerWhere: TLBusWrapperLocation = CBUS ) { def dmi = protocols.contains(DMI) def jtag = protocols.contains(JTAG) @@ -75,10 +75,10 @@ class ResetCtrlIO(val nComponents: Int)(implicit val p: Parameters) extends Bund */ trait HasPeripheryDebug { this: BaseSubsystem => - private lazy val tlbus = locateTLBusWrapper(p(ExportDebug).slaveWhere) + private lazy val tlbus = locateTLBusWrapper(p(ExportDebug).managerWhere) lazy val debugCustomXbarOpt = p(DebugModuleKey).map(params => LazyModule( new DebugCustomXbar(outputRequiresInput = false))) - lazy val apbDebugNodeOpt = p(ExportDebug).apb.option(APBMasterNode(Seq(APBMasterPortParameters(Seq(APBMasterParameters("debugAPB")))))) + lazy val apbDebugNodeOpt = p(ExportDebug).apb.option(APBManagerNode(Seq(APBManagerPortParameters(Seq(APBManagerParameters("debugAPB")))))) val debugTLDomainOpt = p(DebugModuleKey).map { _ => val domain = ClockSinkNode(Seq(ClockSinkParameters())) domain := tlbus.fixedClockNode @@ -90,12 +90,14 @@ trait HasPeripheryDebug { this: BaseSubsystem => tlDM.node := tlbus.coupleTo("debug"){ TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("Debug")) := _ } tlDM.dmInner.dmInner.customNode := debugCustomXbarOpt.get.node - (apbDebugNodeOpt zip tlDM.apbNodeOpt) foreach { case (master, slave) => - slave := master + // amba interfaces use Mananger -> Subordinate and tilelink uses Client -> Manager to indicate Initator -> Responder flow + // in this case apbmanager is the Initiator and tlmanager the Responder. + (apbDebugNodeOpt zip tlDM.apbNodeOpt) foreach { case (apbmanager, tlmanager) => + tlmanager := apbmanager } tlDM.dmInner.dmInner.sb2tlOpt.foreach { sb2tl => - locateTLBusWrapper(p(ExportDebug).masterWhere).coupleFrom("debug_sb") { + locateTLBusWrapper(p(ExportDebug).clientWhere).coupleFrom("debug_sb") { _ := TLWidthWidget(1) := sb2tl.node } } diff --git a/src/main/scala/devices/debug/SBA.scala b/src/main/scala/devices/debug/SBA.scala index 568291a221f..cdfff3225a0 100644 --- a/src/main/scala/devices/debug/SBA.scala +++ b/src/main/scala/devices/debug/SBA.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.amba.{AMBAProt, AMBAProtField} import freechips.rocketchip.devices.debug.{DebugModuleKey, RWNotify, SBCSFields, WNotifyVal} import freechips.rocketchip.diplomacy.TransferSizes import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup, RegFieldWrType} -import freechips.rocketchip.tilelink.{TLClientNode, TLMasterParameters, TLMasterPortParameters} +import freechips.rocketchip.tilelink.{TLClientNode, TLClientParameters, TLClientPortParameters} import freechips.rocketchip.util.property object SystemBusAccessState extends scala.Enumeration { @@ -265,8 +265,8 @@ class SBToTL(implicit p: Parameters) extends LazyModule { val cfg = p(DebugModuleKey).get - val node = TLClientNode(Seq(TLMasterPortParameters.v1( - clients = Seq(TLMasterParameters.v1("debug")), + val node = TLClientNode(Seq(TLClientPortParameters.v1( + clients = Seq(TLClientParameters.v1("debug")), requestFields = Seq(AMBAProtField())))) lazy val module = new Impl diff --git a/src/main/scala/devices/debug/dm_registers.scala b/src/main/scala/devices/debug/dm_registers.scala index ed46fed9611..9e511a25b4d 100644 --- a/src/main/scala/devices/debug/dm_registers.scala +++ b/src/main/scala/devices/debug/dm_registers.scala @@ -116,7 +116,7 @@ object DMI_RegAddrs { of the configuration string pointer. Reading the other {\tt confstrptr} registers returns the upper bits of the address. - When system bus mastering is implemented, this must be an + When system bus driving is implemented, this must be an address that can be used with the System Bus Access module. Otherwise, this must be an address that can be used to access the configuration string from the hart with ID 0. @@ -241,7 +241,7 @@ object DMI_RegAddrs { /* If \Fsbasize is 0, then this register is not present. - When the system bus master is busy, writes to this register will set + When the system bus driver is busy, writes to this register will set \Fsbbusyerror and don't do anything else. \begin{steps}{If \Fsberror is 0, \Fsbbusyerror is 0, and \Fsbreadonaddr @@ -257,21 +257,21 @@ object DMI_RegAddrs { /* If \Fsbasize is less than 33, then this register is not present. - When the system bus master is busy, writes to this register will set + When the system bus driver is busy, writes to this register will set \Fsbbusyerror and don't do anything else. */ def DMI_SBADDRESS1 = 0x3a /* If \Fsbasize is less than 65, then this register is not present. - When the system bus master is busy, writes to this register will set + When the system bus driver is busy, writes to this register will set \Fsbbusyerror and don't do anything else. */ def DMI_SBADDRESS2 = 0x3b /* If \Fsbasize is less than 97, then this register is not present. - When the system bus master is busy, writes to this register will set + When the system bus driver is busy, writes to this register will set \Fsbbusyerror and don't do anything else. */ def DMI_SBADDRESS3 = 0x37 @@ -285,7 +285,7 @@ object DMI_RegAddrs { If \Fsberror or \Fsbbusyerror both aren't 0 then accesses do nothing. - If the bus master is busy then accesses set \Fsbbusyerror, and don't do + If the bus driver is busy then accesses set \Fsbbusyerror, and don't do anything else. \begin{steps}{Writes to this register start the following:} @@ -316,21 +316,21 @@ object DMI_RegAddrs { /* If \Fsbaccesssixtyfour and \Fsbaccessonetwentyeight are 0, then this register is not present. - If the bus master is busy then accesses set \Fsbbusyerror, and don't do + If the bus driver is busy then accesses set \Fsbbusyerror, and don't do anything else. */ def DMI_SBDATA1 = 0x3d /* This register only exists if \Fsbaccessonetwentyeight is 1. - If the bus master is busy then accesses set \Fsbbusyerror, and don't do + If the bus driver is busy then accesses set \Fsbbusyerror, and don't do anything else. */ def DMI_SBDATA2 = 0x3e /* This register only exists if \Fsbaccessonetwentyeight is 1. - If the bus master is busy then accesses set \Fsbbusyerror, and don't do + If the bus driver is busy then accesses set \Fsbbusyerror, and don't do anything else. */ def DMI_SBDATA3 = 0x3f @@ -858,7 +858,7 @@ class SBCSFields extends Bundle { */ val sbbusyerror = Bool() - /* When 1, indicates the system bus master is busy. (Whether the + /* When 1, indicates the system bus driver is busy. (Whether the system bus itself is busy is related, but not the same thing.) This bit goes high immediately when a read or write is requested for any reason, and does not go low until the access is fully completed. @@ -902,7 +902,7 @@ class SBCSFields extends Bundle { val sbreadondata = Bool() /* When the Debug Module's system bus - master encounters an error, this field gets set. The bits in this + driver encounters an error, this field gets set. The bits in this field remain set until they are cleared by writing 1 to them. While this field is non-zero, no more system bus accesses can be initiated by the Debug Module. diff --git a/src/main/scala/devices/tilelink/BootROM.scala b/src/main/scala/devices/tilelink/BootROM.scala index 7cbfcca6df8..6cfd69d6375 100644 --- a/src/main/scala/devices/tilelink/BootROM.scala +++ b/src/main/scala/devices/tilelink/BootROM.scala @@ -12,7 +12,7 @@ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes} import freechips.rocketchip.resources.{Resource, SimpleDevice} import freechips.rocketchip.subsystem._ -import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLSlaveParameters, TLSlavePortParameters} +import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLManagerParameters, TLManagerPortParameters} import java.nio.ByteBuffer import java.nio.file.{Files, Paths} @@ -27,8 +27,8 @@ case class BootROMParams( class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4, resources: Seq[Resource] = new SimpleDevice("rom", Seq("sifive,rom0")).reg("mem"))(implicit p: Parameters) extends LazyModule { - val node = TLManagerNode(Seq(TLSlavePortParameters.v1( - Seq(TLSlaveParameters.v1( + val node = TLManagerNode(Seq(TLManagerPortParameters.v1( + Seq(TLManagerParameters.v1( address = List(AddressSet(base, size-1)), resources = resources, regionType = RegionType.UNCACHED, diff --git a/src/main/scala/devices/tilelink/BusBypass.scala b/src/main/scala/devices/tilelink/BusBypass.scala index 39ccbb0c117..02baa53ea8b 100644 --- a/src/main/scala/devices/tilelink/BusBypass.scala +++ b/src/main/scala/devices/tilelink/BusBypass.scala @@ -46,7 +46,7 @@ class TLBusBypass(beatBytes: Int, bufferError: Boolean = false, maxAtomic: Int = } } -class TLBypassNode(dFn: TLSlavePortParameters => TLSlavePortParameters)(implicit valName: ValName) extends TLCustomNode +class TLBypassNode(dFn: TLManagerPortParameters => TLManagerPortParameters)(implicit valName: ValName) extends TLCustomNode { def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = { require (iStars == 0 && oStars == 0, "TLBypass node does not support :=* or :*=") @@ -54,11 +54,11 @@ class TLBypassNode(dFn: TLSlavePortParameters => TLSlavePortParameters)(implicit require (oKnown == 2, "TLBypass node expects exactly two outputs") (0, 0) } - def mapParamsD(n: Int, p: Seq[TLMasterPortParameters]): Seq[TLMasterPortParameters] = { p ++ p } - def mapParamsU(n: Int, p: Seq[TLSlavePortParameters]): Seq[TLSlavePortParameters] = { Seq(dFn(p.last).v1copy(minLatency = p.map(_.minLatency).min))} + def mapParamsD(n: Int, p: Seq[TLClientPortParameters]): Seq[TLClientPortParameters] = { p ++ p } + def mapParamsU(n: Int, p: Seq[TLManagerPortParameters]): Seq[TLManagerPortParameters] = { Seq(dFn(p.last).v1copy(minLatency = p.map(_.minLatency).min))} } -class TLBusBypassBar(dFn: TLSlavePortParameters => TLSlavePortParameters)(implicit p: Parameters) extends LazyModule +class TLBusBypassBar(dFn: TLManagerPortParameters => TLManagerPortParameters)(implicit p: Parameters) extends LazyModule { val node = new TLBypassNode(dFn) @@ -73,7 +73,7 @@ class TLBusBypassBar(dFn: TLSlavePortParameters => TLSlavePortParameters)(implic val Seq((out0, edgeOut0), (out1, edgeOut1)) = node.out require (edgeOut0.manager.beatBytes == edgeOut1.manager.beatBytes, - s"BusBypass slave device widths mismatch (${edgeOut0.manager.managers.map(_.name)} has ${edgeOut0.manager.beatBytes}B vs ${edgeOut1.manager.managers.map(_.name)} has ${edgeOut1.manager.beatBytes}B)") + s"BusBypass manager device widths mismatch (${edgeOut0.manager.managers.map(_.name)} has ${edgeOut0.manager.beatBytes}B vs ${edgeOut1.manager.managers.map(_.name)} has ${edgeOut1.manager.beatBytes}B)") // We need to be locked to the given bypass direction until all transactions stop val in_reset = RegNext(false.B, init = true.B) diff --git a/src/main/scala/devices/tilelink/CLINT.scala b/src/main/scala/devices/tilelink/CLINT.scala index 81c7051ae46..d8376bb8fa9 100644 --- a/src/main/scala/devices/tilelink/CLINT.scala +++ b/src/main/scala/devices/tilelink/CLINT.scala @@ -37,7 +37,7 @@ case class CLINTParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0) case object CLINTKey extends Field[Option[CLINTParams]](None) case class CLINTAttachParams( - slaveWhere: TLBusWrapperLocation = CBUS + managerWhere: TLBusWrapperLocation = CBUS ) case object CLINTAttachKey extends Field(CLINTAttachParams()) @@ -107,7 +107,7 @@ class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends /** Trait that will connect a CLINT to a subsystem */ trait CanHavePeripheryCLINT { this: BaseSubsystem => val (clintOpt, clintDomainOpt, clintTickOpt) = p(CLINTKey).map { params => - val tlbus = locateTLBusWrapper(p(CLINTAttachKey).slaveWhere) + val tlbus = locateTLBusWrapper(p(CLINTAttachKey).managerWhere) val clintDomainWrapper = tlbus.generateSynchronousDomain("CLINT").suggestName("clint_domain") val clint = clintDomainWrapper { LazyModule(new CLINT(params, tlbus.beatBytes)) } clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus, Some("CLINT")) := _ } } diff --git a/src/main/scala/devices/tilelink/Deadlock.scala b/src/main/scala/devices/tilelink/Deadlock.scala index 0d5e970b216..32c2c5609c9 100644 --- a/src/main/scala/devices/tilelink/Deadlock.scala +++ b/src/main/scala/devices/tilelink/Deadlock.scala @@ -7,7 +7,7 @@ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.resources.{SimpleDevice} -/** Adds a /dev/null slave that does not raise ready for any incoming traffic. +/** Adds a /dev/null manager that does not raise ready for any incoming traffic. * !!! WARNING: This device WILL cause your bus to deadlock for as long as you * continue to send traffic to it !!! */ diff --git a/src/main/scala/devices/tilelink/DevNull.scala b/src/main/scala/devices/tilelink/DevNull.scala index 9d3462e715c..2f2920247ba 100644 --- a/src/main/scala/devices/tilelink/DevNull.scala +++ b/src/main/scala/devices/tilelink/DevNull.scala @@ -8,7 +8,7 @@ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes} import freechips.rocketchip.resources.{SimpleDevice} import freechips.rocketchip.prci.{HasClockDomainCrossing} -import freechips.rocketchip.tilelink.{TLManagerNode, TLSlaveParameters, TLSlavePortParameters} +import freechips.rocketchip.tilelink.{TLManagerNode, TLManagerParameters, TLManagerPortParameters} import freechips.rocketchip.tilelink.TLClockDomainCrossing @@ -38,8 +38,8 @@ abstract class DevNullDevice(params: DevNullParams, minLatency: Int, beatBytes: val atom = if (params.maxAtomic > 0) TransferSizes(1, params.maxAtomic) else TransferSizes.none val acq = if (params.acquire) xfer else TransferSizes.none val hint = if (params.hint) xfer else TransferSizes.none - val node = TLManagerNode(Seq(TLSlavePortParameters.v1( - Seq(TLSlaveParameters.v1( + val node = TLManagerNode(Seq(TLManagerPortParameters.v1( + Seq(TLManagerParameters.v1( address = params.address, resources = device.reg, regionType = params.region, diff --git a/src/main/scala/devices/tilelink/Error.scala b/src/main/scala/devices/tilelink/Error.scala index cb048c3aab3..cd23b1f0c6b 100644 --- a/src/main/scala/devices/tilelink/Error.scala +++ b/src/main/scala/devices/tilelink/Error.scala @@ -11,7 +11,7 @@ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.resources.SimpleDevice import freechips.rocketchip.tilelink.{TLArbiter, TLMessages, TLPermissions} -/** Adds a /dev/null slave that generates TL error response messages */ +/** Adds a /dev/null manager that generates TL error response messages */ class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends DevNullDevice(params, minLatency = if (buffer) 1 else 0, diff --git a/src/main/scala/devices/tilelink/MaskROM.scala b/src/main/scala/devices/tilelink/MaskROM.scala index 8a01ec5fd7b..5a712d0c55c 100644 --- a/src/main/scala/devices/tilelink/MaskROM.scala +++ b/src/main/scala/devices/tilelink/MaskROM.scala @@ -11,7 +11,7 @@ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{RegionType, AddressSet, TransferSizes} import freechips.rocketchip.resources.{SimpleDevice} import freechips.rocketchip.subsystem.{Attachable, HierarchicalLocation, TLBusWrapperLocation} -import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLSlaveParameters, TLSlavePortParameters, TLWidthWidget} +import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLManagerParameters, TLManagerPortParameters, TLWidthWidget} import freechips.rocketchip.util.{ROMConfig, ROMGenerator} import freechips.rocketchip.util.DataToAugmentedData @@ -20,8 +20,8 @@ case class MaskROMParams(address: BigInt, name: String, depth: Int = 2048, width class TLMaskROM(c: MaskROMParams)(implicit p: Parameters) extends LazyModule { val beatBytes = c.width/8 - val node = TLManagerNode(Seq(TLSlavePortParameters.v1( - Seq(TLSlaveParameters.v1( + val node = TLManagerNode(Seq(TLManagerPortParameters.v1( + Seq(TLManagerParameters.v1( address = AddressSet.misaligned(c.address, c.depth*beatBytes), resources = new SimpleDevice("rom", Seq("sifive,maskrom0")).reg("mem"), regionType = RegionType.UNCACHED, diff --git a/src/main/scala/devices/tilelink/MasterMux.scala b/src/main/scala/devices/tilelink/MasterMux.scala index c1ddf82477b..e368f8fbcb2 100644 --- a/src/main/scala/devices/tilelink/MasterMux.scala +++ b/src/main/scala/devices/tilelink/MasterMux.scala @@ -11,25 +11,25 @@ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.tilelink.{ LFSR64, TLBundleA, TLBundleC, TLBundleE, TLClientNode, TLCustomNode, TLFilter, TLFragmenter, - TLFuzzer, TLMasterParameters, TLMasterPortParameters, TLPermissions, TLRAM, TLRAMModel, - TLSlaveParameters, TLSlavePortParameters + TLFuzzer, TLClientParameters, TLClientPortParameters, TLPermissions, TLRAM, TLRAMModel, + TLManagerParameters, TLManagerPortParameters } -class MasterMuxNode(uFn: Seq[TLMasterPortParameters] => TLMasterPortParameters)(implicit valName: ValName) extends TLCustomNode +class ClientMuxNode(uFn: Seq[TLClientPortParameters] => TLClientPortParameters)(implicit valName: ValName) extends TLCustomNode { def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = { - require (iStars == 0 && oStars == 0, "MasterMux node does not support :=* or :*=") - require (iKnown == 2, "MasterMux node expects exactly two inputs") - require (oKnown == 1, "MasterMux node expects exactly one output") + require (iStars == 0 && oStars == 0, "ClientMux node does not support :=* or :*=") + require (iKnown == 2, "ClientMux node expects exactly two inputs") + require (oKnown == 1, "ClientMux node expects exactly one output") (0, 0) } - def mapParamsD(n: Int, p: Seq[TLMasterPortParameters]): Seq[TLMasterPortParameters] = { Seq(uFn(p)) } - def mapParamsU(n: Int, p: Seq[TLSlavePortParameters]): Seq[TLSlavePortParameters] = { p ++ p } + def mapParamsD(n: Int, p: Seq[TLClientPortParameters]): Seq[TLClientPortParameters] = { Seq(uFn(p)) } + def mapParamsU(n: Int, p: Seq[TLManagerPortParameters]): Seq[TLManagerPortParameters] = { p ++ p } } -class MuteMaster(name: String = "MuteMaster", maxProbe: Int = 0)(implicit p: Parameters) extends LazyModule +class MuteClient(name: String = "MuteClient", maxProbe: Int = 0)(implicit p: Parameters) extends LazyModule { - val node = TLClientNode(Seq(TLMasterPortParameters.v1(clients = Seq(TLMasterParameters.v1( + val node = TLClientNode(Seq(TLClientPortParameters.v1(clients = Seq(TLClientParameters.v1( name = name, supportsProbe = if (maxProbe > 0) TransferSizes(1, maxProbe) else TransferSizes.none))))) @@ -46,9 +46,9 @@ class MuteMaster(name: String = "MuteMaster", maxProbe: Int = 0)(implicit p: Par } } -class MasterMux(uFn: Seq[TLMasterPortParameters] => TLMasterPortParameters)(implicit p: Parameters) extends LazyModule +class ClientMux(uFn: Seq[TLClientPortParameters] => TLClientPortParameters)(implicit p: Parameters) extends LazyModule { - val node = new MasterMuxNode(uFn) + val node = new ClientMuxNode(uFn) lazy val module = new Impl class Impl extends LazyModuleImp(this) { @@ -117,12 +117,12 @@ class MasterMux(uFn: Seq[TLMasterPortParameters] => TLMasterPortParameters)(impl // Synthesizable unit tests import freechips.rocketchip.unittest._ -class TLMasterMuxTester(txns: Int)(implicit p: Parameters) extends LazyModule { +class TLClientMuxTester(txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz1 = LazyModule(new TLFuzzer(txns)) val fuzz2 = LazyModule(new TLFuzzer(txns)) - val model1 = LazyModule(new TLRAMModel("MasterMux1")) - val model2 = LazyModule(new TLRAMModel("MasterMux2")) - val mux = LazyModule(new MasterMux(uFn = _.head)) + val model1 = LazyModule(new TLRAMModel("ClientMux1")) + val model2 = LazyModule(new TLRAMModel("ClientMux2")) + val mux = LazyModule(new ClientMux(uFn = _.head)) val ram = LazyModule(new TLRAM(AddressSet(0, 0x3ff), beatBytes = 4)) mux.node := TLFilter(TLFilter.mSelectIntersect(AddressSet( 0, ~16))) := model1.node := fuzz1.node mux.node := TLFilter(TLFilter.mSelectIntersect(AddressSet(16, ~16))) := model2.node := fuzz2.node @@ -136,7 +136,7 @@ class TLMasterMuxTester(txns: Int)(implicit p: Parameters) extends LazyModule { } } -class TLMasterMuxTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { - val dut = Module(LazyModule(new TLMasterMuxTester(txns)).module) +class TLClientMuxTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { + val dut = Module(LazyModule(new TLClientMuxTester(txns)).module) io <> dut.io } diff --git a/src/main/scala/devices/tilelink/Plic.scala b/src/main/scala/devices/tilelink/Plic.scala index 75cf30edf4b..7c2fc58d3ad 100644 --- a/src/main/scala/devices/tilelink/Plic.scala +++ b/src/main/scala/devices/tilelink/Plic.scala @@ -74,7 +74,7 @@ case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, i case object PLICKey extends Field[Option[PLICParams]](None) case class PLICAttachParams( - slaveWhere: TLBusWrapperLocation = CBUS + managerWhere: TLBusWrapperLocation = CBUS ) case object PLICAttachKey extends Field(PLICAttachParams()) @@ -361,7 +361,7 @@ class PLICFanIn(nDevices: Int, prioBits: Int) extends Module { /** Trait that will connect a PLIC to a subsystem */ trait CanHavePeripheryPLIC { this: BaseSubsystem => val (plicOpt, plicDomainOpt) = p(PLICKey).map { params => - val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere) + val tlbus = locateTLBusWrapper(p(PLICAttachKey).managerWhere) val plicDomainWrapper = tlbus.generateSynchronousDomain("PLIC").suggestName("plic_domain") val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) } diff --git a/src/main/scala/devices/tilelink/TestRAM.scala b/src/main/scala/devices/tilelink/TestRAM.scala index 368c176a9ee..84ee4928694 100644 --- a/src/main/scala/devices/tilelink/TestRAM.scala +++ b/src/main/scala/devices/tilelink/TestRAM.scala @@ -10,15 +10,15 @@ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes} import freechips.rocketchip.resources.{MemoryDevice} -import freechips.rocketchip.tilelink.{TLDelayer, TLFuzzer, TLManagerNode, TLMessages, TLRAMModel, TLSlaveParameters, TLSlavePortParameters} +import freechips.rocketchip.tilelink.{TLDelayer, TLFuzzer, TLManagerNode, TLMessages, TLRAMModel, TLManagerParameters, TLManagerPortParameters} // Do not use this for synthesis! Only for simulation. class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, trackCorruption: Boolean = true)(implicit p: Parameters) extends LazyModule { val device = new MemoryDevice - val node = TLManagerNode(Seq(TLSlavePortParameters.v1( - Seq(TLSlaveParameters.v1( + val node = TLManagerNode(Seq(TLManagerPortParameters.v1( + Seq(TLManagerParameters.v1( address = List(address), resources = device.reg, regionType = RegionType.UNCACHED, From ee641bc6ba41d44d03bff7b088e437a1ed19f664 Mon Sep 17 00:00:00 2001 From: Alex Swehla Date: Thu, 26 Sep 2024 13:28:20 -0700 Subject: [PATCH 4/6] remove master/slave from system and subsystem --- .../subsystem/BankedCoherenceParams.scala | 4 +- src/main/scala/subsystem/BusTopology.scala | 8 +- src/main/scala/subsystem/Cluster.scala | 20 ++--- src/main/scala/subsystem/Configs.scala | 28 +++--- .../subsystem/HasHierarchicalElements.scala | 22 ++--- src/main/scala/subsystem/HasTiles.scala | 22 ++--- .../scala/subsystem/HierarchicalElement.scala | 26 +++--- .../HierarchicalElementPRCIDomain.scala | 28 +++--- src/main/scala/subsystem/Ports.scala | 88 +++++++++---------- src/main/scala/subsystem/RTC.scala | 2 +- .../scala/subsystem/RocketSubsystem.scala | 4 +- src/main/scala/system/Configs.scala | 6 +- .../scala/system/ExampleRocketSystem.scala | 6 +- src/main/scala/system/SimAXIMem.scala | 20 ++--- 14 files changed, 142 insertions(+), 142 deletions(-) diff --git a/src/main/scala/subsystem/BankedCoherenceParams.scala b/src/main/scala/subsystem/BankedCoherenceParams.scala index 235cd1eebbd..8df8d509326 100644 --- a/src/main/scala/subsystem/BankedCoherenceParams.scala +++ b/src/main/scala/subsystem/BankedCoherenceParams.scala @@ -81,10 +81,10 @@ object CoherenceManagerWrapper { def broadcastManagerFn( name: String, location: HierarchicalLocation, - controlPortsSlaveWhere: TLBusWrapperLocation + controlPortsManagerWhere: TLBusWrapperLocation ): CoherenceManagerInstantiationFn = { context => implicit val p = context.p - val cbus = context.locateTLBusWrapper(controlPortsSlaveWhere) + val cbus = context.locateTLBusWrapper(controlPortsManagerWhere) val BroadcastParams(nTrackers, bufferless, controlAddress, filterFactory) = p(BroadcastKey) val bh = LazyModule(new TLBroadcast(TLBroadcastParams( diff --git a/src/main/scala/subsystem/BusTopology.scala b/src/main/scala/subsystem/BusTopology.scala index 5b3dd7c452a..4e1e20ae7e6 100644 --- a/src/main/scala/subsystem/BusTopology.scala +++ b/src/main/scala/subsystem/BusTopology.scala @@ -104,10 +104,10 @@ case class CoherentBusTopologyParams( (MBUS, mbus), (COH, CoherenceManagerWrapperParams(mbus.blockBytes, mbus.beatBytes, coherence.nBanks, COH.name)(coherence.coherenceManager)))), connections = if (coherence.nBanks == 0) Nil else List( - (SBUS, COH, TLBusWrapperConnection(driveClockFromMaster = Some(true), nodeBinding = BIND_STAR)()), + (SBUS, COH, TLBusWrapperConnection(driveClockFromClient = Some(true), nodeBinding = BIND_STAR)()), (COH, MBUS, TLBusWrapperConnection.crossTo( xType = sbusToMbusXType, - driveClockFromMaster = if (driveMBusClockFromSBus) Some(true) else None, + driveClockFromClient = if (driveMBusClockFromSBus) Some(true) else None, nodeBinding = BIND_QUERY)) ) ) @@ -124,10 +124,10 @@ case class ClusterBusTopologyParams( (CMBUS(clusterId), csbus), (CCOH (clusterId), CoherenceManagerWrapperParams(csbus.blockBytes, csbus.beatBytes, coherence.nBanks, CCOH(clusterId).name)(coherence.coherenceManager)))), connections = if (coherence.nBanks == 0) Nil else List( - (CSBUS(clusterId), CCOH (clusterId), TLBusWrapperConnection(driveClockFromMaster = Some(true), nodeBinding = BIND_STAR)()), + (CSBUS(clusterId), CCOH (clusterId), TLBusWrapperConnection(driveClockFromClient = Some(true), nodeBinding = BIND_STAR)()), (CCOH (clusterId), CMBUS(clusterId), TLBusWrapperConnection.crossTo( xType = NoCrossing, - driveClockFromMaster = Some(true), + driveClockFromClient = Some(true), nodeBinding = BIND_QUERY)) ) ) diff --git a/src/main/scala/subsystem/Cluster.scala b/src/main/scala/subsystem/Cluster.scala index 9d82ad616ca..9b3336605f1 100644 --- a/src/main/scala/subsystem/Cluster.scala +++ b/src/main/scala/subsystem/Cluster.scala @@ -52,8 +52,8 @@ class Cluster( csbus.clockGroupNode := allClockGroupsNode ccbus.clockGroupNode := allClockGroupsNode - val slaveNode = ccbus.inwardNode - val masterNode = cmbus.outwardNode + val managerNode = ccbus.inwardNode + val clientNode = cmbus.outwardNode @@ -117,8 +117,8 @@ trait CanAttachCluster { } def connect(domain: ClusterPRCIDomain, context: ClusterContextType): Unit = { - connectMasterPorts(domain, context) - connectSlavePorts(domain, context) + connectClientPorts(domain, context) + connectManagerPorts(domain, context) connectInterrupts(domain, context) connectPRC(domain, context) connectOutputNotifications(domain, context) @@ -126,18 +126,18 @@ trait CanAttachCluster { connectTrace(domain, context) } - def connectMasterPorts(domain: ClusterPRCIDomain, context: Attachable): Unit = { + def connectClientPorts(domain: ClusterPRCIDomain, context: Attachable): Unit = { implicit val p = context.p - val dataBus = context.locateTLBusWrapper(crossingParams.master.where) + val dataBus = context.locateTLBusWrapper(crossingParams.client.where) dataBus.coupleFrom(clusterParams.baseName) { bus => - bus :=* crossingParams.master.injectNode(context) :=* domain.crossMasterPort(crossingParams.crossingType) + bus :=* crossingParams.client.injectNode(context) :=* domain.crossClientPort(crossingParams.crossingType) } } - def connectSlavePorts(domain: ClusterPRCIDomain, context: Attachable): Unit = { + def connectManagerPorts(domain: ClusterPRCIDomain, context: Attachable): Unit = { implicit val p = context.p - val controlBus = context.locateTLBusWrapper(crossingParams.slave.where) + val controlBus = context.locateTLBusWrapper(crossingParams.manager.where) controlBus.coupleTo(clusterParams.baseName) { bus => - domain.crossSlavePort(crossingParams.crossingType) :*= crossingParams.slave.injectNode(context) :*= TLWidthWidget(controlBus.beatBytes) :*= bus + domain.crossManagerPort(crossingParams.crossingType) :*= crossingParams.manager.injectNode(context) :*= TLWidthWidget(controlBus.beatBytes) :*= bus } } def connectInterrupts(domain: ClusterPRCIDomain, context: ClusterContextType): Unit = { diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala index 37001b39fd3..3b4a09e5dfb 100644 --- a/src/main/scala/subsystem/Configs.scala +++ b/src/main/scala/subsystem/Configs.scala @@ -195,9 +195,9 @@ class WithRoccExample extends Config((site, here, up) => { class WithIncoherentTiles extends Config((site, here, up) => { case TilesLocated(location) => up(TilesLocated(location), site) map { case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( - master = tp.crossingParams.master match { - case x: HierarchicalElementMasterPortParams => x.copy(cork = Some(true)) - case _ => throw new Exception("Unrecognized type for RocketCrossingParams.master") + client = tp.crossingParams.client match { + case x: HierarchicalElementClientPortParams => x.copy(cork = Some(true)) + case _ => throw new Exception("Unrecognized type for RocketCrossingParams.client") })) case t => t } @@ -229,7 +229,7 @@ class WithDebugAPB extends Config ((site, here, up) => { class WithDebugSBA extends Config ((site, here, up) => { - case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(hasBusMaster = true)) + case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(hasBusDriver = true)) }) class WithNBitPeripheryBus(nBits: Int) extends Config ((site, here, up) => { @@ -249,7 +249,7 @@ class WithNMemoryChannels(n: Int) extends Config((site, here, up) => { }) class WithExtMemSize(n: BigInt) extends Config((site, here, up) => { - case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = n))) + case ExtMem => up(ExtMem, site).map(x => x.copy(client = x.client.copy(size = n))) }) class WithExtMemSbusBypass(base: BigInt = x"10_0000_0000") extends Config((site, here, up) => { @@ -266,7 +266,7 @@ class WithTimebase(hertz: BigInt) extends Config((site, here, up) => { }) class WithDefaultMemPort extends Config((site, here, up) => { - case ExtMem => Some(MemoryPortParams(MasterPortParams( + case ExtMem => Some(MemoryPortParams(ClientPortParams( base = x"8000_0000", size = x"1000_0000", beatBytes = site(MemoryBusKey).beatBytes, @@ -274,7 +274,7 @@ class WithDefaultMemPort extends Config((site, here, up) => { }) class WithCustomMemPort (base_addr: BigInt, base_size: BigInt, data_width: Int, id_bits: Int, maxXferBytes: Int) extends Config((site, here, up) => { - case ExtMem => Some(MemoryPortParams(MasterPortParams( + case ExtMem => Some(MemoryPortParams(ClientPortParams( base = base_addr, size = base_size, beatBytes = data_width/8, @@ -287,7 +287,7 @@ class WithNoMemPort extends Config((site, here, up) => { }) class WithDefaultMMIOPort extends Config((site, here, up) => { - case ExtBus => Some(MasterPortParams( + case ExtBus => Some(ClientPortParams( base = x"6000_0000", size = x"2000_0000", beatBytes = site(MemoryBusKey).beatBytes, @@ -295,7 +295,7 @@ class WithDefaultMMIOPort extends Config((site, here, up) => { }) class WithCustomMMIOPort (base_addr: BigInt, base_size: BigInt, data_width: Int, id_bits: Int, maxXferBytes: Int) extends Config((site, here, up) => { - case ExtBus => Some(MasterPortParams( + case ExtBus => Some(ClientPortParams( base = base_addr, size = base_size, beatBytes = data_width/8, @@ -307,15 +307,15 @@ class WithNoMMIOPort extends Config((site, here, up) => { case ExtBus => None }) -class WithDefaultSlavePort extends Config((site, here, up) => { - case ExtIn => Some(SlavePortParams(beatBytes = 8, idBits = 8, sourceBits = 4)) +class WithDefaultManagerPort extends Config((site, here, up) => { + case ExtIn => Some(ManagerPortParams(beatBytes = 8, idBits = 8, sourceBits = 4)) }) -class WithCustomSlavePort (data_width: Int, id_bits: Int) extends Config((site, here, up) => { - case ExtIn => Some(SlavePortParams(beatBytes = data_width/8, idBits = id_bits, sourceBits = 4)) +class WithCustomManagerPort (data_width: Int, id_bits: Int) extends Config((site, here, up) => { + case ExtIn => Some(ManagerPortParams(beatBytes = data_width/8, idBits = id_bits, sourceBits = 4)) }) -class WithNoSlavePort extends Config((site, here, up) => { +class WithNoManagerPort extends Config((site, here, up) => { case ExtIn => None }) diff --git a/src/main/scala/subsystem/HasHierarchicalElements.scala b/src/main/scala/subsystem/HasHierarchicalElements.scala index d026395a417..a92ed3e7d1a 100644 --- a/src/main/scala/subsystem/HasHierarchicalElements.scala +++ b/src/main/scala/subsystem/HasHierarchicalElements.scala @@ -22,10 +22,10 @@ import freechips.rocketchip.util.TraceCoreInterface import scala.collection.immutable.SortedMap -/** A default implementation of parameterizing the connectivity of the port where the tile is the master. +/** A default implementation of parameterizing the connectivity of the port where the tile is the client. * Optional timing buffers and/or an optional CacheCork can be inserted in the interconnect's clock domain. */ -case class HierarchicalElementMasterPortParams( +case class HierarchicalElementClientPortParams( buffers: Int = 0, cork: Option[Boolean] = None, where: TLBusWrapperLocation = SBUS @@ -35,17 +35,17 @@ case class HierarchicalElementMasterPortParams( } } -object HierarchicalElementMasterPortParams { +object HierarchicalElementClientPortParams { def locationDefault(loc: HierarchicalLocation) = loc match { - case InSubsystem => HierarchicalElementMasterPortParams() - case InCluster(clusterId) => HierarchicalElementMasterPortParams(where=CSBUS(clusterId)) + case InSubsystem => HierarchicalElementClientPortParams() + case InCluster(clusterId) => HierarchicalElementClientPortParams(where=CSBUS(clusterId)) } } -/** A default implementation of parameterizing the connectivity of the port giving access to slaves inside the tile. +/** A default implementation of parameterizing the connectivity of the port giving access to managers inside the tile. * Optional timing buffers and/or an optional BusBlocker adapter can be inserted in the interconnect's clock domain. */ -case class HierarchicalElementSlavePortParams( +case class HierarchicalElementManagerPortParams( buffers: Int = 0, blockerCtrlAddr: Option[BigInt] = None, blockerCtrlWhere: TLBusWrapperLocation = CBUS, @@ -58,16 +58,16 @@ case class HierarchicalElementSlavePortParams( .map { BasicBusBlockerParams(_, blockerBus.beatBytes, controlBus.beatBytes) } .map { bbbp => val blocker = LazyModule(new BasicBusBlocker(bbbp)) - blockerBus.coupleTo("tile_slave_port_bus_blocker") { blocker.controlNode := TLFragmenter(blockerBus) := _ } + blockerBus.coupleTo("tile_manager_port_bus_blocker") { blocker.controlNode := TLFragmenter(blockerBus) := _ } blocker.node :*= TLBuffer.chainNode(buffers) } .getOrElse { TLBuffer.chainNode(buffers) } } } -object HierarchicalElementSlavePortParams { +object HierarchicalElementManagerPortParams { def locationDefault(loc: HierarchicalLocation) = loc match { - case InSubsystem => HierarchicalElementSlavePortParams() - case InCluster(clusterId) => HierarchicalElementSlavePortParams(where=CCBUS(clusterId), blockerCtrlWhere=CCBUS(clusterId)) + case InSubsystem => HierarchicalElementManagerPortParams() + case InCluster(clusterId) => HierarchicalElementManagerPortParams(where=CCBUS(clusterId), blockerCtrlWhere=CCBUS(clusterId)) } } diff --git a/src/main/scala/subsystem/HasTiles.scala b/src/main/scala/subsystem/HasTiles.scala index ea1f34f7e7b..2c4505e4b9f 100644 --- a/src/main/scala/subsystem/HasTiles.scala +++ b/src/main/scala/subsystem/HasTiles.scala @@ -168,8 +168,8 @@ trait CanAttachTile { /** A default set of connections that need to occur for most tile types */ def connect(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { - connectMasterPorts(domain, context) - connectSlavePorts(domain, context) + connectClientPorts(domain, context) + connectManagerPorts(domain, context) connectInterrupts(domain, context) connectPRC(domain, context) connectOutputNotifications(domain, context) @@ -177,22 +177,22 @@ trait CanAttachTile { connectTrace(domain, context) } - /** Connect the port where the tile is the master to a TileLink interconnect. */ - def connectMasterPorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { + /** Connect the port where the tile is the client to a TileLink interconnect. */ + def connectClientPorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p - val dataBus = context.locateTLBusWrapper(crossingParams.master.where) + val dataBus = context.locateTLBusWrapper(crossingParams.client.where) dataBus.coupleFrom(tileParams.baseName) { bus => - bus :=* crossingParams.master.injectNode(context) :=* domain.crossMasterPort(crossingParams.crossingType) + bus :=* crossingParams.client.injectNode(context) :=* domain.crossClientPort(crossingParams.crossingType) } } - /** Connect the port where the tile is the slave to a TileLink interconnect. */ - def connectSlavePorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { + /** Connect the port where the tile is the manager to a TileLink interconnect. */ + def connectManagerPorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p DisableMonitors { implicit p => - val controlBus = context.locateTLBusWrapper(crossingParams.slave.where) + val controlBus = context.locateTLBusWrapper(crossingParams.manager.where) controlBus.coupleTo(tileParams.baseName) { bus => - domain.crossSlavePort(crossingParams.crossingType) :*= crossingParams.slave.injectNode(context) :*= TLWidthWidget(controlBus.beatBytes) :*= bus + domain.crossManagerPort(crossingParams.crossingType) :*= crossingParams.manager.injectNode(context) :*= TLWidthWidget(controlBus.beatBytes) :*= bus } } } @@ -270,7 +270,7 @@ trait CanAttachTile { /** Connect power/reset/clock resources. */ def connectPRC(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p - val tlBusToGetClockDriverFrom = context.locateTLBusWrapper(crossingParams.master.where) + val tlBusToGetClockDriverFrom = context.locateTLBusWrapper(crossingParams.client.where) (crossingParams.crossingType match { case _: SynchronousCrossing | _: CreditedCrossing => if (crossingParams.forceSeparateClockReset) { diff --git a/src/main/scala/subsystem/HierarchicalElement.scala b/src/main/scala/subsystem/HierarchicalElement.scala index 861a77970e1..df433fac0e8 100644 --- a/src/main/scala/subsystem/HierarchicalElement.scala +++ b/src/main/scala/subsystem/HierarchicalElement.scala @@ -25,10 +25,10 @@ abstract class InstantiableHierarchicalElementParams[ElementType <: BaseHierarch trait HierarchicalElementCrossingParamsLike { /** The type of clock crossing that should be inserted at the element boundary. */ def crossingType: ClockCrossingType - /** Parameters describing the contents and behavior of the point where the element is attached as an interconnect master. */ - def master: HierarchicalElementPortParamsLike - /** Parameters describing the contents and behavior of the point where the element is attached as an interconnect slave. */ - def slave: HierarchicalElementPortParamsLike + /** Parameters describing the contents and behavior of the point where the element is attached as an interconnect client. */ + def client: HierarchicalElementPortParamsLike + /** Parameters describing the contents and behavior of the point where the element is attached as an interconnect manager. */ + def manager: HierarchicalElementPortParamsLike /** The subnetwork location of the device selecting the apparent base address of MMIO devices inside the element */ def mmioBaseAddressPrefixWhere: TLBusWrapperLocation /** Inject a reset management subgraph that effects the element child reset only */ @@ -51,29 +51,29 @@ abstract class BaseHierarchicalElement (val crossing: ClockCrossingType)(implici { def module: BaseHierarchicalElementModuleImp[BaseHierarchicalElement] - protected val tlOtherMastersNode = TLIdentityNode() - protected val tlMasterXbar = LazyModule(new TLXbar(nameSuffix = Some(s"MasterXbar_$desiredName"))) - protected val tlSlaveXbar = LazyModule(new TLXbar(nameSuffix = Some(s"SlaveXbar_$desiredName"))) + protected val tlOtherClientsNode = TLIdentityNode() + protected val tlClientXbar = LazyModule(new TLXbar(nameSuffix = Some(s"ClientXbar_$desiredName"))) + protected val tlManagerXbar = LazyModule(new TLXbar(nameSuffix = Some(s"ManagerXbar_$desiredName"))) protected val intXbar = LazyModule(new IntXbar) - def masterNode: TLOutwardNode - def slaveNode: TLInwardNode + def clientNode: TLOutwardNode + def managerNode: TLInwardNode - /** Helper function to insert additional buffers on master ports at the boundary of the tile. + /** Helper function to insert additional buffers on client ports at the boundary of the tile. * * The boundary buffering needed to cut feed-through paths is * microarchitecture specific, so this may need to be overridden * in subclasses of this class. */ - def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = TLBuffer(BufferParams.none) + def makeClientBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = TLBuffer(BufferParams.none) - /** Helper function to insert additional buffers on slave ports at the boundary of the tile. + /** Helper function to insert additional buffers on manager ports at the boundary of the tile. * * The boundary buffering needed to cut feed-through paths is * microarchitecture specific, so this may need to be overridden * in subclasses of this class. */ - def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = TLBuffer(BufferParams.none) + def makeManagerBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = TLBuffer(BufferParams.none) } diff --git a/src/main/scala/subsystem/HierarchicalElementPRCIDomain.scala b/src/main/scala/subsystem/HierarchicalElementPRCIDomain.scala index b38f208701e..b55c4fecd7d 100644 --- a/src/main/scala/subsystem/HierarchicalElementPRCIDomain.scala +++ b/src/main/scala/subsystem/HierarchicalElementPRCIDomain.scala @@ -74,27 +74,27 @@ abstract class HierarchicalElementPRCIDomain[T <: BaseHierarchicalElement]( intOutClockXing(crossingType) } - /** External code looking to connect the ports where this tile is slaved to an interconnect + /** External code looking to connect the ports where this tile is managerd to an interconnect * (while also crossing clock domains) can call this. */ - def crossSlavePort(crossingType: ClockCrossingType): TLInwardNode = { DisableMonitors { implicit p => FlipRendering { implicit p => - val tlSlaveResetXing = this { - element_reset_domain.crossTLIn(element.slaveNode) :*= - element { element.makeSlaveBoundaryBuffers(crossingType) } + def crossManagerPort(crossingType: ClockCrossingType): TLInwardNode = { DisableMonitors { implicit p => FlipRendering { implicit p => + val tlManagerResetXing = this { + element_reset_domain.crossTLIn(element.managerNode) :*= + element { element.makeManagerBoundaryBuffers(crossingType) } } - val tlSlaveClockXing = this.crossIn(tlSlaveResetXing) - tlSlaveClockXing(crossingType) + val tlManagerClockXing = this.crossIn(tlManagerResetXing) + tlManagerClockXing(crossingType) } } } - /** External code looking to connect the ports where this tile masters an interconnect + /** External code looking to connect the ports where this tile clients an interconnect * (while also crossing clock domains) can call this. */ - def crossMasterPort(crossingType: ClockCrossingType): TLOutwardNode = { - val tlMasterResetXing = this { DisableMonitors { implicit p => - element { element.makeMasterBoundaryBuffers(crossingType) } :=* - element_reset_domain.crossTLOut(element.masterNode) + def crossClientPort(crossingType: ClockCrossingType): TLOutwardNode = { + val tlClientResetXing = this { DisableMonitors { implicit p => + element { element.makeClientBoundaryBuffers(crossingType) } :=* + element_reset_domain.crossTLOut(element.clientNode) } } - val tlMasterClockXing = this.crossOut(tlMasterResetXing) - tlMasterClockXing(crossingType) + val tlClientClockXing = this.crossOut(tlClientResetXing) + tlClientClockXing(crossingType) } } diff --git a/src/main/scala/subsystem/Ports.scala b/src/main/scala/subsystem/Ports.scala index d3ed70c5e98..6df720ca8a2 100644 --- a/src/main/scala/subsystem/Ports.scala +++ b/src/main/scala/subsystem/Ports.scala @@ -10,9 +10,9 @@ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.axi4.{ - AXI4SlaveNode, AXI4SlavePortParameters, AXI4SlaveParameters, AXI4UserYanker, AXI4Buffer, - AXI4Deinterleaver, AXI4IdIndexer, AXI4MasterNode, AXI4MasterPortParameters, AXI4ToTL, - AXI4Fragmenter, AXI4MasterParameters + AXI4SubordinateNode, AXI4SubordinatePortParameters, AXI4SubordinateParameters, AXI4UserYanker, AXI4Buffer, + AXI4Deinterleaver, AXI4IdIndexer, AXI4ManagerNode, AXI4ManagerPortParameters, AXI4ToTL, + AXI4Fragmenter, AXI4ManagerParameters } import freechips.rocketchip.diplomacy.{ AddressSet, RegionType, TransferSizes, IdRange, BufferParams @@ -22,8 +22,8 @@ import freechips.rocketchip.resources.{ } import freechips.rocketchip.tilelink.{ TLXbar, RegionReplicator, ReplicatedRegion, TLWidthWidget, TLFilter, TLToAXI4, TLBuffer, - TLFIFOFixer, TLSlavePortParameters, TLManagerNode, TLSlaveParameters, TLClientNode, - TLSourceShrinker, TLMasterParameters, TLMasterPortParameters + TLFIFOFixer, TLManagerPortParameters, TLManagerNode, TLManagerParameters, TLClientNode, + TLSourceShrinker, TLClientParameters, TLClientPortParameters } import freechips.rocketchip.util.StringToAugmentedString @@ -31,7 +31,7 @@ import freechips.rocketchip.tilelink.TLClockDomainCrossing import freechips.rocketchip.tilelink.TLResetDomainCrossing /** Specifies the size and width of external memory ports */ -case class MasterPortParams( +case class ClientPortParams( base: BigInt, size: BigInt, beatBytes: Int, @@ -39,39 +39,39 @@ case class MasterPortParams( maxXferBytes: Int = 256, executable: Boolean = true) -/** Specifies the width of external slave ports */ -case class SlavePortParams(beatBytes: Int, idBits: Int, sourceBits: Int) +/** Specifies the width of external manager ports */ +case class ManagerPortParams(beatBytes: Int, idBits: Int, sourceBits: Int) // if incohBase is set, creates an incoherent alias for the region that hangs off the sbus -case class MemoryPortParams(master: MasterPortParams, nMemoryChannels: Int, incohBase: Option[BigInt] = None) +case class MemoryPortParams(client: ClientPortParams, nMemoryChannels: Int, incohBase: Option[BigInt] = None) case object ExtMem extends Field[Option[MemoryPortParams]](None) -case object ExtBus extends Field[Option[MasterPortParams]](None) -case object ExtIn extends Field[Option[SlavePortParams]](None) +case object ExtBus extends Field[Option[ClientPortParams]](None) +case object ExtIn extends Field[Option[ManagerPortParams]](None) ///// The following traits add ports to the sytem, in some cases converting to different interconnect standards -/** Adds a port to the system intended to master an AXI4 DRAM controller. */ -trait CanHaveMasterAXI4MemPort { this: BaseSubsystem => +/** Adds a port to the system intended to manager an AXI4 DRAM controller. */ +trait CanHaveManagerAXI4MemPort { this: BaseSubsystem => private val memPortParamsOpt = p(ExtMem) private val portName = "axi4" private val device = new MemoryDevice - private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1) + private val idBits = memPortParamsOpt.map(_.client.idBits).getOrElse(1) private val mbus = tlBusWrapperLocationMap.get(MBUS).getOrElse(viewpointBus) - val memAXI4Node = AXI4SlaveNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels, _) => + val memAXI4Node = AXI4SubordinateNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels, _) => Seq.tabulate(nMemoryChannels) { channel => val base = AddressSet.misaligned(memPortParams.base, memPortParams.size) val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes)) - AXI4SlavePortParameters( - slaves = Seq(AXI4SlaveParameters( + AXI4SubordinatePortParameters( + subordinates = Seq(AXI4SubordinateParameters( address = base.flatMap(_.intersect(filter)), resources = device.reg, regionType = RegionType.UNCACHED, // cacheable executable = true, supportsWrite = TransferSizes(1, mbus.blockBytes), supportsRead = TransferSizes(1, mbus.blockBytes), - interleavedId = Some(0))), // slave does not interleave read responses + interleavedId = Some(0))), // manager does not interleave read responses beatBytes = memPortParams.beatBytes) } }).toList.flatten) @@ -119,16 +119,16 @@ trait CanHaveMasterAXI4MemPort { this: BaseSubsystem => val mem_axi4 = InModuleBody { memAXI4Node.makeIOs() } } -/** Adds a AXI4 port to the system intended to master an MMIO device bus */ -trait CanHaveMasterAXI4MMIOPort { this: BaseSubsystem => +/** Adds a AXI4 port to the system intended to client an MMIO device bus */ +trait CanHaveManagerAXI4MMIOPort { this: BaseSubsystem => private val mmioPortParamsOpt = p(ExtBus) private val portName = "mmio_port_axi4" private val device = new SimpleBus(portName.kebab, Nil) - val mmioAXI4Node = AXI4SlaveNode( + val mmioAXI4Node = AXI4SubordinateNode( mmioPortParamsOpt.map(params => - AXI4SlavePortParameters( - slaves = Seq(AXI4SlaveParameters( + AXI4SubordinatePortParameters( + subordinates = Seq(AXI4SubordinateParameters( address = AddressSet.misaligned(params.base, params.size), resources = device.ranges, executable = params.executable, @@ -152,21 +152,21 @@ trait CanHaveMasterAXI4MMIOPort { this: BaseSubsystem => val mmio_axi4 = InModuleBody { mmioAXI4Node.makeIOs() } } -/** Adds an AXI4 port to the system intended to be a slave on an MMIO device bus */ -trait CanHaveSlaveAXI4Port { this: BaseSubsystem => - private val slavePortParamsOpt = p(ExtIn) - private val portName = "slave_port_axi4" +/** Adds an AXI4 port to the system intended to be a manager on an MMIO device bus */ +trait CanHaveSubordinateAXI4Port { this: BaseSubsystem => + private val subordinatePortParamsOpt = p(ExtIn) + private val portName = "subordinate_port_axi4" private val fifoBits = 1 private val fbus = tlBusWrapperLocationMap.get(FBUS).getOrElse(viewpointBus) - val l2FrontendAXI4Node = AXI4MasterNode( - slavePortParamsOpt.map(params => - AXI4MasterPortParameters( - masters = Seq(AXI4MasterParameters( + val l2FrontendAXI4Node = AXI4ManagerNode( + subordinatePortParamsOpt.map(params => + AXI4ManagerPortParameters( + managers = Seq(AXI4ManagerParameters( name = portName.kebab, id = IdRange(0, 1 << params.idBits))))).toSeq) - slavePortParamsOpt.map { params => + subordinatePortParamsOpt.map { params => fbus.coupleFrom(s"port_named_$portName") { ( _ := TLBuffer(BufferParams.default) @@ -183,16 +183,16 @@ trait CanHaveSlaveAXI4Port { this: BaseSubsystem => val l2_frontend_bus_axi4 = InModuleBody { l2FrontendAXI4Node.makeIOs() } } -/** Adds a TileLink port to the system intended to master an MMIO device bus */ -trait CanHaveMasterTLMMIOPort { this: BaseSubsystem => +/** Adds a TileLink port to the system intended to client an MMIO device bus */ +trait CanHaveClientTLMMIOPort { this: BaseSubsystem => private val mmioPortParamsOpt = p(ExtBus) private val portName = "mmio_port_tl" private val device = new SimpleBus(portName.kebab, Nil) val mmioTLNode = TLManagerNode( mmioPortParamsOpt.map(params => - TLSlavePortParameters.v1( - managers = Seq(TLSlaveParameters.v1( + TLManagerPortParameters.v1( + managers = Seq(TLManagerParameters.v1( address = AddressSet.misaligned(params.base, params.size), resources = device.ranges, executable = params.executable, @@ -217,21 +217,21 @@ trait CanHaveMasterTLMMIOPort { this: BaseSubsystem => } } -/** Adds an TL port to the system intended to be a slave on an MMIO device bus. +/** Adds an TL port to the system intended to be a manager on an MMIO device bus. * NOTE: this port is NOT allowed to issue Acquires. */ -trait CanHaveSlaveTLPort { this: BaseSubsystem => - private val slavePortParamsOpt = p(ExtIn) - private val portName = "slave_port_tl" +trait CanHaveManagerTLPort { this: BaseSubsystem => + private val managerPortParamsOpt = p(ExtIn) + private val portName = "manager_port_tl" val l2FrontendTLNode = TLClientNode( - slavePortParamsOpt.map(params => - TLMasterPortParameters.v1( - clients = Seq(TLMasterParameters.v1( + managerPortParamsOpt.map(params => + TLClientPortParameters.v1( + clients = Seq(TLClientParameters.v1( name = portName.kebab, sourceId = IdRange(0, 1 << params.idBits))))).toSeq) - slavePortParamsOpt.map { params => + managerPortParamsOpt.map { params => viewpointBus.coupleFrom(s"port_named_$portName") { ( _ := TLSourceShrinker(1 << params.sourceBits) diff --git a/src/main/scala/subsystem/RTC.scala b/src/main/scala/subsystem/RTC.scala index c2fd7a5a3f2..1d5cffebabd 100644 --- a/src/main/scala/subsystem/RTC.scala +++ b/src/main/scala/subsystem/RTC.scala @@ -15,7 +15,7 @@ trait HasRTCModuleImp extends LazyRawModuleImp { // Use the static period to toggle the RTC outer.clintDomainOpt.map { domain => { - val bus = outer.locateTLBusWrapper(p(CLINTAttachKey).slaveWhere) + val bus = outer.locateTLBusWrapper(p(CLINTAttachKey).managerWhere) val busFreq = bus.dtsFrequency.get val rtcFreq = outer.p(DTSTimebase) val internalPeriod: BigInt = busFreq / rtcFreq diff --git a/src/main/scala/subsystem/RocketSubsystem.scala b/src/main/scala/subsystem/RocketSubsystem.scala index a10903d050f..03e2686c82f 100644 --- a/src/main/scala/subsystem/RocketSubsystem.scala +++ b/src/main/scala/subsystem/RocketSubsystem.scala @@ -12,8 +12,8 @@ import freechips.rocketchip.util.HasCoreMonitorBundles case class RocketCrossingParams( crossingType: ClockCrossingType = SynchronousCrossing(), - master: HierarchicalElementPortParamsLike = HierarchicalElementMasterPortParams(), - slave: HierarchicalElementSlavePortParams = HierarchicalElementSlavePortParams(), + client: HierarchicalElementPortParamsLike = HierarchicalElementClientPortParams(), + manager: HierarchicalElementManagerPortParams = HierarchicalElementManagerPortParams(), mmioBaseAddressPrefixWhere: TLBusWrapperLocation = CBUS, resetCrossingType: ResetCrossingType = NoResetCrossing(), forceSeparateClockReset: Boolean = false diff --git a/src/main/scala/system/Configs.scala b/src/main/scala/system/Configs.scala index 19e3c174b23..e79f68eb6a8 100644 --- a/src/main/scala/system/Configs.scala +++ b/src/main/scala/system/Configs.scala @@ -14,7 +14,7 @@ class WithDebugAPB extends freechips.rocketchip.subsystem.WithDebugAPB class BaseConfig extends Config( new WithDefaultMemPort ++ new WithDefaultMMIOPort ++ - new WithDefaultSlavePort ++ + new WithDefaultManagerPort ++ new WithTimebase(BigInt(1000000)) ++ // 1 MHz new WithDTS("freechips,rocketchip-unknown", Nil) ++ new WithNExtTopInterrupts(2) ++ @@ -86,12 +86,12 @@ class TinyConfig extends Config( class MemPortOnlyConfig extends Config( new WithNoMMIOPort ++ - new WithNoSlavePort ++ + new WithNoManagerPort ++ new DefaultConfig ) class MMIOPortOnlyConfig extends Config( - new WithNoSlavePort ++ + new WithNoManagerPort ++ new WithNoMemPort ++ new WithNMemoryChannels(0) ++ new WithNBanks(0) ++ diff --git a/src/main/scala/system/ExampleRocketSystem.scala b/src/main/scala/system/ExampleRocketSystem.scala index 7267915c8fc..e8800b62027 100644 --- a/src/main/scala/system/ExampleRocketSystem.scala +++ b/src/main/scala/system/ExampleRocketSystem.scala @@ -10,9 +10,9 @@ import freechips.rocketchip.util.DontTouch /** Example Top with periphery devices and ports, and a Rocket subsystem */ class ExampleRocketSystem(implicit p: Parameters) extends RocketSubsystem with HasAsyncExtInterrupts - with CanHaveMasterAXI4MemPort - with CanHaveMasterAXI4MMIOPort - with CanHaveSlaveAXI4Port + with CanHaveManagerAXI4MemPort + with CanHaveManagerAXI4MMIOPort + with CanHaveSubordinateAXI4Port { // optionally add ROM devices // Note that setting BootROMLocated will override the reset_vector for all tiles diff --git a/src/main/scala/system/SimAXIMem.scala b/src/main/scala/system/SimAXIMem.scala index f0a08e6d5b8..bd111656441 100644 --- a/src/main/scala/system/SimAXIMem.scala +++ b/src/main/scala/system/SimAXIMem.scala @@ -8,21 +8,21 @@ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBACorrupt -import freechips.rocketchip.amba.axi4.{AXI4RAM, AXI4MasterNode, AXI4EdgeParameters, AXI4Xbar, AXI4Buffer, AXI4Fragmenter} +import freechips.rocketchip.amba.axi4.{AXI4RAM, AXI4ManagerNode, AXI4EdgeParameters, AXI4Xbar, AXI4Buffer, AXI4Fragmenter} import freechips.rocketchip.diplomacy.AddressSet -import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MMIOPort, CanHaveMasterAXI4MemPort, ExtBus, ExtMem} +import freechips.rocketchip.subsystem.{CanHaveManagerAXI4MMIOPort, CanHaveManagerAXI4MemPort, ExtBus, ExtMem} /** Memory with AXI port for use in elaboratable test harnesses. * - * Topology: AXIRAM <-< AXI4Buffer <-< AXI4Fragmenter <-< AXI4Xbar <-< AXI4MasterNode + * Topology: AXIRAM <-< AXI4Buffer <-< AXI4Fragmenter <-< AXI4Xbar <-< AXI4ManagerNode */ class SimAXIMem(edge: AXI4EdgeParameters, size: BigInt, base: BigInt = 0)(implicit p: Parameters) extends SimpleLazyModule { - val node = AXI4MasterNode(List(edge.master)) + val node = AXI4ManagerNode(List(edge.manager)) val srams = AddressSet.misaligned(base, size).map { aSet => LazyModule(new AXI4RAM( address = aSet, beatBytes = edge.bundle.dataBits/8, - wcorrupt=edge.slave.requestKeys.contains(AMBACorrupt))) + wcorrupt=edge.subordinate.requestKeys.contains(AMBACorrupt))) } val xbar = AXI4Xbar() srams.foreach{ s => s.node := AXI4Buffer() := AXI4Fragmenter() := xbar } @@ -31,12 +31,12 @@ class SimAXIMem(edge: AXI4EdgeParameters, size: BigInt, base: BigInt = 0)(implic } /** - * Connect Master AXI4 Mem/MMIO Port to SimAXIMem. + * Connect Manager AXI4 Mem/MMIO Port to SimAXIMem. */ object SimAXIMem { - def connectMMIO(dut: CanHaveMasterAXI4MMIOPort)(implicit p: Parameters): Seq[SimAXIMem] = { + def connectMMIO(dut: CanHaveManagerAXI4MMIOPort)(implicit p: Parameters): Seq[SimAXIMem] = { dut.mmio_axi4.zip(dut.mmioAXI4Node.in).map { case (io, (_, edge)) => - // test harness size capped to 4KB (ignoring p(ExtMem).get.master.size) + // test harness size capped to 4KB (ignoring p(ExtMem).get.manager.size) val mmio_mem = LazyModule(new SimAXIMem(edge, base = p(ExtBus).get.base, size = 4096)) Module(mmio_mem.module).suggestName("mmio_mem") mmio_mem.io_axi4.head <> io @@ -44,9 +44,9 @@ object SimAXIMem { }.toSeq } - def connectMem(dut: CanHaveMasterAXI4MemPort)(implicit p: Parameters): Seq[SimAXIMem] = { + def connectMem(dut: CanHaveManagerAXI4MemPort)(implicit p: Parameters): Seq[SimAXIMem] = { dut.mem_axi4.zip(dut.memAXI4Node.in).map { case (io, (_, edge)) => - val mem = LazyModule(new SimAXIMem(edge, base = p(ExtMem).get.master.base, size = p(ExtMem).get.master.size)) + val mem = LazyModule(new SimAXIMem(edge, base = p(ExtMem).get.client.base, size = p(ExtMem).get.client.size)) Module(mem.module).suggestName("mem") mem.io_axi4.head <> io mem From 529d2890f7ca9a1c464482b548d188d7a7e4e1c0 Mon Sep 17 00:00:00 2001 From: Alex Swehla Date: Thu, 26 Sep 2024 13:28:48 -0700 Subject: [PATCH 5/6] remove master/slave from rocket and tile --- src/main/scala/rocket/Configs.scala | 12 +- src/main/scala/rocket/DCache.scala | 14 +- src/main/scala/rocket/Frontend.scala | 12 +- src/main/scala/rocket/HellaCache.scala | 10 +- src/main/scala/rocket/ICache.scala | 142 +++++++++--------- src/main/scala/rocket/PMA.scala | 6 +- .../scala/rocket/ScratchpadSlavePort.scala | 10 +- src/main/scala/tile/BaseTile.scala | 14 +- src/main/scala/tile/LazyRoCC.scala | 10 +- src/main/scala/tile/RocketTile.scala | 34 ++--- 10 files changed, 132 insertions(+), 132 deletions(-) diff --git a/src/main/scala/rocket/Configs.scala b/src/main/scala/rocket/Configs.scala index a8f18cc2942..e3e7afb2e28 100644 --- a/src/main/scala/rocket/Configs.scala +++ b/src/main/scala/rocket/Configs.scala @@ -6,7 +6,7 @@ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.prci.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing, ClockCrossingType} -import freechips.rocketchip.subsystem.{TilesLocated, NumTiles, HierarchicalLocation, RocketCrossingParams, SystemBusKey, CacheBlockBytes, RocketTileAttachParams, InSubsystem, InCluster, HierarchicalElementMasterPortParams, HierarchicalElementSlavePortParams, CBUS, CCBUS, ClustersLocated, TileAttachConfig, CloneTileAttachParams} +import freechips.rocketchip.subsystem.{TilesLocated, NumTiles, HierarchicalLocation, RocketCrossingParams, SystemBusKey, CacheBlockBytes, RocketTileAttachParams, InSubsystem, InCluster, HierarchicalElementClientPortParams, HierarchicalElementManagerPortParams, CBUS, CCBUS, ClustersLocated, TileAttachConfig, CloneTileAttachParams} import freechips.rocketchip.tile.{RocketTileParams, RocketTileBoundaryBufferParams, FPUParams} import scala.reflect.ClassTag @@ -49,8 +49,8 @@ class WithNHugeCores( case NumTiles => up(NumTiles) + n }) { def this(n: Int, location: HierarchicalLocation = InSubsystem) = this(n, location, RocketCrossingParams( - master = HierarchicalElementMasterPortParams.locationDefault(location), - slave = HierarchicalElementSlavePortParams.locationDefault(location), + client = HierarchicalElementClientPortParams.locationDefault(location), + manager = HierarchicalElementManagerPortParams.locationDefault(location), mmioBaseAddressPrefixWhere = location match { case InSubsystem => CBUS case InCluster(clusterId) => CCBUS(clusterId) @@ -86,8 +86,8 @@ class WithNBigCores( case NumTiles => up(NumTiles) + n }) { def this(n: Int, location: HierarchicalLocation = InSubsystem) = this(n, location, RocketCrossingParams( - master = HierarchicalElementMasterPortParams.locationDefault(location), - slave = HierarchicalElementSlavePortParams.locationDefault(location), + client = HierarchicalElementClientPortParams.locationDefault(location), + manager = HierarchicalElementManagerPortParams.locationDefault(location), mmioBaseAddressPrefixWhere = location match { case InSubsystem => CBUS case InCluster(clusterId) => CCBUS(clusterId) @@ -192,7 +192,7 @@ class With1TinyCore extends Config((site, here, up) => { tiny, RocketCrossingParams( crossingType = SynchronousCrossing(), - master = HierarchicalElementMasterPortParams()) + client = HierarchicalElementClientPortParams()) )) } case NumTiles => 1 diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index edbd7328277..54e1fdf6917 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -923,13 +923,13 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { io.cpu.s2_gpa_is_pte := s2_tlb_xcpt.gpa_is_pte // report whether there are any outstanding accesses. disregard any - // slave-port accesses, since they don't affect local memory ordering. - val s1_isSlavePortAccess = s1_req.no_xcpt - val s2_isSlavePortAccess = s2_req.no_xcpt - io.cpu.ordered := !(s1_valid && !s1_isSlavePortAccess || s2_valid && !s2_isSlavePortAccess || cached_grant_wait || uncachedInFlight.asUInt.orR) + // manager-port accesses, since they don't affect local memory ordering. + val s1_isManagerPortAccess = s1_req.no_xcpt + val s2_isManagerPortAccess = s2_req.no_xcpt + io.cpu.ordered := !(s1_valid && !s1_isManagerPortAccess || s2_valid && !s2_isManagerPortAccess || cached_grant_wait || uncachedInFlight.asUInt.orR) io.cpu.store_pending := (cached_grant_wait && isWrite(s2_req.cmd)) || uncachedInFlight.asUInt.orR - val s1_xcpt_valid = tlb.io.req.valid && !s1_isSlavePortAccess && !s1_nack + val s1_xcpt_valid = tlb.io.req.valid && !s1_isManagerPortAccess && !s1_nack io.cpu.s2_xcpt := Mux(RegNext(s1_xcpt_valid), s2_tlb_xcpt, 0.U.asTypeOf(s2_tlb_xcpt)) if (usingDataScratchpad) { @@ -1139,8 +1139,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { property.CoverBoolean(data_error && !data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(data_error && data_error_uncorrectable, Seq("data_uncorrectable_error"))) val request_source = Seq( - property.CoverBoolean(s2_isSlavePortAccess, Seq("from_TL")), - property.CoverBoolean(!s2_isSlavePortAccess, Seq("from_CPU"))) + property.CoverBoolean(s2_isManagerPortAccess, Seq("from_TL")), + property.CoverBoolean(!s2_isManagerPortAccess, Seq("from_CPU"))) property.cover(new property.CrossProperty( Seq(data_error_cover, request_source), diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala index 8156e51c475..614c3385252 100644 --- a/src/main/scala/rocket/Frontend.scala +++ b/src/main/scala/rocket/Frontend.scala @@ -68,9 +68,9 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) { class Frontend(val icacheParams: ICacheParams, tileId: Int)(implicit p: Parameters) extends LazyModule { lazy val module = new FrontendModule(this) val icache = LazyModule(new ICache(icacheParams, tileId)) - val masterNode = icache.masterNode - val slaveNode = icache.slaveNode - val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(masterNode.edges.out.head.bundle.addressBits.W))) + val clientNode = icache.clientNode + val managerNode = icache.managerNode + val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(clientNode.edges.out.head.bundle.addressBits.W))) } class FrontendBundle(val outer: Frontend) extends CoreBundle()(outer.p) { @@ -84,7 +84,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) with HasL1ICacheParameters { val io = IO(new FrontendBundle(outer)) val io_reset_vector = outer.resetVectorSinkNode.bundle - implicit val edge: TLEdgeOut = outer.masterNode.edges.out(0) + implicit val edge: TLEdgeOut = outer.clientNode.edges.out(0) val icache = outer.icache.module require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes) @@ -391,8 +391,8 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) trait HasICacheFrontend extends CanHavePTW { this: BaseTile => val module: HasICacheFrontendModule val frontend = LazyModule(new Frontend(tileParams.icache.get, tileId)) - tlMasterXbar.node := TLWidthWidget(tileParams.icache.get.rowBits/8) := frontend.masterNode - connectTLSlave(frontend.slaveNode, tileParams.core.fetchBytes) + tlClientXbar.node := TLWidthWidget(tileParams.icache.get.rowBits/8) := frontend.clientNode + connectTLManager(frontend.managerNode, tileParams.core.fetchBytes) frontend.icache.hartIdSinkNodeOpt.foreach { _ := hartIdNexusNode } frontend.icache.mmioAddressPrefixSinkNodeOpt.foreach { _ := mmioAddressPrefixNexusNode } frontend.resetVectorSinkNode := resetVectorNexusNode diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index 29333c13fa3..c2a08c20311 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -13,7 +13,7 @@ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBAProtField import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} -import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} +import freechips.rocketchip.tilelink.{TLClientParameters, TLClientNode, TLClientPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} @@ -200,19 +200,19 @@ abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModul with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get - protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( + protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLClientParameters.v1( name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) - protected def mmioClientParameters = Seq(TLMasterParameters.v1( + protected def mmioClientParameters = Seq(TLClientParameters.v1( name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max - val node = TLClientNode(Seq(TLMasterPortParameters.v1( + val node = TLClientNode(Seq(TLClientPortParameters.v1( clients = cacheClientParameters ++ mmioClientParameters, minLatency = 1, requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) @@ -277,7 +277,7 @@ trait HasHellaCache { this: BaseTile => var nDCachePorts = 0 lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p)) - tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node + tlClientXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode } dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode } InModuleBody { diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index d3bf3c2119f..c922b2d26a4 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -16,7 +16,7 @@ import freechips.rocketchip.amba.{AMBAProt, AMBAProtField} import freechips.rocketchip.diplomacy.{IdRange, AddressSet, RegionType, TransferSizes} import freechips.rocketchip.resources.{SimpleDevice, ResourceBindings, Binding, ResourceAddress, Description, ResourceString, ResourceValue} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, TileKey, LookupByHartId} -import freechips.rocketchip.tilelink.{TLClientNode, TLMasterPortParameters, TLManagerNode, TLSlavePortParameters, TLSlaveParameters, TLMasterParameters, TLHints} +import freechips.rocketchip.tilelink.{TLClientNode, TLClientPortParameters, TLManagerNode, TLManagerPortParameters, TLManagerParameters, TLClientParameters, TLHints} import freechips.rocketchip.util.{Code, CanHaveErrors, DescribedSRAM, RandomReplacement, Split, IdentityCode, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean @@ -137,7 +137,7 @@ class ICache(val icacheParams: ICacheParams, val staticIdForMetadataUseOnly: Int /** Rocket configuration has virtual memory. * - * This only affect [[masterNode]] AMBA ports only: + * This only affect [[clientNode]] AMBA ports only: * AMBA privileged, secure will be set as true while others set as false. * see [[freechips.rocketchip.amba.AMBAProt]] for more informations. */ @@ -151,8 +151,8 @@ class ICache(val icacheParams: ICacheParams, val staticIdForMetadataUseOnly: Int * * @todo why if no [[useVM]], will have AMBAProtField in requestFields? */ - val masterNode = TLClientNode(Seq(TLMasterPortParameters.v1( - clients = Seq(TLMasterParameters.v1( + val clientNode = TLClientNode(Seq(TLClientPortParameters.v1( + clients = Seq(TLClientParameters.v1( sourceId = IdRange(0, 1 + icacheParams.prefetch.toInt), // 0=refill, 1=hint name = s"Core ${staticIdForMetadataUseOnly} ICache")), requestFields = useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) @@ -183,9 +183,9 @@ class ICache(val icacheParams: ICacheParams, val staticIdForMetadataUseOnly: Int private val wordBytes = icacheParams.fetchBytes /** Instruction Tightly Integrated Memory node. */ - val slaveNode = - TLManagerNode(icacheParams.itimAddr.toSeq.map { itimAddr => TLSlavePortParameters.v1( - Seq(TLSlaveParameters.v1( + val managerNode = + TLManagerNode(icacheParams.itimAddr.toSeq.map { itimAddr => TLManagerPortParameters.v1( + Seq(TLManagerParameters.v1( address = Seq(AddressSet(itimAddr, size-1)), resources = device.reg("mem"), regionType = RegionType.IDEMPOTENT, @@ -256,14 +256,14 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) val io = IO(new ICacheBundle(outer)) /** TileLink port to memory. */ - val (tl_out, edge_out) = outer.masterNode.out(0) + val (tl_out, edge_out) = outer.clientNode.out(0) /** TileLink port as ITIM memory. - * if [[outer.slaveNode]] is not connected [[outer.slaveNode.in]] will be empty. + * if [[outer.managerNode]] is not connected [[outer.managerNode.in]] will be empty. * * wes: Option.unzip does not exist :-( */ - val (tl_in, edge_in) = outer.slaveNode.in.headOption.unzip + val (tl_in, edge_in) = outer.managerNode.in.headOption.unzip val tECC = cacheParams.tagCode val dECC = cacheParams.dataCode @@ -322,15 +322,15 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) * │ line │ * }}} * @param addr address to be found. - * applied to slave_addr + * applied to manager_addr */ def scratchpadLine(addr: UInt) = addr(untagBits+log2Ceil(nWays)-1, blockOffBits) /** scratchpad access valid in stage N*/ - val s0_slaveValid = tl_in.map(_.a.fire).getOrElse(false.B) - val s1_slaveValid = RegNext(s0_slaveValid, false.B) - val s2_slaveValid = RegNext(s1_slaveValid, false.B) - val s3_slaveValid = RegNext(false.B) + val s0_managerValid = tl_in.map(_.a.fire).getOrElse(false.B) + val s1_managerValid = RegNext(s0_managerValid, false.B) + val s2_managerValid = RegNext(s1_managerValid, false.B) + val s3_managerValid = RegNext(false.B) /** valid signal for CPU accessing cache in stage 0. */ val s0_valid = io.req.fire @@ -346,19 +346,19 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) /** CPU I$ Hit in stage 1. * * @note - * for logic in `Mux(s1_slaveValid, true.B, addrMaybeInScratchpad(io.s1_paddr))`, + * for logic in `Mux(s1_managerValid, true.B, addrMaybeInScratchpad(io.s1_paddr))`, * there are two different types based on latency: * - * if latency is 1: `s1_slaveValid === false.B` and `addrMaybeInScratchpad(io.s1_paddr) === false.B` , + * if latency is 1: `s1_managerValid === false.B` and `addrMaybeInScratchpad(io.s1_paddr) === false.B` , * since in this case, ITIM must be empty. * - * if latency is 2: if `s1_slaveValid` is true, this SRAM accessing is coming from [[tl_in]], so it will hit. - * if `s1_slaveValid` is false, but CPU is accessing memory range in scratchpad address, it will hit by default. + * if latency is 2: if `s1_managerValid` is true, this SRAM accessing is coming from [[tl_in]], so it will hit. + * if `s1_managerValid` is false, but CPU is accessing memory range in scratchpad address, it will hit by default. * Hardware won't guarantee this access will access to a data which have been written in ITIM. * - * @todo seem CPU access are both processed by `s1_tag_hit` and `Mux(s1_slaveValid, true.B, addrMaybeInScratchpad(io.s1_paddr))`? + * @todo seem CPU access are both processed by `s1_tag_hit` and `Mux(s1_managerValid, true.B, addrMaybeInScratchpad(io.s1_paddr))`? */ - val s1_hit = s1_tag_hit.reduce(_||_) || Mux(s1_slaveValid, true.B, addrMaybeInScratchpad(io.s1_paddr)) + val s1_hit = s1_tag_hit.reduce(_||_) || Mux(s1_managerValid, true.B, addrMaybeInScratchpad(io.s1_paddr)) dontTouch(s1_hit) val s2_valid = RegNext(s1_valid && !io.s1_kill, false.B) val s2_hit = RegNext(s1_hit) @@ -391,14 +391,14 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) val refill_one_beat = tl_out.d.fire && edge_out.hasData(tl_out.d.bits) /** block request from CPU when refill or scratch pad access. */ - io.req.ready := !(refill_one_beat || s0_slaveValid || s3_slaveValid) + io.req.ready := !(refill_one_beat || s0_managerValid || s3_managerValid) s1_valid := s0_valid val (_, _, d_done, refill_cnt) = edge_out.count(tl_out.d) /** at last beat of `tl_out.d.fire`, finish refill. */ val refill_done = refill_one_beat && d_done /** scratchpad is writing data. block refill. */ - tl_out.d.ready := !s3_slaveValid + tl_out.d.ready := !s3_managerValid require (edge_out.manager.minLatency > 0) /** way to be replaced, implemented with a hardcoded random replacement algorithm */ @@ -474,19 +474,19 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) s1_dout := DontCare /** address accessed by [[tl_in]] for ITIM. */ - val s0_slaveAddr = tl_in.map(_.a.bits.address).getOrElse(0.U) + val s0_managerAddr = tl_in.map(_.a.bits.address).getOrElse(0.U) /** address used at stage 1 and 3. * {{{ * In stage 1, it caches TileLink data, store in stage 2 if ECC passed. * In stage 3, it caches corrected data from stage 2, and store in stage 4.}}} */ - val s1s3_slaveAddr = Reg(UInt(log2Ceil(outer.size).W)) + val s1s3_managerAddr = Reg(UInt(log2Ceil(outer.size).W)) /** data used at stage 1 and 3. * {{{ * In stage 1, it caches TileLink data, store in stage 2. * In stage 3, it caches corrected data from data ram, and return to d channel.}}} */ - val s1s3_slaveData = Reg(UInt(wordBits.W)) + val s1s3_managerData = Reg(UInt(wordBits.W)) for (i <- 0 until nWays) { val s1_idx = index(s1_vaddr, io.s1_paddr) @@ -495,17 +495,17 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) * [[tag_array]] corrupted. */ val scratchpadHit = scratchpadWayValid(i.U) && - Mux(s1_slaveValid, + Mux(s1_managerValid, // scratchpad accessing form [[tl_in]]. // @todo I think XBar will guarantee there won't be an illegal access on the bus? - // so why did have this check `lineInScratchpad(scratchpadLine(s1s3_slaveAddr))`? + // so why did have this check `lineInScratchpad(scratchpadLine(s1s3_managerAddr))`? // I think it will always be true. - lineInScratchpad(scratchpadLine(s1s3_slaveAddr)) && scratchpadWay(s1s3_slaveAddr) === i.U, + lineInScratchpad(scratchpadLine(s1s3_managerAddr)) && scratchpadWay(s1s3_managerAddr) === i.U, // scratchpad accessing from [[io]]. // @todo Accessing ITIM correspond address will be able to read cacheline? // is this desired behavior? addrInScratchpad(io.s1_paddr) && scratchpadWay(io.s1_paddr) === i.U) - val s1_vb = vb_array(Cat(i.U, s1_idx).pad(log2Ceil(nSets*nWays))) && !s1_slaveValid + val s1_vb = vb_array(Cat(i.U, s1_idx).pad(log2Ceil(nSets*nWays))) && !s1_managerValid val enc_tag = tECC.decode(tag_rdata(i)) /** [[tl_error]] ECC error bit. * [[tag]] of [[tag_array]] access. @@ -518,7 +518,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) s1_tl_error(i) := tagMatch && tl_error.asBool s1_tag_hit(i) := tagMatch || scratchpadHit } - assert(!(s1_valid || s1_slaveValid) || PopCount(s1_tag_hit zip s1_tag_disparity map { case (h, d) => h && !d }) <= 1.U) + assert(!(s1_valid || s1_managerValid) || PopCount(s1_tag_hit zip s1_tag_disparity map { case (h, d) => h && !d }) <= 1.U) require(tl_out.d.bits.data.getWidth % wordBits == 0) @@ -564,32 +564,32 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) def wordMatch(addr: UInt) = addr.extract(log2Ceil(tl_out.d.bits.data.getWidth/8)-1, log2Ceil(wordBits/8)) === i.U def row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)) /** read_enable signal*/ - val s0_ren = (s0_valid && wordMatch(s0_vaddr)) || (s0_slaveValid && wordMatch(s0_slaveAddr)) + val s0_ren = (s0_valid && wordMatch(s0_vaddr)) || (s0_managerValid && wordMatch(s0_managerAddr)) /** write_enable signal * refill from [[tl_out]] or ITIM write. */ - val wen = (refill_one_beat && !invalidated) || (s3_slaveValid && wordMatch(s1s3_slaveAddr)) + val wen = (refill_one_beat && !invalidated) || (s3_managerValid && wordMatch(s1s3_managerAddr)) /** index to access [[data_array]]. */ val mem_idx = // I$ refill. refill_idx[2:0] is the beats Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt, // ITIM write. - Mux(s3_slaveValid, row(s1s3_slaveAddr), + Mux(s3_managerValid, row(s1s3_managerAddr), // ITIM read. - Mux(s0_slaveValid, row(s0_slaveAddr), + Mux(s0_managerValid, row(s0_managerAddr), // CPU read. row(s0_vaddr)))) when (wen) { //wr_data - val data = Mux(s3_slaveValid, s1s3_slaveData, tl_out.d.bits.data(wordBits*(i+1)-1, wordBits*i)) + val data = Mux(s3_managerValid, s1s3_managerData, tl_out.d.bits.data(wordBits*(i+1)-1, wordBits*i)) //the way to be replaced/written - val way = Mux(s3_slaveValid, scratchpadWay(s1s3_slaveAddr), repl_way) + val way = Mux(s3_managerValid, scratchpadWay(s1s3_managerAddr), repl_way) data_array.write(mem_idx, VecInit(Seq.fill(nWays){dECC.encode(data)}), (0 until nWays).map(way === _.U)) } // write access /** data read from [[data_array]]. */ val dout = data_array.read(mem_idx, !wen && s0_ren) // Mux to select a way to [[s1_dout]] - when (wordMatch(Mux(s1_slaveValid, s1s3_slaveAddr, io.s1_paddr))) { + when (wordMatch(Mux(s1_managerValid, s1s3_managerAddr, io.s1_paddr))) { s1_dout := dout } } @@ -598,17 +598,17 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) * When writing a full scratchpad word, suppress the read so Xs don't leak out */ val s1s2_full_word_write = WireDefault(false.B) - val s1_dont_read = s1_slaveValid && s1s2_full_word_write + val s1_dont_read = s1_managerValid && s1s2_full_word_write /** clock gate signal for [[s2_tag_hit]], [[s2_dout]], [[s2_tag_disparity]], [[s2_tl_error]], [[s2_scratchpad_hit]]. */ - val s1_clk_en = s1_valid || s1_slaveValid + val s1_clk_en = s1_valid || s1_managerValid val s2_tag_hit = RegEnable(Mux(s1_dont_read, 0.U.asTypeOf(s1_tag_hit), s1_tag_hit), s1_clk_en) /** way index to access [[data_arrays]]. */ val s2_hit_way = OHToUInt(s2_tag_hit) /** ITIM index to access [[data_arrays]]. * replace tag with way, word set to 0. */ - val s2_scratchpad_word_addr = Cat(s2_hit_way, Mux(s2_slaveValid, s1s3_slaveAddr, io.s2_vaddr)(untagBits-1, log2Ceil(wordBits/8)), 0.U(log2Ceil(wordBits/8).W)) + val s2_scratchpad_word_addr = Cat(s2_hit_way, Mux(s2_managerValid, s1s3_managerAddr, io.s2_vaddr)(untagBits-1, log2Ceil(wordBits/8)), 0.U(log2Ceil(wordBits/8).W)) val s2_dout = RegEnable(s1_dout, s1_clk_en) val s2_way_mux = Mux1H(s2_tag_hit, s2_dout) val s2_tag_disparity = RegEnable(s1_tag_disparity, s1_clk_en).asUInt.orR @@ -617,19 +617,19 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) val s2_data_decoded = dECC.decode(s2_way_mux) /** ECC error happened, correctable or uncorrectable, ask CPU to replay. */ val s2_disparity = s2_tag_disparity || s2_data_decoded.error - /** access hit in ITIM, if [[s1_slaveValid]], this access is from [[tl_in]], else from CPU [[io]]. */ - val s1_scratchpad_hit = Mux(s1_slaveValid, lineInScratchpad(scratchpadLine(s1s3_slaveAddr)), addrInScratchpad(io.s1_paddr)) + /** access hit in ITIM, if [[s1_managerValid]], this access is from [[tl_in]], else from CPU [[io]]. */ + val s1_scratchpad_hit = Mux(s1_managerValid, lineInScratchpad(scratchpadLine(s1s3_managerAddr)), addrInScratchpad(io.s1_paddr)) /** stage 2 of [[s1_scratchpad_hit]]. */ val s2_scratchpad_hit = RegEnable(s1_scratchpad_hit, s1_clk_en) /** ITIM uncorrectable read. * `s2_scratchpad_hit`: processing a scratchpad read(from [[tl_in]] or [[io]]) * `s2_data_decoded.uncorrectable`: read a uncorrectable data. * `s2_valid`: [[io]] non-canceled read. - * `(s2_slaveValid && !s2_full_word_write)`: [[tl_in]] read or write a word with wormhole. + * `(s2_managerValid && !s2_full_word_write)`: [[tl_in]] read or write a word with wormhole. * if write a full word, even stage 2 read uncorrectable. * stage 3 full word write will recovery this. */ - val s2_report_uncorrectable_error = s2_scratchpad_hit && s2_data_decoded.uncorrectable && (s2_valid || (s2_slaveValid && !s1s2_full_word_write)) + val s2_report_uncorrectable_error = s2_scratchpad_hit && s2_data_decoded.uncorrectable && (s2_valid || (s2_managerValid && !s1s2_full_word_write)) /** ECC uncorrectable address, send to Bus Error Unit. */ val s2_error_addr = scratchpadBase.map(base => Mux(s2_scratchpad_hit, base + s2_scratchpad_word_addr, 0.U)).getOrElse(0.U) @@ -660,7 +660,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) // report correctable error to BEU at stage 2. io.errors.correctable.foreach { c => - c.valid := (s2_valid || s2_slaveValid) && s2_disparity && !s2_report_uncorrectable_error + c.valid := (s2_valid || s2_managerValid) && s2_disparity && !s2_report_uncorrectable_error c.bits := s2_error_addr } // report uncorrectable error to BEU at stage 2. @@ -674,18 +674,18 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) /** valid signal for D channel. */ val respValid = RegInit(false.B) // ITIM access is unpipelined - tl.a.ready := !(tl_out.d.valid || s1_slaveValid || s2_slaveValid || s3_slaveValid || respValid || !io.clock_enabled) + tl.a.ready := !(tl_out.d.valid || s1_managerValid || s2_managerValid || s3_managerValid || respValid || !io.clock_enabled) /** register used to latch TileLink request for one cycle. */ - val s1_a = RegEnable(tl.a.bits, s0_slaveValid) + val s1_a = RegEnable(tl.a.bits, s0_managerValid) // Write Data(Put / PutPartial all mask is 1) s1s2_full_word_write := edge_in.get.hasData(s1_a) && s1_a.mask.andR // (de)allocate ITIM - when (s0_slaveValid) { + when (s0_managerValid) { val a = tl.a.bits // address - s1s3_slaveAddr := tl.a.bits.address + s1s3_managerAddr := tl.a.bits.address // store Put/PutP data - s1s3_slaveData := tl.a.bits.data + s1s3_managerData := tl.a.bits.data // S0 when (edge_in.get.hasData(a)) { // access data in 0 -> way - 2 allocate and enable, access data in way - 1(last way), deallocate. @@ -711,37 +711,37 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) } assert(!s2_valid || RegNext(RegNext(s0_vaddr)) === io.s2_vaddr) - when (!(tl.a.valid || s1_slaveValid || s2_slaveValid || respValid) + when (!(tl.a.valid || s1_managerValid || s2_managerValid || respValid) && s2_valid && s2_data_decoded.error && !s2_tag_disparity) { // handle correctable errors on CPU accesses to the scratchpad. - // if there is an in-flight slave-port access to the scratchpad, + // if there is an in-flight manager-port access to the scratchpad, // report the miss but don't correct the error (as there is - // a structural hazard on s1s3_slaveData/s1s3_slaveAddress). - s3_slaveValid := true.B - s1s3_slaveData := s2_data_decoded.corrected - s1s3_slaveAddr := s2_scratchpad_word_addr | s1s3_slaveAddr(log2Ceil(wordBits/8)-1, 0) + // a structural hazard on s1s3_managerData/s1s3_managerAddress). + s3_managerValid := true.B + s1s3_managerData := s2_data_decoded.corrected + s1s3_managerAddr := s2_scratchpad_word_addr | s1s3_managerAddr(log2Ceil(wordBits/8)-1, 0) } // back pressure is allowed on the [[tl]] - // pull up [[respValid]] when [[s2_slaveValid]] until [[tl.d.fire]] - respValid := s2_slaveValid || (respValid && !tl.d.ready) + // pull up [[respValid]] when [[s2_managerValid]] until [[tl.d.fire]] + respValid := s2_managerValid || (respValid && !tl.d.ready) // if [[s2_full_word_write]] will overwrite data, and [[s2_data_decoded.uncorrectable]] can be ignored. - val respError = RegEnable(s2_scratchpad_hit && s2_data_decoded.uncorrectable && !s1s2_full_word_write, s2_slaveValid) - when (s2_slaveValid) { + val respError = RegEnable(s2_scratchpad_hit && s2_data_decoded.uncorrectable && !s1s2_full_word_write, s2_managerValid) + when (s2_managerValid) { // need stage 3 if Put or correct decoding. // @todo if uncorrectable [[s2_data_decoded]]? - when (edge_in.get.hasData(s1_a) || s2_data_decoded.error) { s3_slaveValid := true.B } + when (edge_in.get.hasData(s1_a) || s2_data_decoded.error) { s3_managerValid := true.B } /** data not masked by the TileLink PutData/PutPartialData. - * means data is stored at [[s1s3_slaveData]] which was read at stage 1. + * means data is stored at [[s1s3_managerData]] which was read at stage 1. */ def byteEn(i: Int) = !(edge_in.get.hasData(s1_a) && s1_a.mask(i)) - // write [[s1s3_slaveData]] based on index of wordBits. + // write [[s1s3_managerData]] based on index of wordBits. // @todo seems a problem here? // granularity of CPU fetch is `wordBits/8`, // granularity of TileLink access is `TLBundleParameters.dataBits/8` // these two granularity can be different. // store data read from RAM - s1s3_slaveData := (0 until wordBits/8).map(i => Mux(byteEn(i), s2_data_decoded.corrected, s1s3_slaveData)(8*(i+1)-1, 8*i)).asUInt + s1s3_managerData := (0 until wordBits/8).map(i => Mux(byteEn(i), s2_data_decoded.corrected, s1s3_managerData)(8*(i+1)-1, 8*i)).asUInt } tl.d.valid := respValid @@ -750,14 +750,14 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) edge_in.get.AccessAck(s1_a), // Get -> AccessAckData edge_in.get.AccessAck(s1_a, 0.U, denied = false.B, corrupt = respError)) - tl.d.bits.data := s1s3_slaveData + tl.d.bits.data := s1s3_managerData // Tie off unused channels tl.b.valid := false.B tl.c.ready := true.B tl.e.ready := true.B - ccover(s0_valid && s1_slaveValid, "CONCURRENT_ITIM_ACCESS_1", "ITIM accessed, then I$ accessed next cycle") - ccover(s0_valid && s2_slaveValid, "CONCURRENT_ITIM_ACCESS_2", "ITIM accessed, then I$ accessed two cycles later") + ccover(s0_valid && s1_managerValid, "CONCURRENT_ITIM_ACCESS_1", "ITIM accessed, then I$ accessed next cycle") + ccover(s0_valid && s2_managerValid, "CONCURRENT_ITIM_ACCESS_2", "ITIM accessed, then I$ accessed two cycles later") ccover(tl.d.valid && !tl.d.ready, "ITIM_D_STALL", "ITIM response blocked by D-channel") ccover(tl_out.d.valid && !tl_out.d.ready, "ITIM_BLOCK_D", "D-channel blocked by ITIM access") } @@ -833,7 +833,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) io.perf.acquire := refill_fire // don't gate I$ clock since there are outstanding transcations. io.keep_clock_enabled := - tl_in.map(tl => tl.a.valid || tl.d.valid || s1_slaveValid || s2_slaveValid || s3_slaveValid).getOrElse(false.B) || // ITIM + tl_in.map(tl => tl.a.valid || tl.d.valid || s1_managerValid || s2_managerValid || s3_managerValid).getOrElse(false.B) || // ITIM s1_valid || s2_valid || refill_valid || send_hint || hint_outstanding // I$ /** index to access [[data_arrays]] and [[tag_array]]. @@ -874,8 +874,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) property.CoverBoolean(s2_data_decoded.correctable, Seq("data_correctable_error")), property.CoverBoolean(s2_data_decoded.uncorrectable, Seq("data_uncorrectable_error"))) val request_source = Seq( - property.CoverBoolean(!s2_slaveValid, Seq("from_CPU")), - property.CoverBoolean(s2_slaveValid, Seq("from_TL")) + property.CoverBoolean(!s2_managerValid, Seq("from_CPU")), + property.CoverBoolean(s2_managerValid, Seq("from_TL")) ) val tag_error = Seq( property.CoverBoolean(!s2_tag_disparity, Seq("no_tag_error")), diff --git a/src/main/scala/rocket/PMA.scala b/src/main/scala/rocket/PMA.scala index b2144e6b38a..55bd1a8d2c0 100644 --- a/src/main/scala/rocket/PMA.scala +++ b/src/main/scala/rocket/PMA.scala @@ -13,9 +13,9 @@ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} -import freechips.rocketchip.tilelink.{TLSlavePortParameters, TLManagerParameters} +import freechips.rocketchip.tilelink.{TLManagerPortParameters, TLManagerParameters} -class PMAChecker(manager: TLSlavePortParameters)(implicit p: Parameters) extends CoreModule()(p) { +class PMAChecker(manager: TLManagerPortParameters)(implicit p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { val paddr = Input(UInt()) @@ -32,7 +32,7 @@ class PMAChecker(manager: TLSlavePortParameters)(implicit p: Parameters) extends }) // PMA - // check exist a slave can consume this address. + // check exist a manager can consume this address. val legal_address = manager.findSafe(io.paddr).reduce(_||_) // check utility to help check SoC property. def fastCheck(member: TLManagerParameters => Boolean) = diff --git a/src/main/scala/rocket/ScratchpadSlavePort.scala b/src/main/scala/rocket/ScratchpadSlavePort.scala index 8b613aa09de..cf034a98e52 100644 --- a/src/main/scala/rocket/ScratchpadSlavePort.scala +++ b/src/main/scala/rocket/ScratchpadSlavePort.scala @@ -11,21 +11,21 @@ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes} import freechips.rocketchip.resources.{SimpleDevice} -import freechips.rocketchip.tilelink.{TLManagerNode, TLSlavePortParameters, TLSlaveParameters, TLBundleA, TLMessages, TLAtomics} +import freechips.rocketchip.tilelink.{TLManagerNode, TLManagerPortParameters, TLManagerParameters, TLBundleA, TLMessages, TLAtomics} import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.DataToAugmentedData /* This adapter converts between diplomatic TileLink and non-diplomatic HellaCacheIO */ -class ScratchpadSlavePort(address: Seq[AddressSet], coreDataBytes: Int, usingAtomics: Boolean)(implicit p: Parameters) extends LazyModule { +class ScratchpadManagerPort(address: Seq[AddressSet], coreDataBytes: Int, usingAtomics: Boolean)(implicit p: Parameters) extends LazyModule { def this(address: AddressSet, coreDataBytes: Int, usingAtomics: Boolean)(implicit p: Parameters) = { this(Seq(address), coreDataBytes, usingAtomics) } val device = new SimpleDevice("dtim", Seq("sifive,dtim0")) - val node = TLManagerNode(Seq(TLSlavePortParameters.v1( - Seq(TLSlaveParameters.v1( + val node = TLManagerNode(Seq(TLManagerPortParameters.v1( + Seq(TLManagerParameters.v1( address = address, resources = device.reg("mem"), regionType = RegionType.IDEMPOTENT, @@ -45,7 +45,7 @@ class ScratchpadSlavePort(address: Seq[AddressSet], coreDataBytes: Int, usingAto val dmem = new HellaCacheIO }) - require(coreDataBytes * 8 == io.dmem.resp.bits.data.getWidth, "ScratchpadSlavePort is misconfigured: coreDataBytes must match D$ data width") + require(coreDataBytes * 8 == io.dmem.resp.bits.data.getWidth, "ScratchpadManagerPort is misconfigured: coreDataBytes must match D$ data width") val (tl_in, edge) = node.in(0) diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index 263b73c69a8..24bd66da6cc 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -90,7 +90,7 @@ trait HasNonDiplomaticTileParameters { def cacheBlockBytes = p(CacheBlockBytes) def lgCacheBlockBytes = log2Up(cacheBlockBytes) - def masterPortBeatBytes = p(SystemBusKey).beatBytes + def clientPortBeatBytes = p(SystemBusKey).beatBytes // TODO make HellaCacheIO diplomatic and remove this brittle collection of hacks // Core PTW DTIM coprocessors @@ -219,7 +219,7 @@ abstract class BaseTile private (crossing: ClockCrossingType, q: Parameters) def this(tileParams: TileParams, crossing: ClockCrossingType, lookup: LookupByHartIdImpl, p: Parameters) = { this(crossing, p.alterMap(Map( TileKey -> tileParams, - TileVisibilityNodeKey -> TLEphemeralNode()(ValName("tile_master")), + TileVisibilityNodeKey -> TLEphemeralNode()(ValName("tile_client")), LookupByHartId -> lookup ))) } @@ -252,7 +252,7 @@ abstract class BaseTile private (crossing: ClockCrossingType, q: Parameters) /** Node for consuming the reset vector input in tile-layer Chisel logic. * * Its width is sized by looking at the size of the address space visible - * on the tile's master ports, but this lookup is not evaluated until + * on the tile's client ports, but this lookup is not evaluated until * diplomacy has completed and Chisel elaboration has begun. */ val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(visiblePhysAddrBits.W))) @@ -321,17 +321,17 @@ abstract class BaseTile private (crossing: ClockCrossingType, q: Parameters) val bpwatchNode: BundleBridgeOutwardNode[Vec[BPWatch]] = BundleBridgeNameNode("bpwatch") :*= bpwatchNexusNode := bpwatchSourceNode - /** Helper function for connecting MMIO devices inside the tile to an xbar that will make them visible to external masters. */ - def connectTLSlave(xbarNode: TLOutwardNode, node: TLNode, bytes: Int): Unit = { + /** Helper function for connecting MMIO devices inside the tile to an xbar that will make them visible to external clients. */ + def connectTLManager(xbarNode: TLOutwardNode, node: TLNode, bytes: Int): Unit = { DisableMonitors { implicit p => (Seq(node, TLFragmenter(bytes, cacheBlockBytes, earlyAck=EarlyAck.PutFulls)) ++ (xBytes != bytes).option(TLWidthWidget(xBytes))) .foldRight(xbarNode)(_ :*= _) } } - def connectTLSlave(node: TLNode, bytes: Int): Unit = { connectTLSlave(tlSlaveXbar.node, node, bytes) } + def connectTLManager(node: TLNode, bytes: Int): Unit = { connectTLManager(tlManagerXbar.node, node, bytes) } - /** TileLink node which represents the view that the intra-tile masters have of the rest of the system. */ + /** TileLink node which represents the view that the intra-tile clients have of the rest of the system. */ val visibilityNode = p(TileVisibilityNodeKey) protected def visibleManagers = visibilityNode.edges.out.flatMap(_.manager.managers) protected def visiblePhysAddrBits = visibilityNode.edges.out.head.bundle.addressBits diff --git a/src/main/scala/tile/LazyRoCC.scala b/src/main/scala/tile/LazyRoCC.scala index 3b869b9aca4..e88f033ee04 100644 --- a/src/main/scala/tile/LazyRoCC.scala +++ b/src/main/scala/tile/LazyRoCC.scala @@ -15,7 +15,7 @@ import freechips.rocketchip.rocket.{ SimpleHellaCacheIF, M_XRD, PTE, PRV, M_SZ } import freechips.rocketchip.tilelink.{ - TLNode, TLIdentityNode, TLClientNode, TLMasterParameters, TLMasterPortParameters + TLNode, TLIdentityNode, TLClientNode, TLClientParameters, TLClientPortParameters } import freechips.rocketchip.util.InOrderArbiter @@ -86,9 +86,9 @@ trait HasLazyRoCC extends CanHavePTW { this: BaseTile => val roccCSRs = roccs.map(_.roccCSRs) // the set of custom CSRs requested by all roccs require(roccCSRs.flatten.map(_.id).toSet.size == roccCSRs.flatten.size, "LazyRoCC instantiations require overlapping CSRs") - roccs.map(_.atlNode).foreach { atl => tlMasterXbar.node :=* atl } - roccs.map(_.tlNode).foreach { tl => tlOtherMastersNode :=* tl } - roccs.map(_.stlNode).foreach { stl => stl :*= tlSlaveXbar.node } + roccs.map(_.atlNode).foreach { atl => tlClientXbar.node :=* atl } + roccs.map(_.tlNode).foreach { tl => tlOtherClientsNode :=* tl } + roccs.map(_.stlNode).foreach { stl => stl :*= tlManagerXbar.node } nPTWPorts += roccs.map(_.nPTWPorts).sum nDCachePorts += roccs.size @@ -236,7 +236,7 @@ class TranslatorExampleModuleImp(outer: TranslatorExample)(implicit p: Parameter class CharacterCountExample(opcodes: OpcodeSet)(implicit p: Parameters) extends LazyRoCC(opcodes) { override lazy val module = new CharacterCountExampleModuleImp(this) - override val atlNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1("CharacterCountRoCC"))))) + override val atlNode = TLClientNode(Seq(TLClientPortParameters.v1(Seq(TLClientParameters.v1("CharacterCountRoCC"))))) } class CharacterCountExampleModuleImp(outer: CharacterCountExample)(implicit p: Parameters) extends LazyRoCCModuleImp(outer) diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index 619e7d836ca..5a259bfa8ad 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -20,7 +20,7 @@ import freechips.rocketchip.interrupts.IntIdentityNode import freechips.rocketchip.tilelink.{TLIdentityNode, TLBuffer} import freechips.rocketchip.rocket.{ RocketCoreParams, ICacheParams, DCacheParams, BTBParams, HasHellaCache, - HasICacheFrontend, ScratchpadSlavePort, HasICacheFrontendModule, Rocket + HasICacheFrontend, ScratchpadManagerPort, HasICacheFrontendModule, Rocket } import freechips.rocketchip.subsystem.HierarchicalElementCrossingParamsLike import freechips.rocketchip.prci.{ClockSinkParameters, RationalCrossing, ClockCrossingType} @@ -68,32 +68,32 @@ class RocketTile private( this(params, crossing.crossingType, lookup, p) val intOutwardNode = rocketParams.beuAddr map { _ => IntIdentityNode() } - val slaveNode = TLIdentityNode() - val masterNode = visibilityNode + val managerNode = TLIdentityNode() + val clientNode = visibilityNode val dtim_adapter = tileParams.dcache.flatMap { d => d.scratch.map { s => - LazyModule(new ScratchpadSlavePort(AddressSet.misaligned(s, d.dataScratchpadBytes), lazyCoreParamsView.coreDataBytes, tileParams.core.useAtomics && !tileParams.core.useAtomicsOnlyForIO)) + LazyModule(new ScratchpadManagerPort(AddressSet.misaligned(s, d.dataScratchpadBytes), lazyCoreParamsView.coreDataBytes, tileParams.core.useAtomics && !tileParams.core.useAtomicsOnlyForIO)) }} - dtim_adapter.foreach(lm => connectTLSlave(lm.node, lm.node.portParams.head.beatBytes)) + dtim_adapter.foreach(lm => connectTLManager(lm.node, lm.node.portParams.head.beatBytes)) val bus_error_unit = rocketParams.beuAddr map { a => val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a), xLen/8)) intOutwardNode.get := beu.intNode - connectTLSlave(beu.node, xBytes) + connectTLManager(beu.node, xBytes) beu } - val tile_master_blocker = + val tile_client_blocker = tileParams.blockerCtrlAddr - .map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true)) + .map(BasicBusBlockerParams(_, xBytes, clientPortBeatBytes, deadlock = true)) .map(bp => LazyModule(new BasicBusBlocker(bp))) - tile_master_blocker.foreach(lm => connectTLSlave(lm.controlNode, xBytes)) + tile_client_blocker.foreach(lm => connectTLManager(lm.controlNode, xBytes)) - // TODO: this doesn't block other masters, e.g. RoCCs - tlOtherMastersNode := tile_master_blocker.map { _.node := tlMasterXbar.node } getOrElse { tlMasterXbar.node } - masterNode :=* tlOtherMastersNode - DisableMonitors { implicit p => tlSlaveXbar.node :*= slaveNode } + // TODO: this doesn't block other clients, e.g. RoCCs + tlOtherClientsNode := tile_client_blocker.map { _.node := tlClientXbar.node } getOrElse { tlClientXbar.node } + clientNode :=* tlOtherClientsNode + DisableMonitors { implicit p => tlManagerXbar.node :*= managerNode } nDCachePorts += 1 /*core */ + (dtim_adapter.isDefined).toInt + rocketParams.core.vector.map(_.useDCache.toInt).getOrElse(0) @@ -115,8 +115,8 @@ class RocketTile private( } val vector_unit = rocketParams.core.vector.map(v => LazyModule(v.build(p))) - vector_unit.foreach(vu => tlMasterXbar.node :=* vu.atlNode) - vector_unit.foreach(vu => tlOtherMastersNode :=* vu.tlNode) + vector_unit.foreach(vu => tlClientXbar.node :=* vu.atlNode) + vector_unit.foreach(vu => tlOtherClientsNode :=* vu.tlNode) ResourceBinding { @@ -125,13 +125,13 @@ class RocketTile private( override lazy val module = new RocketTileModuleImp(this) - override def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (rocketParams.boundaryBuffers, crossing) match { + override def makeClientBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (rocketParams.boundaryBuffers, crossing) match { case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer() case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)) case _ => TLBuffer(BufferParams.none) } - override def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (rocketParams.boundaryBuffers, crossing) match { + override def makeManagerBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (rocketParams.boundaryBuffers, crossing) match { case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer() case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none) case _ => TLBuffer(BufferParams.none) From d56bcb051b13ea6d09b916c9992df7dfc4580e09 Mon Sep 17 00:00:00 2001 From: Alex Swehla Date: Thu, 26 Sep 2024 13:29:15 -0700 Subject: [PATCH 6/6] remove master/slave from remaining modules --- src/main/scala/diplomacy/Parameters.scala | 4 +- src/main/scala/formal/FormalUtils.scala | 4 +- src/main/scala/groundtest/Configs.scala | 6 +- .../groundtest/GroundTestSubsystem.scala | 2 +- src/main/scala/groundtest/Tile.scala | 2 +- src/main/scala/groundtest/TraceGen.scala | 2 +- src/main/scala/jtag/JtagTap.scala | 2 +- src/main/scala/jtag/JtagUtils.scala | 2 +- .../scala/regmapper/RegisterCrossing.scala | 203 +++++++++--------- src/main/scala/regmapper/Test.scala | 26 +-- src/main/scala/unittest/Configs.scala | 2 +- src/main/scala/util/Annotations.scala | 6 +- src/main/scala/util/BundleMap.scala | 6 +- 13 files changed, 133 insertions(+), 134 deletions(-) diff --git a/src/main/scala/diplomacy/Parameters.scala b/src/main/scala/diplomacy/Parameters.scala index ef28b918aa5..0bfeb54e324 100644 --- a/src/main/scala/diplomacy/Parameters.scala +++ b/src/main/scala/diplomacy/Parameters.scala @@ -15,7 +15,7 @@ object RegionType { } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you - case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided + case object TRACKED extends T // the region may have been cached by another client, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects @@ -119,7 +119,7 @@ object TransferSizes { def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) - implicit def asBool(x: TransferSizes) = !x.none + implicit def asBool(x: TransferSizes): Boolean = !x.none } // AddressSets specify the address space managed by the manager diff --git a/src/main/scala/formal/FormalUtils.scala b/src/main/scala/formal/FormalUtils.scala index 07922d789fc..7b3a3a599f3 100644 --- a/src/main/scala/formal/FormalUtils.scala +++ b/src/main/scala/formal/FormalUtils.scala @@ -12,10 +12,10 @@ sealed abstract class MonitorDirection(name: String) { def flip: MonitorDirection } object MonitorDirection { - // Also known as master, effectively contains assumes + // Also known as client, effectively contains assumes object Driver extends MonitorDirection("Driver") { override def flip: MonitorDirection = Receiver } - // Also known as slave, effectively contains asserts + // Also known as manager, effectively contains asserts object Receiver extends MonitorDirection("Receiver") { override def flip: MonitorDirection = Driver } object Monitor extends MonitorDirection("Monitor") { override def flip: MonitorDirection = Monitor } diff --git a/src/main/scala/groundtest/Configs.scala b/src/main/scala/groundtest/Configs.scala index e9b00689aa9..d51503ee258 100644 --- a/src/main/scala/groundtest/Configs.scala +++ b/src/main/scala/groundtest/Configs.scala @@ -6,10 +6,10 @@ package freechips.rocketchip.groundtest import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.tilelink.{CLINTKey, PLICKey} -import freechips.rocketchip.devices.debug.{DebugModuleKey} +import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.subsystem._ import freechips.rocketchip.system.BaseConfig -import freechips.rocketchip.rocket.{DCacheParams} +import freechips.rocketchip.rocket.DCacheParams /** Actual testing target Configs */ @@ -44,7 +44,7 @@ class WithTraceGen( case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) val idOffset = up(NumTiles) - val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L) + val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.client.base)).getOrElse(0x0L) params.zipWithIndex.map { case (dcp, i) => TraceGenTileAttachParams( tileParams = TraceGenParams( diff --git a/src/main/scala/groundtest/GroundTestSubsystem.scala b/src/main/scala/groundtest/GroundTestSubsystem.scala index 11263966ebf..4c5a9655dca 100644 --- a/src/main/scala/groundtest/GroundTestSubsystem.scala +++ b/src/main/scala/groundtest/GroundTestSubsystem.scala @@ -23,7 +23,7 @@ class GroundTestSubsystem(implicit p: Parameters) with HasHierarchicalElements with HasTileNotificationSinks with HasTileInputConstants - with CanHaveMasterAXI4MemPort + with CanHaveManagerAXI4MemPort { val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), beatBytes=tlBusWrapperLocationMap.get(PBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))).beatBytes)) tlBusWrapperLocationMap.lift(PBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))).coupleTo("TestRAM") { testram.node := TLFragmenter(tlBusWrapperLocationMap.lift(PBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))))) := _ } diff --git a/src/main/scala/groundtest/Tile.scala b/src/main/scala/groundtest/Tile.scala index c9516ab4965..f6a18afa1e1 100644 --- a/src/main/scala/groundtest/Tile.scala +++ b/src/main/scala/groundtest/Tile.scala @@ -40,7 +40,7 @@ abstract class GroundTestTile( { val cpuDevice: SimpleDevice = new SimpleDevice("groundtest", Nil) val intOutwardNode = None - val slaveNode: TLInwardNode = TLIdentityNode() + val managerNode: TLInwardNode = TLIdentityNode() val statusNode = BundleBridgeSource(() => new GroundTestStatus) val dcacheOpt = params.dcache.map { dc => LazyModule(p(BuildHellaCache)(this)(p)) } diff --git a/src/main/scala/groundtest/TraceGen.scala b/src/main/scala/groundtest/TraceGen.scala index 588f930978d..5be57ae2c0a 100644 --- a/src/main/scala/groundtest/TraceGen.scala +++ b/src/main/scala/groundtest/TraceGen.scala @@ -622,7 +622,7 @@ class TraceGenTile private( def this(params: TraceGenParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = this(params, crossing.crossingType, lookup, p) - val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcacheOpt.map(_.node).getOrElse(TLTempNode()) + val clientNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcacheOpt.map(_.node).getOrElse(TLTempNode()) override lazy val module = new TraceGenTileModuleImp(this) } diff --git a/src/main/scala/jtag/JtagTap.scala b/src/main/scala/jtag/JtagTap.scala index e477c2d5246..3323abe352a 100644 --- a/src/main/scala/jtag/JtagTap.scala +++ b/src/main/scala/jtag/JtagTap.scala @@ -7,7 +7,7 @@ import scala.collection.SortedMap import chisel3._ import org.chipsalliance.cde.config.Parameters -/** JTAG signals, viewed from the master side +/** JTAG signals, viewed from the driver side */ class JTAGIO(hasTRSTn: Boolean = false) extends Bundle { val TRSTn = if (hasTRSTn) Some(Output(Bool())) else None diff --git a/src/main/scala/jtag/JtagUtils.scala b/src/main/scala/jtag/JtagUtils.scala index 12180944b75..0efcee0e76c 100644 --- a/src/main/scala/jtag/JtagUtils.scala +++ b/src/main/scala/jtag/JtagUtils.scala @@ -21,7 +21,7 @@ object JtagIdcode { BigInt(version) << 28 | BigInt(partNumber) << 12 | BigInt(mfrId) << 1 | 1 } - /** A dummy manufacturer ID, not to be used per 12.2.1b since bus masters may shift this out to + /** A dummy manufacturer ID, not to be used per 12.2.1b since bus drivers may shift this out to * determine the end of a bus. */ def dummyMfrId: Int = 0x7f diff --git a/src/main/scala/regmapper/RegisterCrossing.scala b/src/main/scala/regmapper/RegisterCrossing.scala index 37fce9ed40e..cc430ae46b2 100644 --- a/src/main/scala/regmapper/RegisterCrossing.scala +++ b/src/main/scala/regmapper/RegisterCrossing.scala @@ -11,10 +11,10 @@ import freechips.rocketchip.util.{AsyncQueue,AsyncQueueParams,AsyncResetRegVec} class BusyRegisterCrossing extends Module { val io = IO(new Bundle { val bypass = Input(Bool()) - val master_request_valid = Input(Bool()) - val master_request_ready = Output(Bool()) - val master_response_valid = Output(Bool()) - val master_response_ready = Input(Bool()) + val client_request_valid = Input(Bool()) + val client_request_ready = Output(Bool()) + val client_response_valid = Output(Bool()) + val client_response_ready = Input(Bool()) val crossing_request_valid = Output(Bool()) val crossing_request_ready = Input(Bool()) // ... no crossing_response_ready; we are always ready @@ -24,50 +24,49 @@ class BusyRegisterCrossing extends Module { val bypass = Reg(Bool()) when (io.crossing_request_ready || Mux(busy, bypass, io.bypass)) { - busy := Mux(busy, !io.master_response_ready, io.master_request_valid) + busy := Mux(busy, !io.client_response_ready, io.client_request_valid) } - when (io.master_request_valid && io.master_request_ready) { + when (io.client_request_valid && io.client_request_ready) { bypass := io.bypass } - io.crossing_request_valid := io.master_request_valid && !io.bypass && !busy - io.master_request_ready := (io.bypass || io.crossing_request_ready) && !busy - io.master_response_valid := (bypass || io.crossing_request_ready) && busy + io.crossing_request_valid := io.client_request_valid && !io.bypass && !busy + io.client_request_ready := (io.bypass || io.crossing_request_ready) && !busy + io.client_response_valid := (bypass || io.crossing_request_ready) && busy } class RegisterCrossingAssertion extends Module { val io = IO(new Bundle { - val master_bypass = Input(Bool()) - val slave_reset = Input(Bool()) + val client_bypass = Input(Bool()) + val manager_reset = Input(Bool()) }) val up = RegInit(false.B) - up := !io.slave_reset + up := !io.manager_reset - assert (io.master_bypass || !up || !io.slave_reset) + assert (io.client_bypass || !up || !io.manager_reset) } // RegField should support connecting to one of these class RegisterWriteIO[T <: Data](gen: T) extends Bundle { val request = Flipped(Decoupled(gen)) val response = Irrevocable(Bool()) // ignore .bits - } // To turn off=>on a domain: -// A. To turn disable the master domain +// A. To turn disable the client domain // 1. wait for all inflight traffic to resolve -// 2. assert master reset -// 3. (optional) stop the master clock +// 2. assert client reset +// 3. (optional) stop the client clock // --- YOU MAY NOT TURN OFF POWER --- // 4. re-enable the clock // 5. deassert reset -// B. To turn off the slave domain +// B. To turn off the manager domain // 1. assert bypass // 2. wait for inflight traffic to resolve -// 3. assert slave reset -// 4. (optional) stop the slave clock +// 3. assert manager reset +// 4. (optional) stop the manager clock // --- YOU MAY NOT TURN OFF POWER --- // 5. re-enable the clock // 6. deassert reset @@ -76,17 +75,17 @@ class RegisterWriteIO[T <: Data](gen: T) extends Bundle { // If you need to cut power, use something that support isolation gates. class RegisterWriteCrossingIO[T <: Data](gen: T) extends Bundle { - // Master clock domain - val master_clock = Input(Clock()) - val master_reset = Input(Bool()) - val master_port = new RegisterWriteIO(gen) - // Bypass requests from the master to be noops - val master_bypass = Input(Bool()) - // Slave clock domain - val slave_clock = Input(Clock()) - val slave_reset = Input(Bool()) - val slave_register = Output(gen) - val slave_valid = Output(Bool()) // is high on 1st cycle slave_register has a new value + // client clock domain + val client_clock = Input(Clock()) + val client_reset = Input(Bool()) + val client_port = new RegisterWriteIO(gen) + // Bypass requests from the client to be noops + val client_bypass = Input(Bool()) + // manager clock domain + val manager_clock = Input(Clock()) + val manager_reset = Input(Bool()) + val manager_register = Output(gen) + val manager_valid = Output(Bool()) // is high on 1st cycle manager_register has a new value } class RegisterWriteCrossing[T <: Data](gen: T, sync: Int = 3) extends Module { @@ -95,33 +94,33 @@ class RegisterWriteCrossing[T <: Data](gen: T, sync: Int = 3) extends Module { val control = Module(new BusyRegisterCrossing) val crossing = Module(new AsyncQueue(gen, AsyncQueueParams.singleton(sync))) - control.clock := io.master_clock - control.reset := io.master_reset - crossing.io.enq_clock := io.master_clock - crossing.io.enq_reset := io.master_reset - crossing.io.deq_clock := io.slave_clock - crossing.io.deq_reset := io.slave_reset + control.clock := io.client_clock + control.reset := io.client_reset + crossing.io.enq_clock := io.client_clock + crossing.io.enq_reset := io.client_reset + crossing.io.deq_clock := io.manager_clock + crossing.io.deq_reset := io.manager_reset - control.io.bypass := io.master_bypass - control.io.master_request_valid := io.master_port.request.valid - control.io.master_response_ready := io.master_port.response.ready - io.master_port.request.ready := control.io.master_request_ready - io.master_port.response.valid := control.io.master_response_valid - io.master_port.response.bits := DontCare + control.io.bypass := io.client_bypass + control.io.client_request_valid := io.client_port.request.valid + control.io.client_response_ready := io.client_port.response.ready + io.client_port.request.ready := control.io.client_request_ready + io.client_port.response.valid := control.io.client_response_valid + io.client_port.response.bits := DontCare control.io.crossing_request_ready := crossing.io.enq.ready crossing.io.enq.valid := control.io.crossing_request_valid - crossing.io.enq.bits := io.master_port.request.bits + crossing.io.enq.bits := io.client_port.request.bits crossing.io.deq.ready := true.B - io.slave_valid := crossing.io.deq.valid - io.slave_register := crossing.io.deq.bits + io.manager_valid := crossing.io.deq.valid + io.manager_register := crossing.io.deq.bits val assertion = Module(new RegisterCrossingAssertion) - assertion.clock := io.master_clock - assertion.reset := io.master_reset - assertion.io.master_bypass := io.master_bypass - assertion.io.slave_reset := io.slave_reset + assertion.clock := io.client_clock + assertion.reset := io.client_reset + assertion.io.client_bypass := io.client_bypass + assertion.io.manager_reset := io.manager_reset } // RegField should support connecting to one of these @@ -132,16 +131,16 @@ class RegisterReadIO[T <: Data](gen: T) extends Bundle { } class RegisterReadCrossingIO[T <: Data](gen: T) extends Bundle { - // Master clock domain - val master_clock = Input(Clock()) - val master_reset = Input(Bool()) - val master_port = new RegisterReadIO(gen) - // Bypass requests from the master to be noops - val master_bypass = Input(Bool()) - // Slave clock domain - val slave_clock = Input(Clock()) - val slave_reset = Input(Bool()) - val slave_register = Input(gen) + // client clock domain + val client_clock = Input(Clock()) + val client_reset = Input(Bool()) + val client_port = new RegisterReadIO(gen) + // Bypass requests from the client to be noops + val client_bypass = Input(Bool()) + // manager clock domain + val manager_clock = Input(Clock()) + val manager_reset = Input(Bool()) + val manager_register = Input(gen) } class RegisterReadCrossing[T <: Data](gen: T, sync: Int = 3) extends Module { @@ -150,35 +149,35 @@ class RegisterReadCrossing[T <: Data](gen: T, sync: Int = 3) extends Module { val control = Module(new BusyRegisterCrossing) val crossing = Module(new AsyncQueue(gen, AsyncQueueParams.singleton(sync))) - control.clock := io.master_clock - control.reset := io.master_reset - crossing.io.deq_clock := io.master_clock - crossing.io.deq_reset := io.master_reset - crossing.io.enq_clock := io.slave_clock - crossing.io.enq_reset := io.slave_reset + control.clock := io.client_clock + control.reset := io.client_reset + crossing.io.deq_clock := io.client_clock + crossing.io.deq_reset := io.client_reset + crossing.io.enq_clock := io.manager_clock + crossing.io.enq_reset := io.manager_reset - control.io.bypass := io.master_bypass - control.io.master_request_valid := io.master_port.request.valid - control.io.master_response_ready := io.master_port.response.ready - io.master_port.request.ready := control.io.master_request_ready - io.master_port.response.valid := control.io.master_response_valid + control.io.bypass := io.client_bypass + control.io.client_request_valid := io.client_port.request.valid + control.io.client_response_ready := io.client_port.response.ready + io.client_port.request.ready := control.io.client_request_ready + io.client_port.response.valid := control.io.client_response_valid control.io.crossing_request_ready := crossing.io.deq.valid crossing.io.deq.ready := control.io.crossing_request_valid - io.master_port.response.bits := crossing.io.deq.bits + io.client_port.response.bits := crossing.io.deq.bits crossing.io.enq.valid := true.B - crossing.io.enq.bits := io.slave_register + crossing.io.enq.bits := io.manager_register val assertion = Module(new RegisterCrossingAssertion) - assertion.clock := io.master_clock - assertion.reset := io.master_reset - assertion.io.master_bypass := io.master_bypass - assertion.io.slave_reset := io.slave_reset + assertion.clock := io.client_clock + assertion.reset := io.client_reset + assertion.io.client_bypass := io.client_bypass + assertion.io.manager_reset := io.manager_reset } /** Wrapper to create an - * asynchronously reset slave register which can be + * asynchronously reset manager register which can be * both read and written * using crossing FIFOs. * The reset and allow assertion & de-assertion @@ -186,48 +185,48 @@ class RegisterReadCrossing[T <: Data](gen: T, sync: Int = 3) extends Module { * domains. */ -object AsyncRWSlaveRegField { +object AsyncRWManagerRegField { def apply( - master_clock: Clock, - master_reset: Bool, - slave_clock: Clock, - slave_reset: Bool, + client_clock: Clock, + client_reset: Bool, + manager_clock: Clock, + manager_reset: Bool, width: Int, init: Int, name: Option[String] = None, - master_bypass: Bool = true.B, + client_bypass: Bool = true.B, desc: Option[RegFieldDesc] = None ): (UInt, RegField) = { - val async_slave_reg = Module(new AsyncResetRegVec(width, init)) - name.foreach(async_slave_reg.suggestName(_)) - async_slave_reg.reset := slave_reset - async_slave_reg.clock := slave_clock + val async_manager_reg = Module(new AsyncResetRegVec(width, init)) + name.foreach(async_manager_reg.suggestName(_)) + async_manager_reg.reset := manager_reset + async_manager_reg.clock := manager_clock val wr_crossing = Module (new RegisterWriteCrossing(UInt(width.W))) name.foreach(n => wr_crossing.suggestName(s"${n}_wcrossing")) - wr_crossing.io.master_clock := master_clock - wr_crossing.io.master_reset := master_reset - wr_crossing.io.master_bypass := master_bypass - wr_crossing.io.slave_clock := slave_clock - wr_crossing.io.slave_reset := slave_reset + wr_crossing.io.client_clock := client_clock + wr_crossing.io.client_reset := client_reset + wr_crossing.io.client_bypass := client_bypass + wr_crossing.io.manager_clock := manager_clock + wr_crossing.io.manager_reset := manager_reset - async_slave_reg.io.en := wr_crossing.io.slave_valid - async_slave_reg.io.d := wr_crossing.io.slave_register + async_manager_reg.io.en := wr_crossing.io.manager_valid + async_manager_reg.io.d := wr_crossing.io.manager_register val rd_crossing = Module (new RegisterReadCrossing(UInt(width.W))) name.foreach(n => rd_crossing.suggestName(s"${n}_rcrossing")) - rd_crossing.io.master_clock := master_clock - rd_crossing.io.master_reset := master_reset - rd_crossing.io.master_bypass := master_bypass - rd_crossing.io.slave_clock := slave_clock - rd_crossing.io.slave_reset := slave_reset + rd_crossing.io.client_clock := client_clock + rd_crossing.io.client_reset := client_reset + rd_crossing.io.client_bypass := client_bypass + rd_crossing.io.manager_clock := manager_clock + rd_crossing.io.manager_reset := manager_reset - rd_crossing.io.slave_register := async_slave_reg.io.q + rd_crossing.io.manager_register := async_manager_reg.io.q - (async_slave_reg.io.q, RegField(width, rd_crossing.io.master_port, wr_crossing.io.master_port, desc)) + (async_manager_reg.io.q, RegField(width, rd_crossing.io.client_port, wr_crossing.io.client_port, desc)) } } diff --git a/src/main/scala/regmapper/Test.scala b/src/main/scala/regmapper/Test.scala index 0faedd84cfb..55eb690d72c 100644 --- a/src/main/scala/regmapper/Test.scala +++ b/src/main/scala/regmapper/Test.scala @@ -235,22 +235,22 @@ abstract class RRTest1(address: BigInt, concurrency: Int, undefZero: Boolean = t val readCross = Module(new RegisterReadCrossing(field)) readCross.io := DontCare - readCross.io.master_clock := clock - readCross.io.master_reset := reset - readCross.io.master_bypass := false.B - readCross.io.slave_clock := clocks.io.clock_out - readCross.io.slave_reset := reset + readCross.io.client_clock := clock + readCross.io.client_reset := reset + readCross.io.client_bypass := false.B + readCross.io.manager_clock := clocks.io.clock_out + readCross.io.manager_reset := reset val writeCross = Module(new RegisterWriteCrossing(field)) writeCross.io := DontCare - writeCross.io.master_clock := clock - writeCross.io.master_reset := reset - writeCross.io.master_bypass := false.B - writeCross.io.slave_clock := clocks.io.clock_out - writeCross.io.slave_reset := reset - - readCross.io.slave_register := writeCross.io.slave_register - RegField(bits, readCross.io.master_port, writeCross.io.master_port) + writeCross.io.client_clock := clock + writeCross.io.client_reset := reset + writeCross.io.client_bypass := false.B + writeCross.io.manager_clock := clocks.io.clock_out + writeCross.io.manager_reset := reset + + readCross.io.manager_register := writeCross.io.manager_register + RegField(bits, readCross.io.client_port, writeCross.io.client_port) } val map = RRTest1Map.map.drop(1) ++ Seq(0 -> Seq(x(8), x(8), x(8), x(8))) diff --git a/src/main/scala/unittest/Configs.scala b/src/main/scala/unittest/Configs.scala index 655811576b8..18c3c686989 100644 --- a/src/main/scala/unittest/Configs.scala +++ b/src/main/scala/unittest/Configs.scala @@ -92,7 +92,7 @@ class WithTLXbarUnitTests extends Config((site, here, up) => { Module(new TLRAMXbarTest(2, txns=5*txns, timeout=timeout)), Module(new TLRAMXbarTest(8, txns=5*txns, timeout=timeout)), Module(new TLMulticlientXbarTest(4,4, txns=2*txns, timeout=timeout)), - Module(new TLMasterMuxTest( txns=5*txns, timeout=timeout)) ) } + Module(new TLClientMuxTest( txns=5*txns, timeout=timeout)) ) } }) class WithECCTests extends Config((site, here, up) => { diff --git a/src/main/scala/util/Annotations.scala b/src/main/scala/util/Annotations.scala index 851571ba46e..4c14be9ce5e 100644 --- a/src/main/scala/util/Annotations.scala +++ b/src/main/scala/util/Annotations.scala @@ -70,8 +70,8 @@ case class RetimeModuleAnnotation(target: ModuleName) extends SingleTargetAnnota def duplicate(n: ModuleName) = this.copy(n) } -/** Annotation capturing information about port slave devices. */ -case class SlaveAddressMapChiselAnnotation( +/** Annotation capturing information about port manager devices. */ +case class ManagerAddressMapChiselAnnotation( target: InstanceId, addresses: Seq[AddressSet], perms: ResourcePermissions) extends ChiselAnnotation { @@ -79,7 +79,7 @@ case class SlaveAddressMapChiselAnnotation( def toFirrtl = AddressMapAnnotation( target = target.toNamed, mapping = range.map { r => AddressMapEntry(r, perms, Nil) }, - label = "slaves") + label = "managers") } /** Record information about a top-level port of the design */ diff --git a/src/main/scala/util/BundleMap.scala b/src/main/scala/util/BundleMap.scala index 2b8dc0a1911..aea9c2ab7de 100644 --- a/src/main/scala/util/BundleMap.scala +++ b/src/main/scala/util/BundleMap.scala @@ -88,9 +88,9 @@ abstract class ControlKey[T <: Data](name: String) extends BundleKey[T](name) wi abstract class DataKey [T <: Data](name: String) extends BundleKey[T](name) with IsDataKey /* Signals can be further categorized in a request-response protocol: - * - request fields flow from master to slave - * - response fields flow from slave to master - * - echo fields flow from master to slave to master; a master must receive the same value in the response as he sent in the request + * - request fields flow from client to manager + * - response fields flow from manager to client + * - echo fields flow from client to manager to client; a client must receive the same value in the response as he sent in the request * Generally, this categorization belongs in different BundleMaps */