From 977fc491e2e01e90795ef4b6c2a9e64b7e12bc03 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Thu, 21 Nov 2024 17:52:26 +0100 Subject: [PATCH 01/11] use axi_lsu_dma_bridge in configuration with ahb --- testbench/tb_top.sv | 449 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 426 insertions(+), 23 deletions(-) diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index 60b393f22f6..411d53a05fa 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -44,6 +44,133 @@ module tb_top ); `endif + wire bridge_m_axi_awvalid; + wire bridge_m_axi_awready; + wire [4-1:0] bridge_m_axi_awid; + wire [31:0] bridge_m_axi_awaddr; + wire [3:0] bridge_m_axi_awregion; + wire [7:0] bridge_m_axi_awlen; + wire [2:0] bridge_m_axi_awsize; + wire [1:0] bridge_m_axi_awburst; + wire bridge_m_axi_awlock; + wire [3:0] bridge_m_axi_awcache; + wire [2:0] bridge_m_axi_awprot; + wire [3:0] bridge_m_axi_awqos; + + wire bridge_m_axi_wvalid; + wire bridge_m_axi_wready; + wire [63:0] bridge_m_axi_wdata; + wire [7:0] bridge_m_axi_wstrb; + wire bridge_m_axi_wlast; + + wire bridge_m_axi_bvalid; + wire bridge_m_axi_bready; + wire [1:0] bridge_m_axi_bresp; + wire [4-1:0] bridge_m_axi_bid; + + // AXI Read Channels + wire bridge_m_axi_arvalid; + wire bridge_m_axi_arready; + wire [4-1:0] bridge_m_axi_arid; + wire [31:0] bridge_m_axi_araddr; + wire [3:0] bridge_m_axi_arregion; + wire [7:0] bridge_m_axi_arlen; + wire [2:0] bridge_m_axi_arsize; + wire [1:0] bridge_m_axi_arburst; + wire bridge_m_axi_arlock; + wire [3:0] bridge_m_axi_arcache; + wire [2:0] bridge_m_axi_arprot; + wire [3:0] bridge_m_axi_arqos; + + wire bridge_m_axi_rvalid; + wire bridge_m_axi_rready; + wire [4-1:0] bridge_m_axi_rid; + wire [63:0] bridge_m_axi_rdata; + wire [1:0] bridge_m_axi_rresp; + wire bridge_m_axi_rlast; + wire bridge_m_axi_awuser; + wire bridge_m_axi_wuser; + wire bridge_m_axi_buser; + wire bridge_m_axi_aruser; + wire bridge_m_axi_ruser; + + + wire bridge_s0_awvalid; + wire bridge_s0_awready; + wire [`RV_DMA_BUS_TAG-1:0] bridge_s0_awid; + wire [31:0] bridge_s0_awaddr; + wire [2:0] bridge_s0_awsize; + wire [2:0] bridge_s0_awprot; + wire [7:0] bridge_s0_awlen; + wire [1:0] bridge_s0_awburst; + wire bridge_s0_wvalid; + wire bridge_s0_wready; + wire [63:0] bridge_s0_wdata; + wire [7:0] bridge_s0_wstrb; + wire bridge_s0_wlast; + wire bridge_s0_bvalid; + wire bridge_s0_bready; + wire [1:0] bridge_s0_bresp; + wire [`RV_DMA_BUS_TAG-1:0] bridge_s0_bid; + wire bridge_s0_arvalid; + wire bridge_s0_arready; + wire [`RV_DMA_BUS_TAG-1:0] bridge_s0_arid; + wire [31:0] bridge_s0_araddr; + wire [2:0] bridge_s0_arsize; + wire [2:0] bridge_s0_arprot; + wire [7:0] bridge_s0_arlen; + wire [1:0] bridge_s0_arburst; + wire bridge_s0_rvalid; + wire bridge_s0_rready; + wire [`RV_DMA_BUS_TAG-1:0] bridge_s0_rid; + wire [63:0] bridge_s0_rdata; + wire [1:0] bridge_s0_rresp; + wire bridge_s0_rlast; + + + wire bridge_s1_dma_axi_awvalid; + wire bridge_s1_dma_axi_awready; + wire [`RV_DMA_BUS_TAG-1:0] bridge_s1_dma_axi_awid; + wire [31:0] bridge_s1_dma_axi_awaddr; + wire [2:0] bridge_s1_dma_axi_awsize; + wire [2:0] bridge_s1_dma_axi_awprot; + wire [7:0] bridge_s1_dma_axi_awlen; + wire [1:0] bridge_s1_dma_axi_awburst; + wire bridge_s1_dma_axi_wvalid; + wire bridge_s1_dma_axi_wready; + wire [63:0] bridge_s1_dma_axi_wdata; + wire [7:0] bridge_s1_dma_axi_wstrb; + wire bridge_s1_dma_axi_wlast; + wire bridge_s1_dma_axi_bvalid; + wire bridge_s1_dma_axi_bready; + wire [1:0] bridge_s1_dma_axi_bresp; + wire [`RV_DMA_BUS_TAG-1:0] bridge_s1_dma_axi_bid; + wire bridge_s1_dma_axi_arvalid; + wire bridge_s1_dma_axi_arready; + wire [`RV_DMA_BUS_TAG-1:0] bridge_s1_dma_axi_arid; + wire [31:0] bridge_s1_dma_axi_araddr; + wire [2:0] bridge_s1_dma_axi_arsize; + wire [2:0] bridge_s1_dma_axi_arprot; + wire [7:0] bridge_s1_dma_axi_arlen; + wire [1:0] bridge_s1_dma_axi_arburst; + wire bridge_s1_dma_axi_rvalid; + wire bridge_s1_dma_axi_rready; + wire [`RV_DMA_BUS_TAG-1:0] bridge_s1_dma_axi_rid; + wire [63:0] bridge_s1_dma_axi_rdata; + wire [1:0] bridge_s1_dma_axi_rresp; + wire bridge_s1_dma_axi_rlast; + + logic [31:0] dma_haddr ; + logic [2:0] dma_hburst ; + logic dma_hmastlock ; + logic [3:0] dma_hprot ; + logic [2:0] dma_hsize ; + logic [1:0] dma_htrans ; + logic dma_hwrite ; + logic dma_hreadyout ; + logic dma_hreadyin ; + logic dma_hsel ; + `ifndef VERILATOR bit core_clk; bit [31:0] mem_signature_begin = 32'd0; // TODO: @@ -100,6 +227,21 @@ module tb_top logic mux_hresp ; logic mux_hreadyout ; + logic [31:0] mux_haddr_from_bridge ; + logic [2:0] mux_hburst_from_bridge ; + logic mux_hmastlock_from_bridge ; + logic [3:0] mux_hprot_from_bridge ; + logic [2:0] mux_hsize_from_bridge ; + logic [1:0] mux_htrans_from_bridge ; + logic mux_hwrite_from_bridge ; + logic mux_hsel_from_bridge ; + logic [63:0] mux_hrdata_from_bridge ; + logic [63:0] mux_hwdata_from_bridge ; + logic mux_hready_from_bridge ; + logic mux_hresp_from_bridge ; + logic mux_hreadyout_from_bridge ; + logic lsu_hmastlock_from_bridge ; + logic [31:0] sb_haddr ; logic [2:0] sb_hburst ; logic sb_hmastlock ; @@ -225,7 +367,6 @@ module tb_top `ifdef RV_BUILD_AXI4 //-------------------------- LSU AXI signals-------------------------- // AXI Write Channels - parameter int RV_MUX_BUS_TAG = (`RV_LSU_BUS_TAG > `RV_SB_BUS_TAG ? `RV_LSU_BUS_TAG : `RV_SB_BUS_TAG) + 1; wire lsu_axi_awvalid; wire lsu_axi_awready; wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_awid; @@ -419,7 +560,7 @@ module tb_top wire lmem_axi_arready; wire lmem_axi_rvalid; - wire [RV_MUX_BUS_TAG-1:0] lmem_axi_rid; + wire [4-1:0] lmem_axi_rid; wire [1:0] lmem_axi_rresp; wire [63:0] lmem_axi_rdata; wire lmem_axi_rlast; @@ -433,12 +574,12 @@ module tb_top wire [1:0] lmem_axi_bresp; wire lmem_axi_bvalid; - wire [RV_MUX_BUS_TAG-1:0] lmem_axi_bid; + wire [4-1:0] lmem_axi_bid; wire lmem_axi_bready; wire mux_axi_awvalid; wire mux_axi_awready; - wire [RV_MUX_BUS_TAG-1:0] mux_axi_awid; + wire [4-1:0] mux_axi_awid; wire [31:0] mux_axi_awaddr; wire [3:0] mux_axi_awregion; wire [7:0] mux_axi_awlen; @@ -458,12 +599,12 @@ module tb_top wire mux_axi_bvalid; wire mux_axi_bready; wire [1:0] mux_axi_bresp; - wire [RV_MUX_BUS_TAG-1:0] mux_axi_bid; + wire [4-1:0] mux_axi_bid; // AXI Read Channels wire mux_axi_arvalid; wire mux_axi_arready; - wire [RV_MUX_BUS_TAG-1:0] mux_axi_arid; + wire [4-1:0] mux_axi_arid; wire [31:0] mux_axi_araddr; wire [3:0] mux_axi_arregion; wire [7:0] mux_axi_arlen; @@ -476,7 +617,7 @@ module tb_top wire mux_axi_rvalid; wire mux_axi_rready; - wire [RV_MUX_BUS_TAG-1:0] mux_axi_rid; + wire [4-1:0] mux_axi_rid; wire [63:0] mux_axi_rdata; wire [1:0] mux_axi_rresp; wire mux_axi_rlast; @@ -490,7 +631,7 @@ module tb_top axi_crossbar_wrap_2x1 #( .ADDR_WIDTH (32), .DATA_WIDTH (64), - .S_ID_WIDTH(RV_MUX_BUS_TAG - 1), + .S_ID_WIDTH4 - 1), .M00_ADDR_WIDTH(32) ) u_axi_crossbar ( .clk(core_clk), @@ -1340,24 +1481,287 @@ ahb_sif imem ( ahb_sif lmem ( // Inputs - .HWDATA(mux_hwdata), + .HWDATA(mux_hwdata_from_bridge), .HCLK(core_clk), - .HSEL(mux_hsel), - .HPROT(mux_hprot), - .HWRITE(mux_hwrite), - .HTRANS(mux_htrans), - .HSIZE(mux_hsize), - .HREADY(mux_hready), + .HSEL(mux_hsel_from_bridge), + .HPROT(mux_hprot_from_bridge), + .HWRITE(mux_hwrite_from_bridge), + .HTRANS(mux_htrans_from_bridge), + .HSIZE(mux_hsize_from_bridge), + .HREADY(mux_hready_from_bridge), .HRESETn(rst_l), - .HADDR(mux_haddr), - .HBURST(mux_hburst), + .HADDR(mux_haddr_from_bridge), + .HBURST(mux_hburst_from_bridge), // Outputs - .HREADYOUT(mux_hreadyout), - .HRESP(mux_hresp), - .HRDATA(mux_hrdata[63:0]) + .HREADYOUT(mux_hreadyout_from_bridge), + .HRESP(mux_hresp_from_bridge), + .HRDATA(mux_hrdata_from_bridge[63:0]) +); + + +axi_lsu_dma_bridge # (4,4) bridge( + .clk(core_clk), + .reset_l(rst_l), + + // master read bus + .m_arvalid(bridge_m_axi_arvalid), + .m_arid(bridge_m_axi_arid), + .m_araddr(bridge_m_axi_araddr), + .m_arready(bridge_m_axi_arready), + + .m_rvalid(bridge_m_axi_rvalid), + .m_rready(bridge_m_axi_rready), + .m_rdata(bridge_m_axi_rdata), + .m_rid(bridge_m_axi_rid), + .m_rresp(bridge_m_axi_rresp), + .m_rlast(bridge_m_axi_rlast), + + // master write bus + .m_awvalid(bridge_m_axi_awvalid), + .m_awid(bridge_m_axi_awid), + .m_awaddr(bridge_m_axi_awaddr), + .m_awready(bridge_m_axi_awready), + + .m_wvalid(bridge_m_axi_wvalid), + .m_wready(bridge_m_axi_wready), + + .m_bresp(bridge_m_axi_bresp), + .m_bvalid(bridge_m_axi_bvalid), + .m_bid(bridge_m_axi_bid), + .m_bready(bridge_m_axi_bready), + + // lmem + .s0_arvalid(bridge_s0_arvalid), + .s0_arready(bridge_s0_arready), + + .s0_rvalid(bridge_s0_rvalid), + .s0_rid(bridge_s0_rid), + .s0_rresp(bridge_s0_rresp), + .s0_rdata(bridge_s0_rdata), + .s0_rlast(bridge_s0_rlast), + .s0_rready(bridge_s0_rready), + + .s0_awvalid(bridge_s0_awvalid), + .s0_awready(bridge_s0_awready), + + .s0_wvalid(bridge_s0_wvalid), + .s0_wready(bridge_s0_wready), + + .s0_bresp(bridge_s0_bresp), + .s0_bvalid(bridge_s0_bvalid), + .s0_bid(bridge_s0_bid), + .s0_bready(bridge_s0_bready), + + .s1_arvalid(bridge_s1_dma_axi_arvalid), + .s1_arready(bridge_s1_dma_axi_arready), + + .s1_rvalid(bridge_s1_dma_axi_rvalid), + .s1_rresp(bridge_s1_dma_axi_rresp), + .s1_rdata(bridge_s1_dma_axi_rdata), + .s1_rlast(bridge_s1_dma_axi_rlast), + .s1_rready(bridge_s1_dma_axi_rready), + + .s1_awvalid(bridge_s1_dma_axi_awvalid), + .s1_awready(bridge_s1_dma_axi_awready), + + .s1_wvalid(bridge_s1_dma_axi_wvalid), + .s1_wready(bridge_s1_dma_axi_wready), + + .s1_bresp(bridge_s1_dma_axi_bresp), + .s1_bvalid(bridge_s1_dma_axi_bvalid), + .s1_bready(bridge_s1_dma_axi_bready) +); + + +ahb_to_axi4 #(.pt(pt)) dma_to_bridge_ahb_to_axi4 ( + .clk(core_clk), + .rst_l(rst_l), + .scan_mode('0), + .clk_override('0), + .bus_clk_en(1'b1), + + // AXI Write Channels + .axi_awvalid(bridge_s1_dma_axi_awvalid), + .axi_awready(bridge_s1_dma_axi_awready), + .axi_awid(bridge_s1_dma_axi_awid[pt.DMA_BUS_TAG-1:0]), + .axi_awaddr(bridge_s1_dma_axi_awaddr[31:0]), + .axi_awsize(bridge_s1_dma_axi_awsize[2:0]), + .axi_awprot(bridge_s1_dma_axi_awprot[2:0]), + .axi_awlen(bridge_s1_dma_axi_awlen[7:0]), + .axi_awburst(bridge_s1_dma_axi_awburst[1:0]), + + .axi_wvalid(bridge_s1_dma_axi_wvalid), + .axi_wready(bridge_s1_dma_axi_wready), + .axi_wdata(bridge_s1_dma_axi_wdata[63:0]), + .axi_wstrb(bridge_s1_dma_axi_wstrb[7:0]), + .axi_wlast(bridge_s1_dma_axi_wlast), + + .axi_bvalid(bridge_s1_dma_axi_bvalid), + .axi_bready(bridge_s1_dma_axi_bready), + .axi_bresp(bridge_s1_dma_axi_bresp[1:0]), + .axi_bid(bridge_s1_dma_axi_bid[pt.DMA_BUS_TAG-1:0]), + + // AXI Read Channels + .axi_arvalid(bridge_s1_dma_axi_arvalid), + .axi_arready(bridge_s1_dma_axi_arready), + .axi_arid(bridge_s1_dma_axi_arid[pt.DMA_BUS_TAG-1:0]), + .axi_araddr(bridge_s1_dma_axi_araddr[31:0]), + .axi_arsize(bridge_s1_dma_axi_arsize[2:0]), + .axi_arprot(bridge_s1_dma_axi_arprot[2:0]), + .axi_arlen(bridge_s1_dma_axi_arlen[7:0]), + .axi_arburst(bridge_s1_dma_axi_arburst[1:0]), + + .axi_rvalid(bridge_s1_dma_axi_rvalid), + .axi_rready(bridge_s1_dma_axi_rready), + .axi_rid(bridge_s1_dma_axi_rid[pt.DMA_BUS_TAG-1:0]), + .axi_rdata(bridge_s1_dma_axi_rdata[63:0]), + .axi_rresp(bridge_s1_dma_axi_rresp[1:0]), + + // AHB signals + .ahb_haddr(dma_haddr), + .ahb_hburst(dma_hburst), + .ahb_hmastlock(dma_hmastlock), + .ahb_hprot(dma_hprot), + .ahb_hsize(dma_hsize), + .ahb_htrans(dma_htrans), + .ahb_hwrite(dma_hwrite), + .ahb_hwdata(dma_hwdata), + + .ahb_hrdata(dma_hrdata), + .ahb_hreadyout(dma_hreadyout), + .ahb_hresp(dma_hresp), + .ahb_hreadyin(dma_hreadyin), + .ahb_hsel(dma_hsel), + .* +); + +ahb_to_axi4 #(.pt(pt)) lmem_to_bridge_ahb_to_axi4 ( + .clk(core_clk), + .clk_override('0), + .rst_l(rst_l), + .scan_mode('0), + .bus_clk_en(1'b1), + + // AXI Write Channels + .axi_awvalid(bridge_s0_awvalid), + .axi_awready(bridge_s0_awready), + .axi_awid(bridge_s0_awid[pt.DMA_BUS_TAG-1:0]), + .axi_awaddr(bridge_s0_awaddr[31:0]), + .axi_awsize(bridge_s0_awsize[2:0]), + .axi_awprot(bridge_s0_awprot[2:0]), + .axi_awlen(bridge_s0_awlen[7:0]), + .axi_awburst(bridge_s0_awburst[1:0]), + + .axi_wvalid(bridge_s0_wvalid), + .axi_wready(bridge_s0_wready), + .axi_wdata(bridge_s0_wdata[63:0]), + .axi_wstrb(bridge_s0_wstrb[7:0]), + .axi_wlast(bridge_s0_wlast), + + .axi_bvalid(bridge_s0_bvalid), + .axi_bready(bridge_s0_bready), + .axi_bresp(bridge_s0_bresp[1:0]), + .axi_bid(bridge_s0_bid[pt.DMA_BUS_TAG-1:0]), + + // AXI Read Channels + .axi_arvalid(bridge_s0_arvalid), + .axi_arready(bridge_s0_arready), + .axi_arid(bridge_s0_arid[pt.DMA_BUS_TAG-1:0]), + .axi_araddr(bridge_s0_araddr[31:0]), + .axi_arsize(bridge_s0_arsize[2:0]), + .axi_arprot(bridge_s0_arprot[2:0]), + .axi_arlen(bridge_s0_arlen[7:0]), + .axi_arburst(bridge_s0_arburst[1:0]), + + .axi_rvalid(bridge_s0_rvalid), + .axi_rready(bridge_s0_rready), + .axi_rid(bridge_s0_rid[pt.DMA_BUS_TAG-1:0]), + .axi_rdata(bridge_s0_rdata[63:0]), + .axi_rresp(bridge_s0_rresp[1:0]), + + // AHB signals + .ahb_haddr(mux_haddr_from_bridge), + .ahb_hburst(mux_hburst_from_bridge), + .ahb_hmastlock(lsu_hmastlock_from_bridge), + .ahb_hprot(mux_hprot_from_bridge), + .ahb_hsize(mux_hsize_from_bridge), + .ahb_htrans(mux_htrans_from_bridge), + .ahb_hwrite(mux_hwrite_from_bridge), + .ahb_hwdata(mux_hwdata_from_bridge), + + .ahb_hrdata(mux_hrdata_from_bridge), + .ahb_hreadyout(mux_hreadyout_from_bridge), + .ahb_hresp(mux_hresp_from_bridge), + .ahb_hreadyin(mux_hready_from_bridge), + .ahb_hsel(mux_hsel_from_bridge), + .* +); + + +axi4_to_ahb #(.pt(pt)) axi_to_ahb_bridge_m ( + .clk(core_clk), + .clk_override('0), + .scan_mode('0), + .rst_l(rst_l), + .free_clk('0), + .bus_clk_en(1'b1), + .dec_tlu_force_halt('0), + + // AXI Write Channels + .axi_awvalid(bridge_m_axi_awvalid), + .axi_awready(bridge_m_axi_awready), + .axi_awid(bridge_m_axi_awid[pt.LSU_BUS_TAG-1:0]), + .axi_awaddr(bridge_m_axi_awaddr[31:0]), + .axi_awsize(bridge_m_axi_awsize[2:0]), + .axi_awprot(bridge_m_axi_awprot[2:0]), + + .axi_wvalid(bridge_m_axi_wvalid), + .axi_wready(bridge_m_axi_wready), + .axi_wdata(bridge_m_axi_wdata[63:0]), + .axi_wstrb(bridge_m_axi_wstrb[7:0]), + .axi_wlast(bridge_m_axi_wlast), + + .axi_bvalid(bridge_m_axi_bvalid), + .axi_bready(bridge_m_axi_bready), + .axi_bresp(bridge_m_axi_bresp[1:0]), + .axi_bid(bridge_m_axi_bid[pt.LSU_BUS_TAG-1:0]), + + // AXI Read Channels + .axi_arvalid(bridge_m_axi_arvalid), + .axi_arready(bridge_m_axi_arready), + .axi_arid(bridge_m_axi_arid[pt.LSU_BUS_TAG-1:0]), + .axi_araddr(bridge_m_axi_araddr[31:0]), + .axi_arsize(bridge_m_axi_arsize[2:0]), + .axi_arprot(bridge_m_axi_arprot[2:0]), + + .axi_rvalid(bridge_m_axi_rvalid), + .axi_rready(bridge_m_axi_rready), + .axi_rid(bridge_m_axi_rid[pt.LSU_BUS_TAG-1:0]), + .axi_rdata(bridge_m_axi_rdata[63:0]), + .axi_rresp(bridge_m_axi_rresp[1:0]), + .axi_rlast(bridge_m_axi_rlast), + + // AHB-LITE signals + // lsu here + .ahb_haddr(lsu_haddr[31:0]), + .ahb_hburst(lsu_hburst), + .ahb_hmastlock(lsu_hmastlock), + .ahb_hprot(lsu_hprot[3:0]), + .ahb_hsize(lsu_hsize[2:0]), + .ahb_htrans(lsu_htrans[1:0]), + .ahb_hwrite(lsu_hwrite), + .ahb_hwdata(lsu_hwdata[63:0]), + + .ahb_hrdata(lsu_hrdata[63:0]), + .ahb_hready(lsu_hready), + .ahb_hresp(lsu_hresp), + + .* + ); + `endif `ifdef RV_BUILD_AXI4 axi_slv #(.TAGW(`RV_IFU_BUS_TAG)) imem( @@ -1397,7 +1801,7 @@ axi_slv #(.TAGW(`RV_IFU_BUS_TAG)) imem( .bid() ); -defparam lmem.TAGW = RV_MUX_BUS_TAG; +defparam lmem.TAGW =4; //axi_slv #(.TAGW(`RV_LSU_BUS_TAG)) lmem( axi_slv lmem( @@ -1437,7 +1841,7 @@ axi_slv lmem( .bid(lmem_axi_bid) ); -axi_lsu_dma_bridge # (RV_MUX_BUS_TAG, RV_MUX_BUS_TAG) bridge( +axi_lsu_dma_bridge # 4,4) bridge( .clk(core_clk), .reset_l(rst_l), @@ -1487,7 +1891,6 @@ axi_lsu_dma_bridge # (RV_MUX_BUS_TAG, RV_MUX_BUS_TAG) bridge( .s0_bid(lmem_axi_bid), .s0_bready(lmem_axi_bready), - .s1_arvalid(dma_axi_arvalid), .s1_arready(dma_axi_arready), From 0b1225472b6a3eb31129141bbea4864a434bbdf2 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Thu, 21 Nov 2024 18:04:26 +0100 Subject: [PATCH 02/11] don't use RV_DMA_BUS_TAG --- testbench/tb_top.sv | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index 411d53a05fa..d1c85655c75 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -97,7 +97,7 @@ module tb_top wire bridge_s0_awvalid; wire bridge_s0_awready; - wire [`RV_DMA_BUS_TAG-1:0] bridge_s0_awid; + wire [4-1:0] bridge_s0_awid; wire [31:0] bridge_s0_awaddr; wire [2:0] bridge_s0_awsize; wire [2:0] bridge_s0_awprot; @@ -111,10 +111,10 @@ module tb_top wire bridge_s0_bvalid; wire bridge_s0_bready; wire [1:0] bridge_s0_bresp; - wire [`RV_DMA_BUS_TAG-1:0] bridge_s0_bid; + wire [4-1:0] bridge_s0_bid; wire bridge_s0_arvalid; wire bridge_s0_arready; - wire [`RV_DMA_BUS_TAG-1:0] bridge_s0_arid; + wire [4-1:0] bridge_s0_arid; wire [31:0] bridge_s0_araddr; wire [2:0] bridge_s0_arsize; wire [2:0] bridge_s0_arprot; @@ -122,7 +122,7 @@ module tb_top wire [1:0] bridge_s0_arburst; wire bridge_s0_rvalid; wire bridge_s0_rready; - wire [`RV_DMA_BUS_TAG-1:0] bridge_s0_rid; + wire [4-1:0] bridge_s0_rid; wire [63:0] bridge_s0_rdata; wire [1:0] bridge_s0_rresp; wire bridge_s0_rlast; @@ -130,7 +130,7 @@ module tb_top wire bridge_s1_dma_axi_awvalid; wire bridge_s1_dma_axi_awready; - wire [`RV_DMA_BUS_TAG-1:0] bridge_s1_dma_axi_awid; + wire [4-1:0] bridge_s1_dma_axi_awid; wire [31:0] bridge_s1_dma_axi_awaddr; wire [2:0] bridge_s1_dma_axi_awsize; wire [2:0] bridge_s1_dma_axi_awprot; @@ -144,10 +144,10 @@ module tb_top wire bridge_s1_dma_axi_bvalid; wire bridge_s1_dma_axi_bready; wire [1:0] bridge_s1_dma_axi_bresp; - wire [`RV_DMA_BUS_TAG-1:0] bridge_s1_dma_axi_bid; + wire [4-1:0] bridge_s1_dma_axi_bid; wire bridge_s1_dma_axi_arvalid; wire bridge_s1_dma_axi_arready; - wire [`RV_DMA_BUS_TAG-1:0] bridge_s1_dma_axi_arid; + wire [4-1:0] bridge_s1_dma_axi_arid; wire [31:0] bridge_s1_dma_axi_araddr; wire [2:0] bridge_s1_dma_axi_arsize; wire [2:0] bridge_s1_dma_axi_arprot; @@ -155,7 +155,7 @@ module tb_top wire [1:0] bridge_s1_dma_axi_arburst; wire bridge_s1_dma_axi_rvalid; wire bridge_s1_dma_axi_rready; - wire [`RV_DMA_BUS_TAG-1:0] bridge_s1_dma_axi_rid; + wire [4-1:0] bridge_s1_dma_axi_rid; wire [63:0] bridge_s1_dma_axi_rdata; wire [1:0] bridge_s1_dma_axi_rresp; wire bridge_s1_dma_axi_rlast; From 2dbe0dae8ee55c2b1600a98e78d3445e47ac0d6a Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Fri, 22 Nov 2024 12:18:48 +0100 Subject: [PATCH 03/11] fix axi4<->ahb connections --- testbench/tb_top.sv | 90 +++++++++++++++++++++------------------------ 1 file changed, 42 insertions(+), 48 deletions(-) diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index d1c85655c75..6db0ab767ac 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -44,6 +44,7 @@ module tb_top ); `endif +`ifdef RV_BUILD_AHB_LITE wire bridge_m_axi_awvalid; wire bridge_m_axi_awready; wire [4-1:0] bridge_m_axi_awid; @@ -169,7 +170,7 @@ module tb_top logic dma_hwrite ; logic dma_hreadyout ; logic dma_hreadyin ; - logic dma_hsel ; +`endif // RV_BUILD_AHB_LITE `ifndef VERILATOR bit core_clk; @@ -212,6 +213,9 @@ module tb_top logic [63:0] lsu_hwdata ; logic lsu_hready ; logic lsu_hresp ; + logic lsu_hsel ; + logic lsu_hreadyin ; + logic lsu_hreadyout ; logic [31:0] mux_haddr ; logic [2:0] mux_hburst ; @@ -1171,14 +1175,14 @@ veer_wrapper rvtop_wrapper ( //--------------------------------------------------------------- // DMA Slave //--------------------------------------------------------------- - .dma_haddr ( '0 ), - .dma_hburst ( '0 ), - .dma_hmastlock ( '0 ), - .dma_hprot ( '0 ), - .dma_hsize ( '0 ), - .dma_htrans ( '0 ), - .dma_hwrite ( '0 ), - .dma_hwdata ( '0 ), + .dma_haddr (dma_haddr), + .dma_hburst (dma_hburst), + .dma_hmastlock (dma_hmastlock), + .dma_hprot (dma_hprot), + .dma_hsize (dma_hsize), + .dma_htrans (dma_htrans), + .dma_hwrite (dma_hwrite), + .dma_hwdata (dma_hwdata), .dma_hrdata ( dma_hrdata ), .dma_hresp ( dma_hresp ), @@ -1498,7 +1502,7 @@ ahb_sif lmem ( .HRESP(mux_hresp_from_bridge), .HRDATA(mux_hrdata_from_bridge[63:0]) ); - + axi_lsu_dma_bridge # (4,4) bridge( .clk(core_clk), @@ -1574,12 +1578,14 @@ axi_lsu_dma_bridge # (4,4) bridge( ); -ahb_to_axi4 #(.pt(pt)) dma_to_bridge_ahb_to_axi4 ( +axi4_to_ahb #(.pt(pt)) dma_to_bridge_axi4_to_ahb ( .clk(core_clk), + .free_clk('0), .rst_l(rst_l), .scan_mode('0), + .bus_clk_en('1), .clk_override('0), - .bus_clk_en(1'b1), + .dec_tlu_force_halt('0), // AXI Write Channels .axi_awvalid(bridge_s1_dma_axi_awvalid), @@ -1588,8 +1594,6 @@ ahb_to_axi4 #(.pt(pt)) dma_to_bridge_ahb_to_axi4 ( .axi_awaddr(bridge_s1_dma_axi_awaddr[31:0]), .axi_awsize(bridge_s1_dma_axi_awsize[2:0]), .axi_awprot(bridge_s1_dma_axi_awprot[2:0]), - .axi_awlen(bridge_s1_dma_axi_awlen[7:0]), - .axi_awburst(bridge_s1_dma_axi_awburst[1:0]), .axi_wvalid(bridge_s1_dma_axi_wvalid), .axi_wready(bridge_s1_dma_axi_wready), @@ -1609,14 +1613,13 @@ ahb_to_axi4 #(.pt(pt)) dma_to_bridge_ahb_to_axi4 ( .axi_araddr(bridge_s1_dma_axi_araddr[31:0]), .axi_arsize(bridge_s1_dma_axi_arsize[2:0]), .axi_arprot(bridge_s1_dma_axi_arprot[2:0]), - .axi_arlen(bridge_s1_dma_axi_arlen[7:0]), - .axi_arburst(bridge_s1_dma_axi_arburst[1:0]), .axi_rvalid(bridge_s1_dma_axi_rvalid), .axi_rready(bridge_s1_dma_axi_rready), .axi_rid(bridge_s1_dma_axi_rid[pt.DMA_BUS_TAG-1:0]), .axi_rdata(bridge_s1_dma_axi_rdata[63:0]), .axi_rresp(bridge_s1_dma_axi_rresp[1:0]), + .axi_rlast(bridge_s1_dma_axi_rlast), // AHB signals .ahb_haddr(dma_haddr), @@ -1629,19 +1632,18 @@ ahb_to_axi4 #(.pt(pt)) dma_to_bridge_ahb_to_axi4 ( .ahb_hwdata(dma_hwdata), .ahb_hrdata(dma_hrdata), - .ahb_hreadyout(dma_hreadyout), - .ahb_hresp(dma_hresp), - .ahb_hreadyin(dma_hreadyin), - .ahb_hsel(dma_hsel), - .* + .ahb_hready(dma_hready), + .ahb_hresp(dma_hresp) ); -ahb_to_axi4 #(.pt(pt)) lmem_to_bridge_ahb_to_axi4 ( +axi4_to_ahb #(.pt(pt)) lmem_to_bridge_axi4_to_ahb ( .clk(core_clk), - .clk_override('0), + .free_clk('0), .rst_l(rst_l), .scan_mode('0), - .bus_clk_en(1'b1), + .bus_clk_en('1), + .clk_override('0), + .dec_tlu_force_halt('0), // AXI Write Channels .axi_awvalid(bridge_s0_awvalid), @@ -1650,8 +1652,6 @@ ahb_to_axi4 #(.pt(pt)) lmem_to_bridge_ahb_to_axi4 ( .axi_awaddr(bridge_s0_awaddr[31:0]), .axi_awsize(bridge_s0_awsize[2:0]), .axi_awprot(bridge_s0_awprot[2:0]), - .axi_awlen(bridge_s0_awlen[7:0]), - .axi_awburst(bridge_s0_awburst[1:0]), .axi_wvalid(bridge_s0_wvalid), .axi_wready(bridge_s0_wready), @@ -1671,14 +1671,13 @@ ahb_to_axi4 #(.pt(pt)) lmem_to_bridge_ahb_to_axi4 ( .axi_araddr(bridge_s0_araddr[31:0]), .axi_arsize(bridge_s0_arsize[2:0]), .axi_arprot(bridge_s0_arprot[2:0]), - .axi_arlen(bridge_s0_arlen[7:0]), - .axi_arburst(bridge_s0_arburst[1:0]), .axi_rvalid(bridge_s0_rvalid), .axi_rready(bridge_s0_rready), .axi_rid(bridge_s0_rid[pt.DMA_BUS_TAG-1:0]), .axi_rdata(bridge_s0_rdata[63:0]), .axi_rresp(bridge_s0_rresp[1:0]), + .axi_rlast(bridge_s0_rlast), // AHB signals .ahb_haddr(mux_haddr_from_bridge), @@ -1691,22 +1690,17 @@ ahb_to_axi4 #(.pt(pt)) lmem_to_bridge_ahb_to_axi4 ( .ahb_hwdata(mux_hwdata_from_bridge), .ahb_hrdata(mux_hrdata_from_bridge), - .ahb_hreadyout(mux_hreadyout_from_bridge), - .ahb_hresp(mux_hresp_from_bridge), - .ahb_hreadyin(mux_hready_from_bridge), - .ahb_hsel(mux_hsel_from_bridge), - .* + .ahb_hready(mux_hready_from_bridge), + .ahb_hresp(mux_hresp_from_bridge) ); -axi4_to_ahb #(.pt(pt)) axi_to_ahb_bridge_m ( +ahb_to_axi4 #(.pt(pt)) bridge_m_ahb_to_axi ( .clk(core_clk), - .clk_override('0), - .scan_mode('0), .rst_l(rst_l), - .free_clk('0), + .scan_mode('0), .bus_clk_en(1'b1), - .dec_tlu_force_halt('0), + .clk_override('0), // AXI Write Channels .axi_awvalid(bridge_m_axi_awvalid), @@ -1715,6 +1709,8 @@ axi4_to_ahb #(.pt(pt)) axi_to_ahb_bridge_m ( .axi_awaddr(bridge_m_axi_awaddr[31:0]), .axi_awsize(bridge_m_axi_awsize[2:0]), .axi_awprot(bridge_m_axi_awprot[2:0]), + .axi_awlen(bridge_m_axi_awlen), + .axi_awburst(bridge_m_axi_awburst), .axi_wvalid(bridge_m_axi_wvalid), .axi_wready(bridge_m_axi_wready), @@ -1734,16 +1730,16 @@ axi4_to_ahb #(.pt(pt)) axi_to_ahb_bridge_m ( .axi_araddr(bridge_m_axi_araddr[31:0]), .axi_arsize(bridge_m_axi_arsize[2:0]), .axi_arprot(bridge_m_axi_arprot[2:0]), + .axi_arlen(bridge_m_axi_arlen), + .axi_arburst(bridge_m_axi_arburst), .axi_rvalid(bridge_m_axi_rvalid), .axi_rready(bridge_m_axi_rready), .axi_rid(bridge_m_axi_rid[pt.LSU_BUS_TAG-1:0]), .axi_rdata(bridge_m_axi_rdata[63:0]), .axi_rresp(bridge_m_axi_rresp[1:0]), - .axi_rlast(bridge_m_axi_rlast), // AHB-LITE signals - // lsu here .ahb_haddr(lsu_haddr[31:0]), .ahb_hburst(lsu_hburst), .ahb_hmastlock(lsu_hmastlock), @@ -1752,17 +1748,15 @@ axi4_to_ahb #(.pt(pt)) axi_to_ahb_bridge_m ( .ahb_htrans(lsu_htrans[1:0]), .ahb_hwrite(lsu_hwrite), .ahb_hwdata(lsu_hwdata[63:0]), - - .ahb_hrdata(lsu_hrdata[63:0]), - .ahb_hready(lsu_hready), - .ahb_hresp(lsu_hresp), - - .* - + .ahb_hsel(lsu_hsel), + .ahb_hreadyin(lsu_hreadyin), + .ahb_hrdata(mux_hrdata[63:0]), + .ahb_hreadyout(lsu_hreadyout), + .ahb_hresp(mux_hresp) ); -`endif +`endif // RV_BUILD_AHB_LITE `ifdef RV_BUILD_AXI4 axi_slv #(.TAGW(`RV_IFU_BUS_TAG)) imem( .aclk(core_clk), From 59a55c8b7a5674d1b01400f2207a8329dff8b8c0 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Fri, 22 Nov 2024 12:29:24 +0100 Subject: [PATCH 04/11] cleanup --- testbench/tb_top.sv | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index 6db0ab767ac..18ddbe4861a 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -371,6 +371,7 @@ module tb_top `ifdef RV_BUILD_AXI4 //-------------------------- LSU AXI signals-------------------------- // AXI Write Channels + parameter int RV_MUX_BUS_TAG = (`RV_LSU_BUS_TAG > `RV_SB_BUS_TAG ? `RV_LSU_BUS_TAG : `RV_SB_BUS_TAG) + 1; wire lsu_axi_awvalid; wire lsu_axi_awready; wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_awid; @@ -564,7 +565,7 @@ module tb_top wire lmem_axi_arready; wire lmem_axi_rvalid; - wire [4-1:0] lmem_axi_rid; + wire [RV_MUX_BUS_TAG-1:0] lmem_axi_rid; wire [1:0] lmem_axi_rresp; wire [63:0] lmem_axi_rdata; wire lmem_axi_rlast; @@ -578,12 +579,12 @@ module tb_top wire [1:0] lmem_axi_bresp; wire lmem_axi_bvalid; - wire [4-1:0] lmem_axi_bid; + wire [RV_MUX_BUS_TAG-1:0] lmem_axi_bid; wire lmem_axi_bready; wire mux_axi_awvalid; wire mux_axi_awready; - wire [4-1:0] mux_axi_awid; + wire [RV_MUX_BUS_TAG-1:0] mux_axi_awid; wire [31:0] mux_axi_awaddr; wire [3:0] mux_axi_awregion; wire [7:0] mux_axi_awlen; @@ -603,12 +604,12 @@ module tb_top wire mux_axi_bvalid; wire mux_axi_bready; wire [1:0] mux_axi_bresp; - wire [4-1:0] mux_axi_bid; + wire [RV_MUX_BUS_TAG-1:0] mux_axi_bid; // AXI Read Channels wire mux_axi_arvalid; wire mux_axi_arready; - wire [4-1:0] mux_axi_arid; + wire [RV_MUX_BUS_TAG-1:0] mux_axi_arid; wire [31:0] mux_axi_araddr; wire [3:0] mux_axi_arregion; wire [7:0] mux_axi_arlen; @@ -621,7 +622,7 @@ module tb_top wire mux_axi_rvalid; wire mux_axi_rready; - wire [4-1:0] mux_axi_rid; + wire [RV_MUX_BUS_TAG-1:0] mux_axi_rid; wire [63:0] mux_axi_rdata; wire [1:0] mux_axi_rresp; wire mux_axi_rlast; @@ -635,7 +636,7 @@ module tb_top axi_crossbar_wrap_2x1 #( .ADDR_WIDTH (32), .DATA_WIDTH (64), - .S_ID_WIDTH4 - 1), + .S_ID_WIDTH(RV_MUX_BUS_TAG - 1), .M00_ADDR_WIDTH(32) ) u_axi_crossbar ( .clk(core_clk), @@ -1740,6 +1741,7 @@ ahb_to_axi4 #(.pt(pt)) bridge_m_ahb_to_axi ( .axi_rresp(bridge_m_axi_rresp[1:0]), // AHB-LITE signals + // connect lsu master here .ahb_haddr(lsu_haddr[31:0]), .ahb_hburst(lsu_hburst), .ahb_hmastlock(lsu_hmastlock), @@ -1795,7 +1797,7 @@ axi_slv #(.TAGW(`RV_IFU_BUS_TAG)) imem( .bid() ); -defparam lmem.TAGW =4; +defparam lmem.TAGW = RV_MUX_BUS_TAG; //axi_slv #(.TAGW(`RV_LSU_BUS_TAG)) lmem( axi_slv lmem( @@ -1835,7 +1837,7 @@ axi_slv lmem( .bid(lmem_axi_bid) ); -axi_lsu_dma_bridge # 4,4) bridge( +axi_lsu_dma_bridge # (RV_MUX_BUS_TAG, RV_MUX_BUS_TAG) bridge( .clk(core_clk), .reset_l(rst_l), @@ -1885,6 +1887,7 @@ axi_lsu_dma_bridge # 4,4) bridge( .s0_bid(lmem_axi_bid), .s0_bready(lmem_axi_bready), + .s1_arvalid(dma_axi_arvalid), .s1_arready(dma_axi_arready), From 9550b62da1cd3d0ee06923b1a737a603c22a0130 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Fri, 22 Nov 2024 13:02:44 +0100 Subject: [PATCH 05/11] ecc test passes --- testbench/tb_top.sv | 70 +++++++++++++++++++++++++-------------------- 1 file changed, 39 insertions(+), 31 deletions(-) diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index 18ddbe4861a..b4ed5ba0590 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -170,6 +170,23 @@ module tb_top logic dma_hwrite ; logic dma_hreadyout ; logic dma_hreadyin ; + + logic [31:0] mux_haddr_from_bridge ; + logic [2:0] mux_hburst_from_bridge ; + logic mux_hmastlock_from_bridge ; + logic [3:0] mux_hprot_from_bridge ; + logic [2:0] mux_hsize_from_bridge ; + logic [1:0] mux_htrans_from_bridge ; + logic mux_hwrite_from_bridge ; + logic mux_hsel_from_bridge ; + logic [63:0] mux_hrdata_from_bridge ; + logic [63:0] mux_hwdata_from_bridge ; + logic mux_hready_from_bridge ; + logic mux_hresp_from_bridge ; + logic mux_hreadyout_from_bridge ; + logic lsu_hmastlock_from_bridge ; + + `endif // RV_BUILD_AHB_LITE `ifndef VERILATOR @@ -213,9 +230,6 @@ module tb_top logic [63:0] lsu_hwdata ; logic lsu_hready ; logic lsu_hresp ; - logic lsu_hsel ; - logic lsu_hreadyin ; - logic lsu_hreadyout ; logic [31:0] mux_haddr ; logic [2:0] mux_hburst ; @@ -231,21 +245,6 @@ module tb_top logic mux_hresp ; logic mux_hreadyout ; - logic [31:0] mux_haddr_from_bridge ; - logic [2:0] mux_hburst_from_bridge ; - logic mux_hmastlock_from_bridge ; - logic [3:0] mux_hprot_from_bridge ; - logic [2:0] mux_hsize_from_bridge ; - logic [1:0] mux_htrans_from_bridge ; - logic mux_hwrite_from_bridge ; - logic mux_hsel_from_bridge ; - logic [63:0] mux_hrdata_from_bridge ; - logic [63:0] mux_hwdata_from_bridge ; - logic mux_hready_from_bridge ; - logic mux_hresp_from_bridge ; - logic mux_hreadyout_from_bridge ; - logic lsu_hmastlock_from_bridge ; - logic [31:0] sb_haddr ; logic [2:0] sb_hburst ; logic sb_hmastlock ; @@ -1176,14 +1175,23 @@ veer_wrapper rvtop_wrapper ( //--------------------------------------------------------------- // DMA Slave //--------------------------------------------------------------- - .dma_haddr (dma_haddr), - .dma_hburst (dma_hburst), - .dma_hmastlock (dma_hmastlock), - .dma_hprot (dma_hprot), - .dma_hsize (dma_hsize), - .dma_htrans (dma_htrans), - .dma_hwrite (dma_hwrite), - .dma_hwdata (dma_hwdata), + // .dma_haddr (dma_haddr), + // .dma_hburst (dma_hburst), + // .dma_hmastlock (dma_hmastlock), + // .dma_hprot (dma_hprot), + // .dma_hsize (dma_hsize), + // .dma_htrans (dma_htrans), + // .dma_hwrite (dma_hwrite), + // .dma_hwdata (dma_hwdata), + + .dma_haddr ('0), + .dma_hburst ('0), + .dma_hmastlock ('0), + .dma_hprot ('0), + .dma_hsize ('0), + .dma_htrans ('0), + .dma_hwrite ('0), + .dma_hwdata ('0), .dma_hrdata ( dma_hrdata ), .dma_hresp ( dma_hresp ), @@ -1581,7 +1589,7 @@ axi_lsu_dma_bridge # (4,4) bridge( axi4_to_ahb #(.pt(pt)) dma_to_bridge_axi4_to_ahb ( .clk(core_clk), - .free_clk('0), + .free_clk(core_clk), .rst_l(rst_l), .scan_mode('0), .bus_clk_en('1), @@ -1639,7 +1647,7 @@ axi4_to_ahb #(.pt(pt)) dma_to_bridge_axi4_to_ahb ( axi4_to_ahb #(.pt(pt)) lmem_to_bridge_axi4_to_ahb ( .clk(core_clk), - .free_clk('0), + .free_clk(core_clk), .rst_l(rst_l), .scan_mode('0), .bus_clk_en('1), @@ -1750,10 +1758,10 @@ ahb_to_axi4 #(.pt(pt)) bridge_m_ahb_to_axi ( .ahb_htrans(lsu_htrans[1:0]), .ahb_hwrite(lsu_hwrite), .ahb_hwdata(lsu_hwdata[63:0]), - .ahb_hsel(lsu_hsel), - .ahb_hreadyin(lsu_hreadyin), + .ahb_hsel(mux_hsel), + .ahb_hreadyin(mux_hready), .ahb_hrdata(mux_hrdata[63:0]), - .ahb_hreadyout(lsu_hreadyout), + .ahb_hreadyout(mux_hreadyout), .ahb_hresp(mux_hresp) ); From e0d170f4f7a8a6b5b8d1bfc954d7c061b8c9def4 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Fri, 22 Nov 2024 13:03:45 +0100 Subject: [PATCH 06/11] add todo --- testbench/tb_top.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index b4ed5ba0590..841256c04cc 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -1175,6 +1175,7 @@ veer_wrapper rvtop_wrapper ( //--------------------------------------------------------------- // DMA Slave //--------------------------------------------------------------- + // TODO shouldn't these be connected? // .dma_haddr (dma_haddr), // .dma_hburst (dma_hburst), // .dma_hmastlock (dma_hmastlock), From b5c52f902b857e3251cdccbd2497f8143a2f3e95 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Fri, 22 Nov 2024 16:51:01 +0100 Subject: [PATCH 07/11] reconnect lmem and dma in tb --- testbench/tb_top.sv | 128 ++++++++++++++++++++++---------------------- 1 file changed, 63 insertions(+), 65 deletions(-) diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index 841256c04cc..fd6acdc3cc6 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -171,20 +171,18 @@ module tb_top logic dma_hreadyout ; logic dma_hreadyin ; - logic [31:0] mux_haddr_from_bridge ; - logic [2:0] mux_hburst_from_bridge ; - logic mux_hmastlock_from_bridge ; - logic [3:0] mux_hprot_from_bridge ; - logic [2:0] mux_hsize_from_bridge ; - logic [1:0] mux_htrans_from_bridge ; - logic mux_hwrite_from_bridge ; - logic mux_hsel_from_bridge ; - logic [63:0] mux_hrdata_from_bridge ; - logic [63:0] mux_hwdata_from_bridge ; - logic mux_hready_from_bridge ; - logic mux_hresp_from_bridge ; - logic mux_hreadyout_from_bridge ; - logic lsu_hmastlock_from_bridge ; + logic [31:0] lmem_haddr_from_bridge ; + logic [2:0] lmem_hburst_from_bridge ; + logic lmem_hmastlock_from_bridge ; + logic [3:0] lmem_hprot_from_bridge ; + logic [2:0] lmem_hsize_from_bridge ; + logic [1:0] lmem_htrans_from_bridge ; + logic lmem_hwrite_from_bridge ; + logic [63:0] lmem_hwdata_from_bridge ; + + logic lmem_hready_to_bridge ; + logic lmem_hresp_to_bridge ; + logic [63:0] lmem_hrdata_to_bridge ; `endif // RV_BUILD_AHB_LITE @@ -1175,31 +1173,30 @@ veer_wrapper rvtop_wrapper ( //--------------------------------------------------------------- // DMA Slave //--------------------------------------------------------------- - // TODO shouldn't these be connected? - // .dma_haddr (dma_haddr), - // .dma_hburst (dma_hburst), - // .dma_hmastlock (dma_hmastlock), - // .dma_hprot (dma_hprot), - // .dma_hsize (dma_hsize), - // .dma_htrans (dma_htrans), - // .dma_hwrite (dma_hwrite), - // .dma_hwdata (dma_hwdata), - - .dma_haddr ('0), - .dma_hburst ('0), - .dma_hmastlock ('0), - .dma_hprot ('0), - .dma_hsize ('0), - .dma_htrans ('0), - .dma_hwrite ('0), - .dma_hwdata ('0), + .dma_haddr (dma_haddr), + .dma_hburst (dma_hburst), + .dma_hmastlock (dma_hmastlock), + .dma_hprot (dma_hprot), + .dma_hsize (dma_hsize), + .dma_htrans (dma_htrans), + .dma_hwrite (dma_hwrite), + .dma_hwdata (dma_hwdata), + + // .dma_haddr ('0), + // .dma_hburst ('0), + // .dma_hmastlock ('0), + // .dma_hprot ('0), + // .dma_hsize ('0), + // .dma_htrans ('0), + // .dma_hwrite ('0), + // .dma_hwdata ('0), .dma_hrdata ( dma_hrdata ), .dma_hresp ( dma_hresp ), .dma_hsel ( 1'b1 ), .dma_hreadyin ( dma_hready_out ), .dma_hreadyout ( dma_hready_out ), -`endif +`endif // RV_BUILD_AHB_LITE `ifdef RV_BUILD_AXI4 //-------------------------- LSU AXI signals-------------------------- // AXI Write Channels @@ -1495,22 +1492,22 @@ ahb_sif imem ( ahb_sif lmem ( // Inputs - .HWDATA(mux_hwdata_from_bridge), + .HWDATA(lmem_hwdata_from_bridge), .HCLK(core_clk), - .HSEL(mux_hsel_from_bridge), - .HPROT(mux_hprot_from_bridge), - .HWRITE(mux_hwrite_from_bridge), - .HTRANS(mux_htrans_from_bridge), - .HSIZE(mux_hsize_from_bridge), - .HREADY(mux_hready_from_bridge), + .HSEL('0), // axi4_to_ahb doesn't use hsel + .HPROT(lmem_hprot_from_bridge), + .HWRITE(lmem_hwrite_from_bridge), + .HTRANS(lmem_htrans_from_bridge), + .HSIZE(lmem_hsize_from_bridge), + .HREADY('1), // TODO axi4_to_ahb uses only 'input logic ahb_hready' doesn't have any output like this .HRESETn(rst_l), - .HADDR(mux_haddr_from_bridge), - .HBURST(mux_hburst_from_bridge), + .HADDR(lmem_haddr_from_bridge), + .HBURST(lmem_hburst_from_bridge), // Outputs - .HREADYOUT(mux_hreadyout_from_bridge), - .HRESP(mux_hresp_from_bridge), - .HRDATA(mux_hrdata_from_bridge[63:0]) + .HREADYOUT(lmem_hready_to_bridge), + .HRESP(lmem_hresp_to_bridge), + .HRDATA(lmem_hrdata_to_bridge) ); @@ -1690,21 +1687,22 @@ axi4_to_ahb #(.pt(pt)) lmem_to_bridge_axi4_to_ahb ( .axi_rlast(bridge_s0_rlast), // AHB signals - .ahb_haddr(mux_haddr_from_bridge), - .ahb_hburst(mux_hburst_from_bridge), - .ahb_hmastlock(lsu_hmastlock_from_bridge), - .ahb_hprot(mux_hprot_from_bridge), - .ahb_hsize(mux_hsize_from_bridge), - .ahb_htrans(mux_htrans_from_bridge), - .ahb_hwrite(mux_hwrite_from_bridge), - .ahb_hwdata(mux_hwdata_from_bridge), - - .ahb_hrdata(mux_hrdata_from_bridge), - .ahb_hready(mux_hready_from_bridge), - .ahb_hresp(mux_hresp_from_bridge) + .ahb_haddr(lmem_haddr_from_bridge), + .ahb_hburst(lmem_hburst_from_bridge), + .ahb_hmastlock(lmem_hmastlock_from_bridge), + .ahb_hprot(lmem_hprot_from_bridge), + .ahb_hsize(lmem_hsize_from_bridge), + .ahb_htrans(lmem_htrans_from_bridge), + .ahb_hwrite(lmem_hwrite_from_bridge), + .ahb_hwdata(lmem_hwdata_from_bridge), + + .ahb_hrdata(lmem_hrdata_to_bridge), + .ahb_hready(lmem_hready_to_bridge), + .ahb_hresp(lmem_hresp_to_bridge) ); + ahb_to_axi4 #(.pt(pt)) bridge_m_ahb_to_axi ( .clk(core_clk), .rst_l(rst_l), @@ -1751,14 +1749,14 @@ ahb_to_axi4 #(.pt(pt)) bridge_m_ahb_to_axi ( // AHB-LITE signals // connect lsu master here - .ahb_haddr(lsu_haddr[31:0]), - .ahb_hburst(lsu_hburst), - .ahb_hmastlock(lsu_hmastlock), - .ahb_hprot(lsu_hprot[3:0]), - .ahb_hsize(lsu_hsize[2:0]), - .ahb_htrans(lsu_htrans[1:0]), - .ahb_hwrite(lsu_hwrite), - .ahb_hwdata(lsu_hwdata[63:0]), + .ahb_haddr(mux_haddr[31:0]), + .ahb_hburst(mux_hburst), + .ahb_hmastlock(mux_hmastlock), + .ahb_hprot(mux_hprot[3:0]), + .ahb_hsize(mux_hsize[2:0]), + .ahb_htrans(mux_htrans[1:0]), + .ahb_hwrite(mux_hwrite), + .ahb_hwdata(mux_hwdata[63:0]), .ahb_hsel(mux_hsel), .ahb_hreadyin(mux_hready), .ahb_hrdata(mux_hrdata[63:0]), From f24c95a9b0be921e9b9720d09e01fd5bf6912cfa Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Mon, 25 Nov 2024 12:05:21 +0100 Subject: [PATCH 08/11] connect lsu master to the bridge --- testbench/tb_top.sv | 48 +++++++++++++++++++++++---------------------- 1 file changed, 25 insertions(+), 23 deletions(-) diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index fd6acdc3cc6..044ba35ab1e 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -227,7 +227,9 @@ module tb_top logic [63:0] lsu_hrdata ; logic [63:0] lsu_hwdata ; logic lsu_hready ; + logic lsu_hreadyout ; logic lsu_hresp ; + logic lsu_hsel ; logic [31:0] mux_haddr ; logic [2:0] mux_hburst ; @@ -353,16 +355,16 @@ module tb_top ); `else assign mux_hsel = 1'b1; - assign mux_haddr = lsu_haddr; - assign mux_hwdata = lsu_hwdata; - assign mux_hwrite = lsu_hwrite; - assign mux_htrans = lsu_htrans; - assign mux_hsize = lsu_hsize; - assign mux_hready = lsu_hready; - - assign lsu_hresp = mux_hresp; - assign lsu_hrdata = mux_hrdata; - assign lsu_hready = mux_hreadyout; + // assign mux_haddr = lsu_haddr; + // assign mux_hwdata = lsu_hwdata; + // assign mux_hwrite = lsu_hwrite; + // assign mux_htrans = lsu_htrans; + // assign mux_hsize = lsu_hsize; + // assign mux_hready = lsu_hready; + + // assign lsu_hresp = mux_hresp; + // assign lsu_hrdata = mux_hrdata; + // assign lsu_hready = mux_hreadyout; `endif `ifdef RV_BUILD_AXI4 @@ -1749,19 +1751,19 @@ ahb_to_axi4 #(.pt(pt)) bridge_m_ahb_to_axi ( // AHB-LITE signals // connect lsu master here - .ahb_haddr(mux_haddr[31:0]), - .ahb_hburst(mux_hburst), - .ahb_hmastlock(mux_hmastlock), - .ahb_hprot(mux_hprot[3:0]), - .ahb_hsize(mux_hsize[2:0]), - .ahb_htrans(mux_htrans[1:0]), - .ahb_hwrite(mux_hwrite), - .ahb_hwdata(mux_hwdata[63:0]), - .ahb_hsel(mux_hsel), - .ahb_hreadyin(mux_hready), - .ahb_hrdata(mux_hrdata[63:0]), - .ahb_hreadyout(mux_hreadyout), - .ahb_hresp(mux_hresp) + .ahb_haddr(lsu_haddr[31:0]), + .ahb_hburst(lsu_hburst), + .ahb_hmastlock(lsu_hmastlock), + .ahb_hprot(lsu_hprot[3:0]), + .ahb_hsize(lsu_hsize[2:0]), + .ahb_htrans(lsu_htrans[1:0]), + .ahb_hwrite(lsu_hwrite), + .ahb_hwdata(lsu_hwdata[63:0]), + .ahb_hsel(lsu_hsel), + .ahb_hreadyin(lsu_hready), + .ahb_hrdata(lsu_hrdata[63:0]), + .ahb_hreadyout(lsu_hreadyout), + .ahb_hresp(lsu_hresp) ); From 21ac582ccb429e410a7737a96c57637e5f3405f8 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Mon, 25 Nov 2024 14:29:58 +0100 Subject: [PATCH 09/11] use axi lmem even with ahb configuration --- testbench/ahb_sif.sv | 4 +- testbench/tb_top.sv | 197 +++++++++++++++++++++++++------------------ 2 files changed, 119 insertions(+), 82 deletions(-) diff --git a/testbench/ahb_sif.sv b/testbench/ahb_sif.sv index bd35d1c8d78..adcfd869741 100644 --- a/testbench/ahb_sif.sv +++ b/testbench/ahb_sif.sv @@ -140,7 +140,7 @@ module ahb_sif ( endmodule `endif -`ifdef RV_BUILD_AXI4 +// `ifdef RV_BUILD_AXI4 module axi_slv #( TAGW = 1 ) ( @@ -238,5 +238,5 @@ module axi_slv #( end end endmodule -`endif +// `endif diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index 044ba35ab1e..8a47522b182 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -847,14 +847,14 @@ module tb_top `define DEC rvtop_wrapper.rvtop.veer.dec -`ifdef RV_BUILD_AXI4 +// `ifdef RV_BUILD_AXI4 assign mailbox_write = lmem.awvalid && lmem.awaddr == mem_mailbox && rst_l; assign mailbox_data = lmem.wdata; -`endif -`ifdef RV_BUILD_AHB_LITE - assign mailbox_write = lmem.write && lmem.laddr == mem_mailbox && rst_l; - assign mailbox_data = lmem.HWDATA; -`endif +// `endif +// `ifdef RV_BUILD_AHB_LITE + // assign mailbox_write = lmem.write && lmem.laddr == mem_mailbox && rst_l; + // assign mailbox_data = lmem.HWDATA; +// `endif assign mailbox_data_val = mailbox_data[7:0] > 8'h5 && mailbox_data[7:0] < 8'h7f; @@ -1492,24 +1492,61 @@ ahb_sif imem ( ); -ahb_sif lmem ( +// ahb_sif lmem ( +// use axi memory even in ahb configuration because it goes to axi bridge anyway (so with ahb we'd need to use a converter) +axi_slv lmem( + .aclk(core_clk), + .rst_l(rst_l), // Inputs - .HWDATA(lmem_hwdata_from_bridge), - .HCLK(core_clk), - .HSEL('0), // axi4_to_ahb doesn't use hsel - .HPROT(lmem_hprot_from_bridge), - .HWRITE(lmem_hwrite_from_bridge), - .HTRANS(lmem_htrans_from_bridge), - .HSIZE(lmem_hsize_from_bridge), - .HREADY('1), // TODO axi4_to_ahb uses only 'input logic ahb_hready' doesn't have any output like this - .HRESETn(rst_l), - .HADDR(lmem_haddr_from_bridge), - .HBURST(lmem_hburst_from_bridge), - - // Outputs - .HREADYOUT(lmem_hready_to_bridge), - .HRESP(lmem_hresp_to_bridge), - .HRDATA(lmem_hrdata_to_bridge) + // .HWDATA(lmem_hwdata_from_bridge), + // .HCLK(core_clk), + // .HSEL('0), // axi4_to_ahb doesn't use hsel + // .HPROT(lmem_hprot_from_bridge), + // .HWRITE(lmem_hwrite_from_bridge), + // .HTRANS(lmem_htrans_from_bridge), + // .HSIZE(lmem_hsize_from_bridge), + // .HREADY('1), // TODO axi4_to_ahb uses only 'input logic ahb_hready' doesn't have any output like this + // .HRESETn(rst_l), + // .HADDR(lmem_haddr_from_bridge), + // .HBURST(lmem_hburst_from_bridge), + + // // Outputs + // .HREADYOUT(lmem_hready_to_bridge), + // .HRESP(lmem_hresp_to_bridge), + // .HRDATA(lmem_hrdata_to_bridge) + + .arvalid(bridge_s0_arvalid), + .arready(bridge_s0_arready), + .araddr(bridge_m_axi_araddr), + .arid(bridge_m_axi_arid), + .arlen(bridge_m_axi_arlen), + .arburst(bridge_m_axi_arburst), + .arsize(bridge_m_axi_arsize), + + .rvalid(bridge_s0_rvalid), + .rready(bridge_s0_rready), + .rdata(bridge_s0_rdata), + .rresp(bridge_s0_rresp), + .rid(bridge_s0_rid), + .rlast(bridge_s0_rlast), + + .awvalid(bridge_s0_awvalid), + .awready(bridge_s0_awready), + .awaddr(bridge_m_axi_awaddr), + .awid(bridge_m_axi_awid), + .awlen(bridge_m_axi_awlen), + .awburst(bridge_m_axi_awburst), + .awsize(bridge_m_axi_awsize), + + .wdata(bridge_m_axi_wdata), + .wstrb(bridge_m_axi_wstrb), + .wvalid(bridge_s0_wvalid), + .wready(bridge_s0_wready), + + .bvalid(bridge_s0_bvalid), + .bready(bridge_s0_bready), + .bresp(bridge_s0_bresp), + .bid(bridge_s0_bid) ); @@ -1645,63 +1682,63 @@ axi4_to_ahb #(.pt(pt)) dma_to_bridge_axi4_to_ahb ( .ahb_hresp(dma_hresp) ); -axi4_to_ahb #(.pt(pt)) lmem_to_bridge_axi4_to_ahb ( - .clk(core_clk), - .free_clk(core_clk), - .rst_l(rst_l), - .scan_mode('0), - .bus_clk_en('1), - .clk_override('0), - .dec_tlu_force_halt('0), - - // AXI Write Channels - .axi_awvalid(bridge_s0_awvalid), - .axi_awready(bridge_s0_awready), - .axi_awid(bridge_s0_awid[pt.DMA_BUS_TAG-1:0]), - .axi_awaddr(bridge_s0_awaddr[31:0]), - .axi_awsize(bridge_s0_awsize[2:0]), - .axi_awprot(bridge_s0_awprot[2:0]), - - .axi_wvalid(bridge_s0_wvalid), - .axi_wready(bridge_s0_wready), - .axi_wdata(bridge_s0_wdata[63:0]), - .axi_wstrb(bridge_s0_wstrb[7:0]), - .axi_wlast(bridge_s0_wlast), - - .axi_bvalid(bridge_s0_bvalid), - .axi_bready(bridge_s0_bready), - .axi_bresp(bridge_s0_bresp[1:0]), - .axi_bid(bridge_s0_bid[pt.DMA_BUS_TAG-1:0]), - - // AXI Read Channels - .axi_arvalid(bridge_s0_arvalid), - .axi_arready(bridge_s0_arready), - .axi_arid(bridge_s0_arid[pt.DMA_BUS_TAG-1:0]), - .axi_araddr(bridge_s0_araddr[31:0]), - .axi_arsize(bridge_s0_arsize[2:0]), - .axi_arprot(bridge_s0_arprot[2:0]), - - .axi_rvalid(bridge_s0_rvalid), - .axi_rready(bridge_s0_rready), - .axi_rid(bridge_s0_rid[pt.DMA_BUS_TAG-1:0]), - .axi_rdata(bridge_s0_rdata[63:0]), - .axi_rresp(bridge_s0_rresp[1:0]), - .axi_rlast(bridge_s0_rlast), - - // AHB signals - .ahb_haddr(lmem_haddr_from_bridge), - .ahb_hburst(lmem_hburst_from_bridge), - .ahb_hmastlock(lmem_hmastlock_from_bridge), - .ahb_hprot(lmem_hprot_from_bridge), - .ahb_hsize(lmem_hsize_from_bridge), - .ahb_htrans(lmem_htrans_from_bridge), - .ahb_hwrite(lmem_hwrite_from_bridge), - .ahb_hwdata(lmem_hwdata_from_bridge), - - .ahb_hrdata(lmem_hrdata_to_bridge), - .ahb_hready(lmem_hready_to_bridge), - .ahb_hresp(lmem_hresp_to_bridge) -); +// axi4_to_ahb #(.pt(pt)) lmem_to_bridge_axi4_to_ahb ( +// .clk(core_clk), +// .free_clk(core_clk), +// .rst_l(rst_l), +// .scan_mode('0), +// .bus_clk_en('1), +// .clk_override('0), +// .dec_tlu_force_halt('0), + +// // AXI Write Channels +// .axi_awvalid(bridge_s0_awvalid), +// .axi_awready(bridge_s0_awready), +// .axi_awid(bridge_s0_awid[pt.DMA_BUS_TAG-1:0]), +// .axi_awaddr(bridge_s0_awaddr[31:0]), +// .axi_awsize(bridge_s0_awsize[2:0]), +// .axi_awprot(bridge_s0_awprot[2:0]), + +// .axi_wvalid(bridge_s0_wvalid), +// .axi_wready(bridge_s0_wready), +// .axi_wdata(bridge_s0_wdata[63:0]), +// .axi_wstrb(bridge_s0_wstrb[7:0]), +// .axi_wlast(bridge_s0_wlast), + +// .axi_bvalid(bridge_s0_bvalid), +// .axi_bready(bridge_s0_bready), +// .axi_bresp(bridge_s0_bresp[1:0]), +// .axi_bid(bridge_s0_bid[pt.DMA_BUS_TAG-1:0]), + +// // AXI Read Channels +// .axi_arvalid(bridge_s0_arvalid), +// .axi_arready(bridge_s0_arready), +// .axi_arid(bridge_s0_arid[pt.DMA_BUS_TAG-1:0]), +// .axi_araddr(bridge_s0_araddr[31:0]), +// .axi_arsize(bridge_s0_arsize[2:0]), +// .axi_arprot(bridge_s0_arprot[2:0]), + +// .axi_rvalid(bridge_s0_rvalid), +// .axi_rready(bridge_s0_rready), +// .axi_rid(bridge_s0_rid[pt.DMA_BUS_TAG-1:0]), +// .axi_rdata(bridge_s0_rdata[63:0]), +// .axi_rresp(bridge_s0_rresp[1:0]), +// .axi_rlast(bridge_s0_rlast), + +// // AHB signals +// .ahb_haddr(lmem_haddr_from_bridge), +// .ahb_hburst(lmem_hburst_from_bridge), +// .ahb_hmastlock(lmem_hmastlock_from_bridge), +// .ahb_hprot(lmem_hprot_from_bridge), +// .ahb_hsize(lmem_hsize_from_bridge), +// .ahb_htrans(lmem_htrans_from_bridge), +// .ahb_hwrite(lmem_hwrite_from_bridge), +// .ahb_hwdata(lmem_hwdata_from_bridge), + +// .ahb_hrdata(lmem_hrdata_to_bridge), +// .ahb_hready(lmem_hready_to_bridge), +// .ahb_hresp(lmem_hresp_to_bridge) +// ); From e7f055a2dc2e5f909978c0be30573e3fb608b62b Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Mon, 25 Nov 2024 17:08:00 +0100 Subject: [PATCH 10/11] fix ahb signals in the testbench --- testbench/tb_top.sv | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index 8a47522b182..ca7d7db21a0 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -1494,6 +1494,7 @@ ahb_sif imem ( // ahb_sif lmem ( // use axi memory even in ahb configuration because it goes to axi bridge anyway (so with ahb we'd need to use a converter) +defparam lmem.TAGW = 4; axi_slv lmem( .aclk(core_clk), .rst_l(rst_l), @@ -1678,7 +1679,7 @@ axi4_to_ahb #(.pt(pt)) dma_to_bridge_axi4_to_ahb ( .ahb_hwdata(dma_hwdata), .ahb_hrdata(dma_hrdata), - .ahb_hready(dma_hready), + .ahb_hready(dma_hready_out), .ahb_hresp(dma_hresp) ); @@ -1796,10 +1797,10 @@ ahb_to_axi4 #(.pt(pt)) bridge_m_ahb_to_axi ( .ahb_htrans(lsu_htrans[1:0]), .ahb_hwrite(lsu_hwrite), .ahb_hwdata(lsu_hwdata[63:0]), - .ahb_hsel(lsu_hsel), - .ahb_hreadyin(lsu_hready), + .ahb_hsel('1), + .ahb_hreadyin('1), .ahb_hrdata(lsu_hrdata[63:0]), - .ahb_hreadyout(lsu_hreadyout), + .ahb_hreadyout(lsu_hready), .ahb_hresp(lsu_hresp) ); From a692593a0b24793377e2628c0eee1e31555443e3 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Mon, 25 Nov 2024 17:09:18 +0100 Subject: [PATCH 11/11] do not care about iccm/dccm addressing in ahb_to_axi4 --- design/lib/ahb_to_axi4.sv | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/design/lib/ahb_to_axi4.sv b/design/lib/ahb_to_axi4.sv index a6afc9639d4..b8e36b07bda 100644 --- a/design/lib/ahb_to_axi4.sv +++ b/design/lib/ahb_to_axi4.sv @@ -209,8 +209,7 @@ import el2_pkg::*; assign ahb_hrdata[63:0] = buf_rdata[63:0]; assign ahb_hresp = ((ahb_htrans_q[1:0] != 2'b0) & (buf_state != IDLE) & - ((~(ahb_addr_in_dccm | ahb_addr_in_iccm)) | // request not for ICCM or DCCM - ((ahb_addr_in_iccm | (ahb_addr_in_dccm & ahb_hwrite_q)) & ~((ahb_hsize_q[1:0] == 2'b10) | (ahb_hsize_q[1:0] == 2'b11))) | // ICCM Rd/Wr OR DCCM Wr not the right size + ( ((ahb_hsize_q[2:0] == 3'h1) & ahb_haddr_q[0]) | // HW size but unaligned ((ahb_hsize_q[2:0] == 3'h2) & (|ahb_haddr_q[1:0])) | // W size but unaligned ((ahb_hsize_q[2:0] == 3'h3) & (|ahb_haddr_q[2:0])))) | // DW size but unaligned