diff --git a/design/lib/ahb_to_axi4.sv b/design/lib/ahb_to_axi4.sv index a6afc9639d4..b8e36b07bda 100644 --- a/design/lib/ahb_to_axi4.sv +++ b/design/lib/ahb_to_axi4.sv @@ -209,8 +209,7 @@ import el2_pkg::*; assign ahb_hrdata[63:0] = buf_rdata[63:0]; assign ahb_hresp = ((ahb_htrans_q[1:0] != 2'b0) & (buf_state != IDLE) & - ((~(ahb_addr_in_dccm | ahb_addr_in_iccm)) | // request not for ICCM or DCCM - ((ahb_addr_in_iccm | (ahb_addr_in_dccm & ahb_hwrite_q)) & ~((ahb_hsize_q[1:0] == 2'b10) | (ahb_hsize_q[1:0] == 2'b11))) | // ICCM Rd/Wr OR DCCM Wr not the right size + ( ((ahb_hsize_q[2:0] == 3'h1) & ahb_haddr_q[0]) | // HW size but unaligned ((ahb_hsize_q[2:0] == 3'h2) & (|ahb_haddr_q[1:0])) | // W size but unaligned ((ahb_hsize_q[2:0] == 3'h3) & (|ahb_haddr_q[2:0])))) | // DW size but unaligned diff --git a/testbench/ahb_sif.sv b/testbench/ahb_sif.sv index bd35d1c8d78..adcfd869741 100644 --- a/testbench/ahb_sif.sv +++ b/testbench/ahb_sif.sv @@ -140,7 +140,7 @@ module ahb_sif ( endmodule `endif -`ifdef RV_BUILD_AXI4 +// `ifdef RV_BUILD_AXI4 module axi_slv #( TAGW = 1 ) ( @@ -238,5 +238,5 @@ module axi_slv #( end end endmodule -`endif +// `endif diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index 60b393f22f6..ca7d7db21a0 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -44,6 +44,149 @@ module tb_top ); `endif +`ifdef RV_BUILD_AHB_LITE + wire bridge_m_axi_awvalid; + wire bridge_m_axi_awready; + wire [4-1:0] bridge_m_axi_awid; + wire [31:0] bridge_m_axi_awaddr; + wire [3:0] bridge_m_axi_awregion; + wire [7:0] bridge_m_axi_awlen; + wire [2:0] bridge_m_axi_awsize; + wire [1:0] bridge_m_axi_awburst; + wire bridge_m_axi_awlock; + wire [3:0] bridge_m_axi_awcache; + wire [2:0] bridge_m_axi_awprot; + wire [3:0] bridge_m_axi_awqos; + + wire bridge_m_axi_wvalid; + wire bridge_m_axi_wready; + wire [63:0] bridge_m_axi_wdata; + wire [7:0] bridge_m_axi_wstrb; + wire bridge_m_axi_wlast; + + wire bridge_m_axi_bvalid; + wire bridge_m_axi_bready; + wire [1:0] bridge_m_axi_bresp; + wire [4-1:0] bridge_m_axi_bid; + + // AXI Read Channels + wire bridge_m_axi_arvalid; + wire bridge_m_axi_arready; + wire [4-1:0] bridge_m_axi_arid; + wire [31:0] bridge_m_axi_araddr; + wire [3:0] bridge_m_axi_arregion; + wire [7:0] bridge_m_axi_arlen; + wire [2:0] bridge_m_axi_arsize; + wire [1:0] bridge_m_axi_arburst; + wire bridge_m_axi_arlock; + wire [3:0] bridge_m_axi_arcache; + wire [2:0] bridge_m_axi_arprot; + wire [3:0] bridge_m_axi_arqos; + + wire bridge_m_axi_rvalid; + wire bridge_m_axi_rready; + wire [4-1:0] bridge_m_axi_rid; + wire [63:0] bridge_m_axi_rdata; + wire [1:0] bridge_m_axi_rresp; + wire bridge_m_axi_rlast; + wire bridge_m_axi_awuser; + wire bridge_m_axi_wuser; + wire bridge_m_axi_buser; + wire bridge_m_axi_aruser; + wire bridge_m_axi_ruser; + + + wire bridge_s0_awvalid; + wire bridge_s0_awready; + wire [4-1:0] bridge_s0_awid; + wire [31:0] bridge_s0_awaddr; + wire [2:0] bridge_s0_awsize; + wire [2:0] bridge_s0_awprot; + wire [7:0] bridge_s0_awlen; + wire [1:0] bridge_s0_awburst; + wire bridge_s0_wvalid; + wire bridge_s0_wready; + wire [63:0] bridge_s0_wdata; + wire [7:0] bridge_s0_wstrb; + wire bridge_s0_wlast; + wire bridge_s0_bvalid; + wire bridge_s0_bready; + wire [1:0] bridge_s0_bresp; + wire [4-1:0] bridge_s0_bid; + wire bridge_s0_arvalid; + wire bridge_s0_arready; + wire [4-1:0] bridge_s0_arid; + wire [31:0] bridge_s0_araddr; + wire [2:0] bridge_s0_arsize; + wire [2:0] bridge_s0_arprot; + wire [7:0] bridge_s0_arlen; + wire [1:0] bridge_s0_arburst; + wire bridge_s0_rvalid; + wire bridge_s0_rready; + wire [4-1:0] bridge_s0_rid; + wire [63:0] bridge_s0_rdata; + wire [1:0] bridge_s0_rresp; + wire bridge_s0_rlast; + + + wire bridge_s1_dma_axi_awvalid; + wire bridge_s1_dma_axi_awready; + wire [4-1:0] bridge_s1_dma_axi_awid; + wire [31:0] bridge_s1_dma_axi_awaddr; + wire [2:0] bridge_s1_dma_axi_awsize; + wire [2:0] bridge_s1_dma_axi_awprot; + wire [7:0] bridge_s1_dma_axi_awlen; + wire [1:0] bridge_s1_dma_axi_awburst; + wire bridge_s1_dma_axi_wvalid; + wire bridge_s1_dma_axi_wready; + wire [63:0] bridge_s1_dma_axi_wdata; + wire [7:0] bridge_s1_dma_axi_wstrb; + wire bridge_s1_dma_axi_wlast; + wire bridge_s1_dma_axi_bvalid; + wire bridge_s1_dma_axi_bready; + wire [1:0] bridge_s1_dma_axi_bresp; + wire [4-1:0] bridge_s1_dma_axi_bid; + wire bridge_s1_dma_axi_arvalid; + wire bridge_s1_dma_axi_arready; + wire [4-1:0] bridge_s1_dma_axi_arid; + wire [31:0] bridge_s1_dma_axi_araddr; + wire [2:0] bridge_s1_dma_axi_arsize; + wire [2:0] bridge_s1_dma_axi_arprot; + wire [7:0] bridge_s1_dma_axi_arlen; + wire [1:0] bridge_s1_dma_axi_arburst; + wire bridge_s1_dma_axi_rvalid; + wire bridge_s1_dma_axi_rready; + wire [4-1:0] bridge_s1_dma_axi_rid; + wire [63:0] bridge_s1_dma_axi_rdata; + wire [1:0] bridge_s1_dma_axi_rresp; + wire bridge_s1_dma_axi_rlast; + + logic [31:0] dma_haddr ; + logic [2:0] dma_hburst ; + logic dma_hmastlock ; + logic [3:0] dma_hprot ; + logic [2:0] dma_hsize ; + logic [1:0] dma_htrans ; + logic dma_hwrite ; + logic dma_hreadyout ; + logic dma_hreadyin ; + + logic [31:0] lmem_haddr_from_bridge ; + logic [2:0] lmem_hburst_from_bridge ; + logic lmem_hmastlock_from_bridge ; + logic [3:0] lmem_hprot_from_bridge ; + logic [2:0] lmem_hsize_from_bridge ; + logic [1:0] lmem_htrans_from_bridge ; + logic lmem_hwrite_from_bridge ; + logic [63:0] lmem_hwdata_from_bridge ; + + logic lmem_hready_to_bridge ; + logic lmem_hresp_to_bridge ; + logic [63:0] lmem_hrdata_to_bridge ; + + +`endif // RV_BUILD_AHB_LITE + `ifndef VERILATOR bit core_clk; bit [31:0] mem_signature_begin = 32'd0; // TODO: @@ -84,7 +227,9 @@ module tb_top logic [63:0] lsu_hrdata ; logic [63:0] lsu_hwdata ; logic lsu_hready ; + logic lsu_hreadyout ; logic lsu_hresp ; + logic lsu_hsel ; logic [31:0] mux_haddr ; logic [2:0] mux_hburst ; @@ -210,16 +355,16 @@ module tb_top ); `else assign mux_hsel = 1'b1; - assign mux_haddr = lsu_haddr; - assign mux_hwdata = lsu_hwdata; - assign mux_hwrite = lsu_hwrite; - assign mux_htrans = lsu_htrans; - assign mux_hsize = lsu_hsize; - assign mux_hready = lsu_hready; - - assign lsu_hresp = mux_hresp; - assign lsu_hrdata = mux_hrdata; - assign lsu_hready = mux_hreadyout; + // assign mux_haddr = lsu_haddr; + // assign mux_hwdata = lsu_hwdata; + // assign mux_hwrite = lsu_hwrite; + // assign mux_htrans = lsu_htrans; + // assign mux_hsize = lsu_hsize; + // assign mux_hready = lsu_hready; + + // assign lsu_hresp = mux_hresp; + // assign lsu_hrdata = mux_hrdata; + // assign lsu_hready = mux_hreadyout; `endif `ifdef RV_BUILD_AXI4 @@ -702,14 +847,14 @@ module tb_top `define DEC rvtop_wrapper.rvtop.veer.dec -`ifdef RV_BUILD_AXI4 +// `ifdef RV_BUILD_AXI4 assign mailbox_write = lmem.awvalid && lmem.awaddr == mem_mailbox && rst_l; assign mailbox_data = lmem.wdata; -`endif -`ifdef RV_BUILD_AHB_LITE - assign mailbox_write = lmem.write && lmem.laddr == mem_mailbox && rst_l; - assign mailbox_data = lmem.HWDATA; -`endif +// `endif +// `ifdef RV_BUILD_AHB_LITE + // assign mailbox_write = lmem.write && lmem.laddr == mem_mailbox && rst_l; + // assign mailbox_data = lmem.HWDATA; +// `endif assign mailbox_data_val = mailbox_data[7:0] > 8'h5 && mailbox_data[7:0] < 8'h7f; @@ -1030,21 +1175,30 @@ veer_wrapper rvtop_wrapper ( //--------------------------------------------------------------- // DMA Slave //--------------------------------------------------------------- - .dma_haddr ( '0 ), - .dma_hburst ( '0 ), - .dma_hmastlock ( '0 ), - .dma_hprot ( '0 ), - .dma_hsize ( '0 ), - .dma_htrans ( '0 ), - .dma_hwrite ( '0 ), - .dma_hwdata ( '0 ), + .dma_haddr (dma_haddr), + .dma_hburst (dma_hburst), + .dma_hmastlock (dma_hmastlock), + .dma_hprot (dma_hprot), + .dma_hsize (dma_hsize), + .dma_htrans (dma_htrans), + .dma_hwrite (dma_hwrite), + .dma_hwdata (dma_hwdata), + + // .dma_haddr ('0), + // .dma_hburst ('0), + // .dma_hmastlock ('0), + // .dma_hprot ('0), + // .dma_hsize ('0), + // .dma_htrans ('0), + // .dma_hwrite ('0), + // .dma_hwdata ('0), .dma_hrdata ( dma_hrdata ), .dma_hresp ( dma_hresp ), .dma_hsel ( 1'b1 ), .dma_hreadyin ( dma_hready_out ), .dma_hreadyout ( dma_hready_out ), -`endif +`endif // RV_BUILD_AHB_LITE `ifdef RV_BUILD_AXI4 //-------------------------- LSU AXI signals-------------------------- // AXI Write Channels @@ -1338,27 +1492,320 @@ ahb_sif imem ( ); -ahb_sif lmem ( +// ahb_sif lmem ( +// use axi memory even in ahb configuration because it goes to axi bridge anyway (so with ahb we'd need to use a converter) +defparam lmem.TAGW = 4; +axi_slv lmem( + .aclk(core_clk), + .rst_l(rst_l), // Inputs - .HWDATA(mux_hwdata), - .HCLK(core_clk), - .HSEL(mux_hsel), - .HPROT(mux_hprot), - .HWRITE(mux_hwrite), - .HTRANS(mux_htrans), - .HSIZE(mux_hsize), - .HREADY(mux_hready), - .HRESETn(rst_l), - .HADDR(mux_haddr), - .HBURST(mux_hburst), + // .HWDATA(lmem_hwdata_from_bridge), + // .HCLK(core_clk), + // .HSEL('0), // axi4_to_ahb doesn't use hsel + // .HPROT(lmem_hprot_from_bridge), + // .HWRITE(lmem_hwrite_from_bridge), + // .HTRANS(lmem_htrans_from_bridge), + // .HSIZE(lmem_hsize_from_bridge), + // .HREADY('1), // TODO axi4_to_ahb uses only 'input logic ahb_hready' doesn't have any output like this + // .HRESETn(rst_l), + // .HADDR(lmem_haddr_from_bridge), + // .HBURST(lmem_hburst_from_bridge), + + // // Outputs + // .HREADYOUT(lmem_hready_to_bridge), + // .HRESP(lmem_hresp_to_bridge), + // .HRDATA(lmem_hrdata_to_bridge) + + .arvalid(bridge_s0_arvalid), + .arready(bridge_s0_arready), + .araddr(bridge_m_axi_araddr), + .arid(bridge_m_axi_arid), + .arlen(bridge_m_axi_arlen), + .arburst(bridge_m_axi_arburst), + .arsize(bridge_m_axi_arsize), + + .rvalid(bridge_s0_rvalid), + .rready(bridge_s0_rready), + .rdata(bridge_s0_rdata), + .rresp(bridge_s0_rresp), + .rid(bridge_s0_rid), + .rlast(bridge_s0_rlast), + + .awvalid(bridge_s0_awvalid), + .awready(bridge_s0_awready), + .awaddr(bridge_m_axi_awaddr), + .awid(bridge_m_axi_awid), + .awlen(bridge_m_axi_awlen), + .awburst(bridge_m_axi_awburst), + .awsize(bridge_m_axi_awsize), + + .wdata(bridge_m_axi_wdata), + .wstrb(bridge_m_axi_wstrb), + .wvalid(bridge_s0_wvalid), + .wready(bridge_s0_wready), + + .bvalid(bridge_s0_bvalid), + .bready(bridge_s0_bready), + .bresp(bridge_s0_bresp), + .bid(bridge_s0_bid) +); - // Outputs - .HREADYOUT(mux_hreadyout), - .HRESP(mux_hresp), - .HRDATA(mux_hrdata[63:0]) + +axi_lsu_dma_bridge # (4,4) bridge( + .clk(core_clk), + .reset_l(rst_l), + + // master read bus + .m_arvalid(bridge_m_axi_arvalid), + .m_arid(bridge_m_axi_arid), + .m_araddr(bridge_m_axi_araddr), + .m_arready(bridge_m_axi_arready), + + .m_rvalid(bridge_m_axi_rvalid), + .m_rready(bridge_m_axi_rready), + .m_rdata(bridge_m_axi_rdata), + .m_rid(bridge_m_axi_rid), + .m_rresp(bridge_m_axi_rresp), + .m_rlast(bridge_m_axi_rlast), + + // master write bus + .m_awvalid(bridge_m_axi_awvalid), + .m_awid(bridge_m_axi_awid), + .m_awaddr(bridge_m_axi_awaddr), + .m_awready(bridge_m_axi_awready), + + .m_wvalid(bridge_m_axi_wvalid), + .m_wready(bridge_m_axi_wready), + + .m_bresp(bridge_m_axi_bresp), + .m_bvalid(bridge_m_axi_bvalid), + .m_bid(bridge_m_axi_bid), + .m_bready(bridge_m_axi_bready), + + // lmem + .s0_arvalid(bridge_s0_arvalid), + .s0_arready(bridge_s0_arready), + + .s0_rvalid(bridge_s0_rvalid), + .s0_rid(bridge_s0_rid), + .s0_rresp(bridge_s0_rresp), + .s0_rdata(bridge_s0_rdata), + .s0_rlast(bridge_s0_rlast), + .s0_rready(bridge_s0_rready), + + .s0_awvalid(bridge_s0_awvalid), + .s0_awready(bridge_s0_awready), + + .s0_wvalid(bridge_s0_wvalid), + .s0_wready(bridge_s0_wready), + + .s0_bresp(bridge_s0_bresp), + .s0_bvalid(bridge_s0_bvalid), + .s0_bid(bridge_s0_bid), + .s0_bready(bridge_s0_bready), + + .s1_arvalid(bridge_s1_dma_axi_arvalid), + .s1_arready(bridge_s1_dma_axi_arready), + + .s1_rvalid(bridge_s1_dma_axi_rvalid), + .s1_rresp(bridge_s1_dma_axi_rresp), + .s1_rdata(bridge_s1_dma_axi_rdata), + .s1_rlast(bridge_s1_dma_axi_rlast), + .s1_rready(bridge_s1_dma_axi_rready), + + .s1_awvalid(bridge_s1_dma_axi_awvalid), + .s1_awready(bridge_s1_dma_axi_awready), + + .s1_wvalid(bridge_s1_dma_axi_wvalid), + .s1_wready(bridge_s1_dma_axi_wready), + + .s1_bresp(bridge_s1_dma_axi_bresp), + .s1_bvalid(bridge_s1_dma_axi_bvalid), + .s1_bready(bridge_s1_dma_axi_bready) ); -`endif + +axi4_to_ahb #(.pt(pt)) dma_to_bridge_axi4_to_ahb ( + .clk(core_clk), + .free_clk(core_clk), + .rst_l(rst_l), + .scan_mode('0), + .bus_clk_en('1), + .clk_override('0), + .dec_tlu_force_halt('0), + + // AXI Write Channels + .axi_awvalid(bridge_s1_dma_axi_awvalid), + .axi_awready(bridge_s1_dma_axi_awready), + .axi_awid(bridge_s1_dma_axi_awid[pt.DMA_BUS_TAG-1:0]), + .axi_awaddr(bridge_s1_dma_axi_awaddr[31:0]), + .axi_awsize(bridge_s1_dma_axi_awsize[2:0]), + .axi_awprot(bridge_s1_dma_axi_awprot[2:0]), + + .axi_wvalid(bridge_s1_dma_axi_wvalid), + .axi_wready(bridge_s1_dma_axi_wready), + .axi_wdata(bridge_s1_dma_axi_wdata[63:0]), + .axi_wstrb(bridge_s1_dma_axi_wstrb[7:0]), + .axi_wlast(bridge_s1_dma_axi_wlast), + + .axi_bvalid(bridge_s1_dma_axi_bvalid), + .axi_bready(bridge_s1_dma_axi_bready), + .axi_bresp(bridge_s1_dma_axi_bresp[1:0]), + .axi_bid(bridge_s1_dma_axi_bid[pt.DMA_BUS_TAG-1:0]), + + // AXI Read Channels + .axi_arvalid(bridge_s1_dma_axi_arvalid), + .axi_arready(bridge_s1_dma_axi_arready), + .axi_arid(bridge_s1_dma_axi_arid[pt.DMA_BUS_TAG-1:0]), + .axi_araddr(bridge_s1_dma_axi_araddr[31:0]), + .axi_arsize(bridge_s1_dma_axi_arsize[2:0]), + .axi_arprot(bridge_s1_dma_axi_arprot[2:0]), + + .axi_rvalid(bridge_s1_dma_axi_rvalid), + .axi_rready(bridge_s1_dma_axi_rready), + .axi_rid(bridge_s1_dma_axi_rid[pt.DMA_BUS_TAG-1:0]), + .axi_rdata(bridge_s1_dma_axi_rdata[63:0]), + .axi_rresp(bridge_s1_dma_axi_rresp[1:0]), + .axi_rlast(bridge_s1_dma_axi_rlast), + + // AHB signals + .ahb_haddr(dma_haddr), + .ahb_hburst(dma_hburst), + .ahb_hmastlock(dma_hmastlock), + .ahb_hprot(dma_hprot), + .ahb_hsize(dma_hsize), + .ahb_htrans(dma_htrans), + .ahb_hwrite(dma_hwrite), + .ahb_hwdata(dma_hwdata), + + .ahb_hrdata(dma_hrdata), + .ahb_hready(dma_hready_out), + .ahb_hresp(dma_hresp) +); + +// axi4_to_ahb #(.pt(pt)) lmem_to_bridge_axi4_to_ahb ( +// .clk(core_clk), +// .free_clk(core_clk), +// .rst_l(rst_l), +// .scan_mode('0), +// .bus_clk_en('1), +// .clk_override('0), +// .dec_tlu_force_halt('0), + +// // AXI Write Channels +// .axi_awvalid(bridge_s0_awvalid), +// .axi_awready(bridge_s0_awready), +// .axi_awid(bridge_s0_awid[pt.DMA_BUS_TAG-1:0]), +// .axi_awaddr(bridge_s0_awaddr[31:0]), +// .axi_awsize(bridge_s0_awsize[2:0]), +// .axi_awprot(bridge_s0_awprot[2:0]), + +// .axi_wvalid(bridge_s0_wvalid), +// .axi_wready(bridge_s0_wready), +// .axi_wdata(bridge_s0_wdata[63:0]), +// .axi_wstrb(bridge_s0_wstrb[7:0]), +// .axi_wlast(bridge_s0_wlast), + +// .axi_bvalid(bridge_s0_bvalid), +// .axi_bready(bridge_s0_bready), +// .axi_bresp(bridge_s0_bresp[1:0]), +// .axi_bid(bridge_s0_bid[pt.DMA_BUS_TAG-1:0]), + +// // AXI Read Channels +// .axi_arvalid(bridge_s0_arvalid), +// .axi_arready(bridge_s0_arready), +// .axi_arid(bridge_s0_arid[pt.DMA_BUS_TAG-1:0]), +// .axi_araddr(bridge_s0_araddr[31:0]), +// .axi_arsize(bridge_s0_arsize[2:0]), +// .axi_arprot(bridge_s0_arprot[2:0]), + +// .axi_rvalid(bridge_s0_rvalid), +// .axi_rready(bridge_s0_rready), +// .axi_rid(bridge_s0_rid[pt.DMA_BUS_TAG-1:0]), +// .axi_rdata(bridge_s0_rdata[63:0]), +// .axi_rresp(bridge_s0_rresp[1:0]), +// .axi_rlast(bridge_s0_rlast), + +// // AHB signals +// .ahb_haddr(lmem_haddr_from_bridge), +// .ahb_hburst(lmem_hburst_from_bridge), +// .ahb_hmastlock(lmem_hmastlock_from_bridge), +// .ahb_hprot(lmem_hprot_from_bridge), +// .ahb_hsize(lmem_hsize_from_bridge), +// .ahb_htrans(lmem_htrans_from_bridge), +// .ahb_hwrite(lmem_hwrite_from_bridge), +// .ahb_hwdata(lmem_hwdata_from_bridge), + +// .ahb_hrdata(lmem_hrdata_to_bridge), +// .ahb_hready(lmem_hready_to_bridge), +// .ahb_hresp(lmem_hresp_to_bridge) +// ); + + + +ahb_to_axi4 #(.pt(pt)) bridge_m_ahb_to_axi ( + .clk(core_clk), + .rst_l(rst_l), + .scan_mode('0), + .bus_clk_en(1'b1), + .clk_override('0), + + // AXI Write Channels + .axi_awvalid(bridge_m_axi_awvalid), + .axi_awready(bridge_m_axi_awready), + .axi_awid(bridge_m_axi_awid[pt.LSU_BUS_TAG-1:0]), + .axi_awaddr(bridge_m_axi_awaddr[31:0]), + .axi_awsize(bridge_m_axi_awsize[2:0]), + .axi_awprot(bridge_m_axi_awprot[2:0]), + .axi_awlen(bridge_m_axi_awlen), + .axi_awburst(bridge_m_axi_awburst), + + .axi_wvalid(bridge_m_axi_wvalid), + .axi_wready(bridge_m_axi_wready), + .axi_wdata(bridge_m_axi_wdata[63:0]), + .axi_wstrb(bridge_m_axi_wstrb[7:0]), + .axi_wlast(bridge_m_axi_wlast), + + .axi_bvalid(bridge_m_axi_bvalid), + .axi_bready(bridge_m_axi_bready), + .axi_bresp(bridge_m_axi_bresp[1:0]), + .axi_bid(bridge_m_axi_bid[pt.LSU_BUS_TAG-1:0]), + + // AXI Read Channels + .axi_arvalid(bridge_m_axi_arvalid), + .axi_arready(bridge_m_axi_arready), + .axi_arid(bridge_m_axi_arid[pt.LSU_BUS_TAG-1:0]), + .axi_araddr(bridge_m_axi_araddr[31:0]), + .axi_arsize(bridge_m_axi_arsize[2:0]), + .axi_arprot(bridge_m_axi_arprot[2:0]), + .axi_arlen(bridge_m_axi_arlen), + .axi_arburst(bridge_m_axi_arburst), + + .axi_rvalid(bridge_m_axi_rvalid), + .axi_rready(bridge_m_axi_rready), + .axi_rid(bridge_m_axi_rid[pt.LSU_BUS_TAG-1:0]), + .axi_rdata(bridge_m_axi_rdata[63:0]), + .axi_rresp(bridge_m_axi_rresp[1:0]), + + // AHB-LITE signals + // connect lsu master here + .ahb_haddr(lsu_haddr[31:0]), + .ahb_hburst(lsu_hburst), + .ahb_hmastlock(lsu_hmastlock), + .ahb_hprot(lsu_hprot[3:0]), + .ahb_hsize(lsu_hsize[2:0]), + .ahb_htrans(lsu_htrans[1:0]), + .ahb_hwrite(lsu_hwrite), + .ahb_hwdata(lsu_hwdata[63:0]), + .ahb_hsel('1), + .ahb_hreadyin('1), + .ahb_hrdata(lsu_hrdata[63:0]), + .ahb_hreadyout(lsu_hready), + .ahb_hresp(lsu_hresp) +); + + +`endif // RV_BUILD_AHB_LITE `ifdef RV_BUILD_AXI4 axi_slv #(.TAGW(`RV_IFU_BUS_TAG)) imem( .aclk(core_clk),