From d14fcdb6cb7d5c9d0c3d08a62f91100f09fc33f1 Mon Sep 17 00:00:00 2001
From: Wojciech Sipak <wsipak@antmicro.com>
Date: Wed, 27 Nov 2024 17:19:29 +0100
Subject: [PATCH] bring back openocd configuration

---
 testbench/tb_top.sv | 44 ++++++++++++++++++++++----------------------
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv
index b540692bf31..9c3c52172d0 100644
--- a/testbench/tb_top.sv
+++ b/testbench/tb_top.sv
@@ -258,17 +258,17 @@ module tb_top
         .hrdata_i            (mux_hrdata)
     );
    `else
-   // assign mux_hsel = 1'b1;
-   // assign mux_haddr = lsu_haddr;
-   // assign mux_hwdata = lsu_hwdata;
-   // assign mux_hwrite = lsu_hwrite;
-   // assign mux_htrans = lsu_htrans;
-   // assign mux_hsize = lsu_hsize;
-   // assign mux_hready = lsu_hready;
-
-   // assign lsu_hresp = mux_hresp;
-   // assign lsu_hrdata = mux_hrdata;
-   // assign lsu_hready = mux_hreadyout;
+   assign mux_hsel = 1'b1;
+   assign mux_haddr = lsu_haddr;
+   assign mux_hwdata = lsu_hwdata;
+   assign mux_hwrite = lsu_hwrite;
+   assign mux_htrans = lsu_htrans;
+   assign mux_hsize = lsu_hsize;
+   assign mux_hreadyout = lsu_hready;
+
+   assign lsu_hresp = mux_hresp;
+   assign lsu_hrdata = mux_hrdata;
+   assign lsu_hready = mux_hready;
    `endif
 
 `ifdef RV_BUILD_AXI4
@@ -1433,19 +1433,19 @@ ahb_lsu_dma_bridge #(.pt(pt)) bridge (
     .clk(core_clk),
     .reset_l(rst_l),
 
-    .m_ahb_haddr(lsu_haddr[31:0]),
-    .m_ahb_hburst(lsu_hburst),
-    .m_ahb_hmastlock(lsu_hmastlock),
-    .m_ahb_hprot(lsu_hprot[3:0]),
-    .m_ahb_hsize(lsu_hsize[2:0]),
-    .m_ahb_htrans(lsu_htrans[1:0]),
-    .m_ahb_hwrite(lsu_hwrite),
-    .m_ahb_hwdata(lsu_hwdata[63:0]),
+    .m_ahb_haddr(mux_haddr[31:0]),
+    .m_ahb_hburst(mux_hburst),
+    .m_ahb_hmastlock(mux_hmastlock),
+    .m_ahb_hprot(mux_hprot[3:0]),
+    .m_ahb_hsize(mux_hsize[2:0]),
+    .m_ahb_htrans(mux_htrans[1:0]),
+    .m_ahb_hwrite(mux_hwrite),
+    .m_ahb_hwdata(mux_hwdata[63:0]),
     .m_ahb_hsel('1),
     .m_ahb_hreadyin('1),
-    .m_ahb_hrdata(lsu_hrdata[63:0]),
-    .m_ahb_hreadyout(lsu_hready),
-    .m_ahb_hresp(lsu_hresp),
+    .m_ahb_hrdata(mux_hrdata[63:0]),
+    .m_ahb_hreadyout(mux_hready),
+    .m_ahb_hresp(mux_hresp),
     
     .s0_axi_awvalid(bridge_s0_awvalid),
     .s0_axi_awready(bridge_s0_awready),