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Wrong disassembly in MIPS32 #1990

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pr0cf5 opened this issue Apr 12, 2023 · 1 comment · Fixed by #2410
Closed

Wrong disassembly in MIPS32 #1990

pr0cf5 opened this issue Apr 12, 2023 · 1 comment · Fixed by #2410

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@pr0cf5
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pr0cf5 commented Apr 12, 2023

In MIPS32, there is a typo in the register class listing. Specifically, in MipsGenRegisterInfo.inc, the list of FGRCC registers is incorrectly listed with FGR32 registers. This appears to be a trivial mistake due to copy-and-paste.

Currently, the decoding of FGRCC registers is not supported, so this mistake does not currently affect the disassembly output. However, with the introduction of cmp.condn.s instructions, this error may become problematic in the future. Please correct this mistake to ensure accuracy in the register decoding and to avoid potential issues with new instructions.

static const MCPhysReg FGR32[] = {
    Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31,
  };

  // FGR32 Bit set.
  static const uint8_t FGR32Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
  };

  // FGRCC Register Class...
  static const MCPhysReg FGRCC[] = {
    Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31,
  };
@XVilka
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XVilka commented May 29, 2023

Should be addressed by @brightprogrammer as part of auto-sync effort: #2015

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