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some instruction not test in q8200 #14

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quamtum opened this issue Mar 15, 2023 · 2 comments
Open

some instruction not test in q8200 #14

quamtum opened this issue Mar 15, 2023 · 2 comments

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@quamtum
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quamtum commented Mar 15, 2023

Hi All
When I check cult result, find some instruction not test in q8200
not test:
lea r16,m
movnti m32, r32
movnti m64, r64

only mmx type not test, sse2 type test:
maskmovq mm1,mm2
pavgb mm, mm
pavgb mm, m64 {a}
pavgb mm, m64 {u}
pavgw mm, mm
pavgw mm, m64 {a}
pavgw mm, m64 {u}
pextrw r32, mm, i8
pinsrw mm, r32, i8
pinsrw mm, m16 {a}, i8
pinsrw mm, m16 {u}, i8
pmaxsw mm, mm
pmaxsw mm, m64 {a}
pmaxsw mm, m64 {u}
pmaxub mm, mm
pmaxub mm, m64 {a}
pmaxub mm, m64 {u}
pminsw mm, mm
pminsw mm, m64 {a}
pminsw mm, m64 {u}
pminub mm, mm
pminub mm, m64 {a}
pminub mm, m64 {u}
pmovmskb r32, mm
pmulhuw mm, mm
pmulhuw mm, m64 {a}
pmulhuw mm, m64 {u}
psadbw mm, mm
psadbw mm, m64 {a}
psadbw mm, m64 {u}
pshufw mm, mm, i8
pshufw mm, m64 {a}, i8
pshufw mm, m64 {u}, i8

not same op code:
sar qword ptr [rsp+1], 0 ; 48C17C240100 //op code=C1 and length is longer
sar qword ptr [rsp+9], 1 ; 48D17C2409 //op code=D1 and length is shorter
sar qword ptr [rsp+17], 2 ; 48C17C241102

sar r8, 1
sar r16, 1
sar r32, 1
sar r64, 1
sar m8, 1
sar m16, 1
sar m32, 1
sar m64, 1
shl r8, 1
shl r16, 1
shl r32, 1
shl r64, 1
shl m8, 1
shl m16, 1
shl m32, 1
shl m64, 1
shr r8, 1
shr r16, 1
shr r32, 1
shr r64, 1
shr m8, 1
shr m16, 1
shr m32, 1
shr m64, 1

@kobalicek
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I think asmjit misdetects MMX2 in this case, I would have to check the impl (you are maybe the first testing cult on such CPU it seems)

@kobalicek
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I think this should have been fixed in asmjit by asmjit/asmjit@4163483

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