Welcome to our Introduction to Computer Architecture Education Kit!
Our flagship offering to universities worldwide is the Arm University Program Education Kit series.
These self-contained educational materials offered exclusively and at no cost to academics and teaching staff worldwide. They’re designed to support your day-to-day teaching on core electronic engineering and computer science subjects. You have the freedom to choose which modules to teach – you can use all the modules in the Education Kit or only those that are most appropriate to your teaching outcomes.
Our Introduction to Computer Architecture Education Kit equips your students with the fundamental concepts of computer architecture and how these concepts are applied and implemented in modern processors. This kit is suitable for introductory and mid-level computer architecture courses in Electronic and Computer Engineering, and Computer Science. A full description of the education kit can be found here.
- A full set of lecture slides, ready for use in a typical 10-12 week undergraduate course (full syllabus below).
- Lab manual with solutions for faculty are available upon request from here. The labs are based on a simple 5-stage processor for education purposes called the Arm Education Core, which is written in Verilog and can run a subset of the Armv8-A Assembly instructions. These labs provide a full hands-on experience of demonstrating and implementing Computer Architecture concepts such as pipelining, forwarding paths, stalls, control hazard solution using the Arm Education Core.
- Prerequisites: Digital electronics, basics of hardware description language (Verilog), and familiarity with basic Assembly programming.
To produce students with knowledge of the fundamental topics and concepts of computer architecture including the application of these with modern Arm processors.
- An Introduction to Computer Architecture
- Fundamentals of Computer Design
- Pipelining
- Branches and Limits to Pipelining
- Exploiting Instruction-Level Parallelism
- Memory
- Caches
- Multicore
- Multithreading
- Vector, SIMD, GPUs
- SoC Case Study
You are free to fork or clone this material. See LICENSE.md for the complete license.
Arm is committed to making the language we use inclusive, meaningful, and respectful. Our goal is to remove and replace non-inclusive language from our vocabulary to reflect our values and represent our global ecosystem.
Arm is working actively with our partners, standards bodies, and the wider ecosystem to adopt a consistent approach to the use of inclusive language and to eradicate and replace offensive terms. We recognise that this will take time. This course has been updated to replace references to non-inclusive language. We recognise that some of you will be accustomed to using the previous terms and may not immediately recognise their replacements. Please refer to the following examples:
- When introducing the AMBA AXI Protocols, we will use the term ‘Manager’ instead of ‘Master’ and ‘Subordinate’ instead of ‘Slave’.
- When introducing the architecture, we will use the term ‘Requester’ instead of ‘Master’ and ‘Completer’ instead of ‘Slave’.
This course may still contain other references to non-inclusive language; it will be updated with newer terms as those terms are agreed and ratified with the wider community.
Contact us at [email protected] with questions or comments about this course. You can also report non-inclusive and offensive terminology usage in Arm content at [email protected].