From b366c6bcba58efeda5725e05a4381050c0bf2d50 Mon Sep 17 00:00:00 2001 From: Michal Czyz Date: Tue, 28 Mar 2023 12:33:31 +0200 Subject: [PATCH 1/4] Add push test --- .github/workflows/verible-push.yml | 16 ++++++++++++++++ rtl/module.sv | 10 ++++++++++ 2 files changed, 26 insertions(+) create mode 100644 .github/workflows/verible-push.yml create mode 100644 rtl/module.sv diff --git a/.github/workflows/verible-push.yml b/.github/workflows/verible-push.yml new file mode 100644 index 00000000..b6e1462f --- /dev/null +++ b/.github/workflows/verible-push.yml @@ -0,0 +1,16 @@ +name: verible-push + +on: + [push] + +#c + +jobs: + verible-format: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@master + - uses: antmicro/verible-formatter-action@mczyz/error-presentation + with: + github_token: ${{ secrets.GITHUB_TOKEN }} + fail_on_formatting_suggestions: ${{ github.event_name != 'pull_request' }} diff --git a/rtl/module.sv b/rtl/module.sv new file mode 100644 index 00000000..1e7f5c0c --- /dev/null +++ b/rtl/module.sv @@ -0,0 +1,10 @@ + +module hello(input clk); + +initial + +begin: proc_he + $display("helllo"); +end + +endmodule From e644204ecb879dd6669e822292a590c02cbc56b5 Mon Sep 17 00:00:00 2001 From: Michal Czyz Date: Tue, 28 Mar 2023 11:44:55 +0200 Subject: [PATCH 2/4] Add module --- module.sv | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 module.sv diff --git a/module.sv b/module.sv new file mode 100644 index 00000000..1e7f5c0c --- /dev/null +++ b/module.sv @@ -0,0 +1,10 @@ + +module hello(input clk); + +initial + +begin: proc_he + $display("helllo"); +end + +endmodule From 0f5d91a9fc025589cbd8c9f114ba1f8fb1e83e9d Mon Sep 17 00:00:00 2001 From: Michal Czyz Date: Thu, 30 Mar 2023 15:54:01 +0200 Subject: [PATCH 3/4] Add hello module which is properly formatted --- hello.sv | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 hello.sv diff --git a/hello.sv b/hello.sv new file mode 100644 index 00000000..8cd24a5d --- /dev/null +++ b/hello.sv @@ -0,0 +1,10 @@ + +module hello ( + input clk +); + + initial begin : proc_he + $display("helllo"); + end + +endmodule From 5b052686d1f6e9b1158b3c58bcd3ff9f61cecb20 Mon Sep 17 00:00:00 2001 From: Michal Czyz Date: Tue, 4 Apr 2023 15:28:15 +0200 Subject: [PATCH 4/4] Make sure pr annotate works --- module.sv | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/module.sv b/module.sv index 1e7f5c0c..5fcfec1d 100644 --- a/module.sv +++ b/module.sv @@ -7,4 +7,9 @@ begin: proc_he $display("helllo"); end +always +begin: proc_clk + #(20) $display("tic"); +end + endmodule