From 471ac08544879a9163dcf3d30ea88036a2697aa2 Mon Sep 17 00:00:00 2001 From: Jorge Marques Date: Thu, 12 Sep 2024 18:19:46 -0300 Subject: [PATCH] axi_ad9361: Fixup LVDS RX_FRAME (#916) The rx_error_r* registers were miss-implemented, they intended to be the negate of valid {rx_frame, rx_frame_s} but only took rx_frame_s into check. As an error for the current adc_data is also improper, because a 2Rx takes 4 clock cycles to fulfil, while {rx_frame, rx_frame_s} only look back 2 clock cycles. Change the logic to have rx_error solely as a link stable signal. Relevant information: AD9361 operates in DDR. AD9361 operating register values according to drivers: reg 0x010 value 0xC8[2] -> Rx Frame Pulse Mode : 50% duty cycle reg 0x011 value 0x00[2] -> Invert Rx Frame : don't rx_r1_mode is ADC_COMMON 0x0011[2] R1_MODE with: clear: 2 channels set: 1 channel Signed-off-by: Jorge Marques --- library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v index 89b8854d30..6002396bbb 100644 --- a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v +++ b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -166,6 +166,7 @@ module axi_ad9361_lvds_if #( wire [ 5:0] rx_data_0_s; wire [ 1:0] rx_frame_s; wire locked_s; + wire rx_error; // drp interface signals @@ -214,16 +215,9 @@ module axi_ad9361_lvds_if #( end // frame check + assign rx_error = ^rx_frame; // delineation - reg rx_error_r1 = 'd0; - reg rx_error_r2 = 'd0; - - always @(posedge l_clk) begin - rx_error_r1 <= ~((rx_frame_s == 4'b1100) || (rx_frame_s == 4'b0011)); - rx_error_r2 <= ~((rx_frame_s == 4'b1111) || (rx_frame_s == 4'b1100) || - (rx_frame_s == 4'b0000) || (rx_frame_s == 4'b0011)); - end always @(posedge l_clk) begin case ({rx_r1_mode, rx_frame_s, rx_frame}) @@ -252,11 +246,7 @@ module axi_ad9361_lvds_if #( // adc-status always @(posedge l_clk) begin - if (adc_r1_mode == 1'b1) begin - adc_status_p <= ~rx_error_r1 & rx_locked; - end else begin - adc_status_p <= ~rx_error_r2 & rx_locked; - end + adc_status_p <= ~rx_error & rx_locked; end // transfer to common clock