From 828c2952d2431ebc3c6dea69ee56990d7d3cb6d5 Mon Sep 17 00:00:00 2001 From: Laez Barbosa Date: Tue, 29 Oct 2024 19:08:07 -0300 Subject: [PATCH] axi_ad5766: add interconnect control Signed-off-by: Laez Barbosa --- library/axi_ad5766/Makefile | 2 ++ library/axi_ad5766/axi_ad5766.v | 11 +++++++++-- library/axi_ad5766/axi_ad5766_ip.tcl | 10 +++++++++- projects/ad5766_sdz/common/ad5766_bd.tcl | 1 + 4 files changed, 21 insertions(+), 3 deletions(-) diff --git a/library/axi_ad5766/Makefile b/library/axi_ad5766/Makefile index c38a5167fc..1256a17402 100644 --- a/library/axi_ad5766/Makefile +++ b/library/axi_ad5766/Makefile @@ -22,6 +22,8 @@ XILINX_DEPS += ../spi_engine/interfaces/spi_engine_ctrl.xml XILINX_DEPS += ../spi_engine/interfaces/spi_engine_ctrl_rtl.xml XILINX_DEPS += ../spi_engine/interfaces/spi_engine_offload_ctrl.xml XILINX_DEPS += ../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml +XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_interconnect_ctrl.xml +XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_interconnect_ctrl_rtl.xml XILINX_LIB_DEPS += util_cdc diff --git a/library/axi_ad5766/axi_ad5766.v b/library/axi_ad5766/axi_ad5766.v index 244cbabdc1..ea8b1c67ab 100644 --- a/library/axi_ad5766/axi_ad5766.v +++ b/library/axi_ad5766/axi_ad5766.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -112,7 +112,11 @@ module axi_ad5766 #( input ctrl_enable, output ctrl_enabled, - input ctrl_mem_reset + input ctrl_mem_reset, + + // SPI engine interconnect interface + + output interconnect_dir ); // internal wires @@ -186,6 +190,8 @@ module axi_ad5766 #( wire ctrl_is_enabled; reg spi_enabled = 1'b0; + assign interconnect_dir = spi_enabled; + always @(posedge ctrl_clk) begin if (ctrl_enable == 1'b1) begin ctrl_do_enable <= 1'b1; @@ -231,6 +237,7 @@ module axi_ad5766 #( assign spi_enable_s = ctrl_enable; assign ctrl_enabled = spi_enable_s | spi_active; assign spi_mem_reset_s = ctrl_mem_reset; + assign interconnect_dir = ctrl_enabled; end endgenerate assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1; diff --git a/library/axi_ad5766/axi_ad5766_ip.tcl b/library/axi_ad5766/axi_ad5766_ip.tcl index ad75aec7f7..6864db986c 100644 --- a/library/axi_ad5766/axi_ad5766_ip.tcl +++ b/library/axi_ad5766/axi_ad5766_ip.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -62,9 +62,17 @@ adi_add_bus "spi_engine_offload_ctrl" "slave" \ { "status_sync_data" "sync_data"} \ } +adi_add_bus "m_interconnect_ctrl" "master" \ + "analog.com:interface:spi_engine_interconnect_ctrl_rtl:1.0" \ + "analog.com:interface:spi_engine_interconnect_ctrl:1.0" \ + { \ + {"interconnect_dir" "interconnect_dir"} \ + } + adi_add_bus_clock "ctrl_clk" "spi_engine_offload_ctrl" adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn" adi_add_bus_clock "dma_clk" "dma_fifo_tx" +adi_add_bus_clock "spi_clk" "m_interconnect_ctrl" "resetn" adi_add_auto_fpga_spec_params ipx::create_xgui_files [ipx::current_core] diff --git a/projects/ad5766_sdz/common/ad5766_bd.tcl b/projects/ad5766_sdz/common/ad5766_bd.tcl index ecdb027d6c..9030c901d1 100644 --- a/projects/ad5766_sdz/common/ad5766_bd.tcl +++ b/projects/ad5766_sdz/common/ad5766_bd.tcl @@ -31,6 +31,7 @@ current_bd_instance /spi ad_connect axi/spi_engine_offload_ctrl0 axi_ad5766/spi_engine_offload_ctrl ad_connect axi/spi_engine_ctrl interconnect/s0_ctrl ad_connect axi_ad5766/spi_engine_ctrl interconnect/s1_ctrl + ad_connect axi_ad5766/m_interconnect_ctrl interconnect/s_interconnect_ctrl ad_connect interconnect/m_ctrl execution/ctrl ad_connect m_spi execution/spi ad_connect dma_data axi_ad5766/dma_data