From 68b65bc42ffd8b3964dfae920599d2ec32947b91 Mon Sep 17 00:00:00 2001
From: Uri Shaked <uri@urishaked.com>
Date: Mon, 21 Oct 2024 16:54:56 +0300
Subject: [PATCH] fix: hardening fails due to missing power pins in macro
 netlists

---
 .github/workflows/gds.yaml           | 2 +-
 .gitignore                           | 1 +
 tt                                   | 2 +-
 verilog/includes/includes.gl.mux_top | 8 ++++----
 4 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/.github/workflows/gds.yaml b/.github/workflows/gds.yaml
index 3770a9f..88e0d2f 100644
--- a/.github/workflows/gds.yaml
+++ b/.github/workflows/gds.yaml
@@ -127,7 +127,7 @@ jobs:
           EXPECTED_REPO: ${{ github.repository }}
         run: |
           # temporary workaround for missing bits in pad_raw:
-          sed -i 's/inout \[61:0\] pad_raw/inout [63:0] pad_raw/' efabless/verilog/gl/tt_ihp_wrapper.v
+          sed -i 's/inout \[61:0\] pad_raw/inout [63:0] pad_raw/' efabless/verilog/gl/tt_ihp_wrapper.nl.v
 
           make clean test_mux_gl
           # make will return success even if the test fails, so check for failure in the results.xml
diff --git a/.gitignore b/.gitignore
index 75c120b..5679d1d 100644
--- a/.gitignore
+++ b/.gitignore
@@ -12,6 +12,7 @@ shuttle_index.md
 efabless/gds/*.gds
 efabless/gds/*.lef
 efabless/verilog/gl/tt_ihp_wrapper.v
+efabless/verilog/gl/tt_ihp_wrapper.nl.v
 efabless/verilog/rtl/user_defines.v
 efabless/README.md
 
diff --git a/tt b/tt
index 4eb3789..f3e3861 160000
--- a/tt
+++ b/tt
@@ -1 +1 @@
-Subproject commit 4eb37893cbc4b6ba862712ed81a3a37ea522dc66
+Subproject commit f3e3861176815a7a9e398396cf6a4dc0e446db75
diff --git a/verilog/includes/includes.gl.mux_top b/verilog/includes/includes.gl.mux_top
index 51cc8e1..abdab6c 100644
--- a/verilog/includes/includes.gl.mux_top
+++ b/verilog/includes/includes.gl.mux_top
@@ -1,5 +1,5 @@
--v $(EFABLESS_SUBMISSION)/verilog/gl/tt_ihp_wrapper.v
--v $(TT_GL_VERILOG)/tt_ctrl.v
--v $(TT_GL_VERILOG)/tt_mux.v
--v $(TT_GL_VERILOG)/tt_um_chip_rom.v
+-v $(EFABLESS_SUBMISSION)/verilog/gl/tt_ihp_wrapper.nl.v
+-v $(TT_GL_VERILOG)/tt_ctrl.nl.v
+-v $(TT_GL_VERILOG)/tt_mux.nl.v
+-v $(TT_GL_VERILOG)/tt_um_chip_rom.nl.v
 -v $(USER_PROJECT_VERILOG)/../projects/tt_um_factory_test/tt_um_factory_test.v