diff --git a/.github/workflows/gds.yaml b/.github/workflows/gds.yaml
index 2f489be..3770a9f 100644
--- a/.github/workflows/gds.yaml
+++ b/.github/workflows/gds.yaml
@@ -126,6 +126,9 @@ jobs:
         env:
           EXPECTED_REPO: ${{ github.repository }}
         run: |
+          # temporary workaround for missing bits in pad_raw:
+          sed -i 's/inout \[61:0\] pad_raw/inout [63:0] pad_raw/' efabless/verilog/gl/tt_ihp_wrapper.v
+
           make clean test_mux_gl
           # make will return success even if the test fails, so check for failure in the results.xml
           ! grep failure results.xml
diff --git a/.gitignore b/.gitignore
index 150936b..75c120b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -11,8 +11,7 @@ shuttle_index.md
 # Auto generated eFabless submission files:
 efabless/gds/*.gds
 efabless/gds/*.lef
-efabless/verilog/gl/user_project_wrapper.v
-efabless/verilog/gl/openframe_project_wrapper.v
+efabless/verilog/gl/tt_ihp_wrapper.v
 efabless/verilog/rtl/user_defines.v
 efabless/README.md
 
diff --git a/modules.test.yaml b/modules.test.yaml
index dd921ed..39fa647 100644
--- a/modules.test.yaml
+++ b/modules.test.yaml
@@ -1,9 +1,9 @@
 modules:
   - name: "chip_rom"
-    x: 7
-    y: 15
+    x: 5
+    y: 9
     pg_vdd: false
   - name: "factory_test"
-    x: 7
-    y: 14
+    x: 5
+    y: 8
     pg_vdd: false
diff --git a/tt b/tt
index a328dbb..4eb3789 160000
--- a/tt
+++ b/tt
@@ -1 +1 @@
-Subproject commit a328dbb7484e0760d6df260ccf727e81cc5a3e32
+Subproject commit 4eb37893cbc4b6ba862712ed81a3a37ea522dc66
diff --git a/tt-multiplexer b/tt-multiplexer
index 636fa31..ba69b2f 160000
--- a/tt-multiplexer
+++ b/tt-multiplexer
@@ -1 +1 @@
-Subproject commit 636fa3106c84cdad60cdcd028bb3da85672fc444
+Subproject commit ba69b2f87ea53c6d89256db11840d41431563931
diff --git a/verilog/dv/mux/Makefile b/verilog/dv/mux/Makefile
index 06f2dda..d726f77 100644
--- a/verilog/dv/mux/Makefile
+++ b/verilog/dv/mux/Makefile
@@ -13,11 +13,10 @@ export EFABLESS_SUBMISSION = $(abspath ../../../efabless/)
 export TT_GL_VERILOG := $(abspath ../../../tt-multiplexer/ol2/tt_top/verilog/)
 
 SIM           ?= icarus
-WAVES         ?= no
+WAVES         ?= yes
 TOPLEVEL      ?= test_mux_tb
 MODULE        ?= test_mux
 TOPLEVEL_LANG ?= verilog
-COMPILE_ARGS  += -DMPRJ_IO_PADS=44
 COMPILE_ARGS  += -DSIM_$(shell echo $(SIM) | tr a-z A-Z)=1
 COMPILE_ARGS  += -DROM_VMEM_PATH=\"../../../tt/rom/rom.vmem\"
 
@@ -50,16 +49,16 @@ ifeq ($(GATES),yes)
   COMPILE_ARGS    += -DGL_TEST
   COMPILE_ARGS    += -DFUNCTIONAL
   COMPILE_ARGS    += -DSIM
-  COMPILE_ARGS    += -DUNIT_DELAY=\#1
-  COMPILE_ARGS    += -DUSE_POWER_PINS
-  VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
-  VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
+  VERILOG_SOURCES += $(PDK_ROOT)/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v
   SIM_BUILD       := sim_build_gates
 else
+  COMPILE_ARGS    += -DRTL_TESTBENCH
   COMPILE_ARGS    += -f $(abspath ../../includes/includes.rtl.caravel_user_project) -I $(abspath ../../rtl/tt-multiplexer/rtl)
-  VERILOG_SOURCES += $(abspath ../../rtl/fast/sky130_fd_sc_hd_fast.v)
 endif
 
+# IO cell library is relevent for both RTL / GL sims
+VERILOG_SOURCES += $(PDK_ROOT)/ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v
+
 # Standard sources
 VERILOG_SOURCES += $(abspath test_mux_tb.v)
 
@@ -73,9 +72,7 @@ include $(shell cocotb-config --makefiles)/Makefile.sim
 # ==============================================================================
 
 .PHONY: test_mux
-test_mux: TESTCASE=test_mux,test_rom
 test_mux: $(COCOTB_RESULTS_FILE)
 
 .PHONY: test_mux_gl
-test_mux_gl: TESTCASE=test_mux,test_rom
 test_mux_gl: $(COCOTB_RESULTS_FILE)
diff --git a/verilog/dv/mux/test_mux.py b/verilog/dv/mux/test_mux.py
index b6adf68..c41f996 100644
--- a/verilog/dv/mux/test_mux.py
+++ b/verilog/dv/mux/test_mux.py
@@ -1,6 +1,7 @@
 import cocotb
+from cocotb.types import LogicArray
 from cocotb.clock import Clock
-from cocotb.triggers import ClockCycles
+from cocotb.triggers import ClockCycles, Timer
 import re
 import os
 import binascii
@@ -8,40 +9,36 @@
 
 async def enable_design(dut, mux_addr):
     dut._log.info(f"enabling design at mux address {mux_addr}")
-
-    # reset the controller
-    dut.ctrl_sel_inc.value = 0
-    dut.ctrl_sel_rst_n.value = 0
     dut.ctrl_ena.value = 0
-    await ClockCycles(dut.clk, 5)
+    dut.ctrl_sel_rst_n.value = 0
+    dut.ctrl_sel_inc.value = 0
+    await Timer(100, units="ns")
     dut.ctrl_sel_rst_n.value = 1
-    await ClockCycles(dut.clk, 5)
-
-    # send the number of pulses required
-    for c in range(mux_addr):
+    await Timer(100, units="ns")
+    for i in range(mux_addr):
         dut.ctrl_sel_inc.value = 1
-        await ClockCycles(dut.clk, 1)
+        await Timer(100, units="ns")
         dut.ctrl_sel_inc.value = 0
-        await ClockCycles(dut.clk, 1)
-
+        await Timer(100, units="ns")
     dut.ctrl_ena.value = 1
+    await Timer(100, units="ns")
 
 
 @cocotb.test()
-async def test_mux(dut):
+async def test_factory_test(dut):
     clock = Clock(dut.clk, 100, units="ns")  # 10 MHz
     cocotb.start_soon(clock.start())
 
-    dut.uio_in.value = 0
+    dut.uio_in.value = LogicArray("Z" * 8)
     dut.ui_in.value = 0
     # select test design
-    dut.reset_n.value = 0
+    dut.rst_n.value = 0
     await enable_design(dut, 1)
 
     # with bit 0 of ui_in set to 0, module will copy inputs to outputs
     dut.ui_in.value = 0b0
     await ClockCycles(dut.clk, 5)  # wait until the wait state config is read
-    dut.reset_n.value = 1
+    dut.rst_n.value = 1
 
     dut._log.info("test loopback")
     for i in range(256):
@@ -50,12 +47,13 @@ async def test_mux(dut):
         assert dut.uo_out.value == i
 
     # with bit 0 of ui_in set to 1, module will enable bidirectional outputs and put a counter on both output and bidirectional output
+    dut.uio_in.value = LogicArray("Z" * 8)
     dut.ui_in.value = 0b1
 
     # reset it
-    dut.reset_n.value = 0
+    dut.rst_n.value = 0
     await ClockCycles(dut.clk, 5)  # wait until the wait state config is read
-    dut.reset_n.value = 1
+    dut.rst_n.value = 1
     await ClockCycles(dut.clk, 2)  # sync
 
     dut._log.info("test counter")
@@ -70,10 +68,10 @@ async def test_rom(dut):
     clock = Clock(dut.clk, 100, units="ns")  # 10 MHz
     cocotb.start_soon(clock.start())
 
-    dut.uio_in.value = 0
+    dut.uio_in.value = LogicArray("Z" * 8)
     dut.ui_in.value = 0
     # select ROM design
-    dut.reset_n.value = 0
+    dut.rst_n.value = 0
     await enable_design(dut, 0)
 
     dut._log.info("test ROM")
@@ -81,7 +79,7 @@ async def test_rom(dut):
     for byte_idx in range(len(buf)):
         dut.ui_in.value = byte_idx
         await ClockCycles(dut.clk, 1)
-        buf[byte_idx] = dut.uo_out.value
+        buf[byte_idx] = dut.uo_out.value.integer
 
     text = buf[32:128].rstrip(b"\0").decode("ascii")
     items = {}
diff --git a/verilog/dv/mux/test_mux_tb.v b/verilog/dv/mux/test_mux_tb.v
index 7a24a84..eac9fbe 100644
--- a/verilog/dv/mux/test_mux_tb.v
+++ b/verilog/dv/mux/test_mux_tb.v
@@ -3,11 +3,11 @@
 module test_mux_tb (
     // the user module's interface
     input wire clk,
-    input wire reset_n,
+    input wire rst_n,
     input wire [7:0] ui_in,
     output wire [7:0] uo_out,
-    input wire [7:0] uio_in,  // IOs: Input path
-    output wire [7:0] uio_out,  // IOs: Output path
+    inout wire [7:0] uio_in,
+    output wire [7:0] uio_out,
 
     // control interface
     input wire ctrl_sel_rst_n,
@@ -15,24 +15,6 @@ module test_mux_tb (
     input wire ctrl_ena
 );
 
-  // signals for openframe_project_wrapper
-  reg  [`MPRJ_IO_PADS-1:0] io_in;
-  wire [`MPRJ_IO_PADS-1:0] io_out;
-  wire [`MPRJ_IO_PADS-1:0] io_oeb;
-
-  assign io_in[23:16] = uio_in[7:0];
-  assign uio_out[7:0] = io_out[23:16];
-
-  assign io_in[14]    = clk;
-  assign io_in[15]    = reset_n;
-  assign io_in[13]    = ui_in[7];
-  assign io_in[6:0]   = ui_in[6:0];
-  assign uo_out[7:0]  = io_out[31:24];
-
-  assign io_in[40]    = ctrl_sel_rst_n;
-  assign io_in[39]    = ctrl_sel_inc;
-  assign io_in[38]    = ctrl_ena;
-
 `ifdef SIM_ICARUS
   initial begin
     string f_name;
@@ -47,36 +29,17 @@ module test_mux_tb (
   end
 `endif
 
-  wire [43:0] gpio_in;
-  wire [43:0] gpio_out;
-  wire [43:0] gpio_oeb;
-  wire [43:0] gpio_inp_dis;
-  wire [43:0] gpio_dm2;
-  wire [43:0] gpio_dm1;
-  wire [43:0] gpio_dm0;
-
-  assign gpio_in = io_in;
-  assign io_out  = gpio_out & ~gpio_oeb & gpio_dm2 & gpio_dm1;
-  assign io_oeb  = gpio_oeb;
-  wire [43:0] inp_ena = (gpio_dm0 | gpio_dm1 | gpio_dm2) & ~gpio_inp_dis;
-
-  wire vccd1 = 1'b1;
-  wire vssd1 = 1'b0;
-
-  openframe_project_wrapper user_project_wrapper (
-`ifdef GL_TEST
-      .vccd1             (vccd1),
-      .vssd1             (vssd1),
-`endif
-      .gpio_loopback_zero({44{1'b0}}),
-      .gpio_loopback_one ({44{1'b1}}),
-      .gpio_in           (gpio_in & inp_ena),
-      .gpio_out          (gpio_out),
-      .gpio_oeb          (gpio_oeb),
-      .gpio_inp_dis      (gpio_inp_dis),
-      .gpio_dm2          (gpio_dm2),
-      .gpio_dm1          (gpio_dm1),
-      .gpio_dm0          (gpio_dm0)
-  );
+  wire [63:0] pad_raw;
+  assign pad_raw[0] = ctrl_ena;
+  assign pad_raw[1] = ctrl_sel_inc;
+  assign pad_raw[2] = ctrl_sel_rst_n;
+  assign uo_out = pad_raw[15:8];
+  assign pad_raw[39:32] = uio_in;
+  assign uio_out = pad_raw[39:32];
+  assign pad_raw[47:40] = ui_in;
+  assign pad_raw[48] = rst_n;
+  assign pad_raw[49] = clk;
+
+  tt_ihp_wrapper tt (.pad_raw(pad_raw));
 
 endmodule
diff --git a/verilog/includes/includes.gl.mux_top b/verilog/includes/includes.gl.mux_top
index a437bf9..51cc8e1 100644
--- a/verilog/includes/includes.gl.mux_top
+++ b/verilog/includes/includes.gl.mux_top
@@ -1,9 +1,5 @@
--v $(EFABLESS_SUBMISSION)/verilog/gl/openframe_project_wrapper.v
+-v $(EFABLESS_SUBMISSION)/verilog/gl/tt_ihp_wrapper.v
 -v $(TT_GL_VERILOG)/tt_ctrl.v
 -v $(TT_GL_VERILOG)/tt_mux.v
 -v $(TT_GL_VERILOG)/tt_um_chip_rom.v
--v $(TT_GL_VERILOG)/tt_pg_1v8_1.v
--v $(TT_GL_VERILOG)/tt_pg_1v8_2.v
--v $(TT_GL_VERILOG)/tt_pg_1v8_4.v
--v $(TT_GL_VERILOG)/tt_asw_3v3.v
 -v $(USER_PROJECT_VERILOG)/../projects/tt_um_factory_test/tt_um_factory_test.v
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 9d5cd36..ea2c3bb 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,7 +1,7 @@
--v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/ol2/tt_top/openframe_project_wrapper.v
+-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/ol2/tt_top/tt_ihp_wrapper.v
 -v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/tt_top.v
 -v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/tt_ctrl.v
--v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/tt_gpio.v
+-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/tt_ihp_gpio.v
 -v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/tt_mux.v
 -v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/tt_user_module.v
 -v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_buf.v