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naxriscv boot on tang_primer 20k #64
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Hi, NaxRiscv is likely too big for it. Mainly because it assumes that the FPGA support distributed ram (lut ram, meaning 1w port, 1r asyncronous port) |
@54o8: Can you share your build command? We could do some test here with @trabucayre that also has the board. Is it working with other CPU (ex with --cpu-type=vexriscv?) Since it seems there is an issue on the UART TX/RX pins. |
@54o8: It could be worth testing with litex-hub/litex-boards@17a0152 and upstream LiteX/LiteDRAM. |
@enjoy-digital The command I use is as follows by the way,How do you solve the DDR problem of the gowin138k board? As far as I know, gowin doesn't give a DDRPHY for 138k, similar to GW2DDRPHY for 20k boards, so does that mean I have to write my own DDRPHY when I want to use DDR on 138k board? or as in target.sipeed_tang_mega_138k.py using external sdram to solve this problem |
So, there are different issues. For NaxRiscv, from what I undersand, it has never been tested on a Gowin FPGA, so it would be interesting to carefully check the synthesis logs and also to make sure it passes timings. You could eventually try to reduce For the DDR3, it's not yet supported with LiteX/LiteDRAM, but we are working on it (ex: enjoy-digital/litedram#351). For the SDRAM, with upstream code, it should be working with |
Yes right. Also on thing which will help a lot with the size of the design is to add the following on the litex args: (not i do not often use mmu=false) |
@enjoy-digital |
please use |
DDR3 for tang Mega it's currently not working. I try to find why but gowin doesn't provides any real/effective documentations so it's not really easy. |
Thanks for contributing to this, bset wish! |
Hi, It seems more like some memory issue. 0x5c2ff isn't a valid instruction. Can you check the linux binary,? what is at 0xC0053200 ? |
When I tried to build the soc for naxriscv on tang_primer_20k, there was an error. Do you have any suggestions?
I used the following command
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