opae-sdk-1.1.0

Open Programmable Acceleration Engine (OPAE )is a software framework for managing and accessing programmable accelerators (FPGAs). Its main parts are:

• OPAE Software Development Kit (OPAE SDK),

• OPAE Linux driver for Intel(R) Xeon(R) CPU with Integrated FPGAs and Intel(R) PAC with Arria(R) 10 GX FPGA

• Basic Building Block (BBB) library for accelerating AFU
  development (not part of this release, but pre-release code is
  available on GitHub: https://github.com/OPAE/intel-fpga-bbb

OPAE is under active development to extend to more hardware platforms, as well as to build up the software stack with additional abstractions to enable more software developers.

OPAE SDK is a collection of libraries and tools to facilitate the development of software applications and accelerators using OPAE. It provides a library implementing the OPAE C API for presenting a streamlined and easy-to-use interface for software applications to discover, access, and manage FPGA devices and accelerators using the OPAE software stack. The OPAE SDK also includes the AFU Simulation Environment (ASE) for end-to-end simulation of accelerator RTL together with software applications using the OPAE C API.

OPAE's goal is to accelerate FPGA adoption. It is a community effort to simplify the development and deployment of FPGA applications, so we explicitly welcome discussions and contributions! The OPAE SDK source, unless otherwise noted, is released under a BSD 3-clause license.

More information about OPAE can be found
at http://01.org/OPAE.

Open Programmable Acceleration Engine (OPAE) 1.1.0 Release Notes

This document provides the Release Notes for the Open Programmable
Acceleration Engine (OPAE) 1.1.0 release.

System Compatibility

• Hardware: tightly coupled FPGA products and programmable FPGA
  acceleration cards for Intel(R) Xeon(R) processors (to be released):

  • Intel(R) PAC with Arria(R) 10 GX FPGA (PCI ID: 0x09c4) FIM version 1.0.3 (1.0 Production)
  • Intel(R) Xeon with Integrated FPGA (PCI ID: 0xbcc0) FIM version 6.4.0

• Operating System: tested on Red Hat Enterprise Linux 7.3, Ubuntu 16.04, SUSE SLE 12 SP3 and CentOS
  7.4, with Linux kernels 3.10 through 4.7

Major Changes from 1.0.0 to 1.1.0

• Updated command line options for OPAE tools for a consistent user interface
• Added two new language bindings
  • A C++ Core API that is interoperable with the OPAE C API
  • A Python API which wraps the C++ Core API object model
• Disabled documentation generation by default in make to speed up development
• Implemented CMake build-chain for ASE
• Organized samples directory
• Increased test coverage
• Added Error API
• Added SUSE support
• Cleaned up dead/legacy code
• Various bug fixes

Notes / Known Issues

• Seldom in stress tests, kernel panic may be encountered in kernel version 3.10. Preliminary debug information seems to indicate it may be related to hugepage support in the Linux kernel.

• Memory leak detected by Valgrind points to global data structures used by enumeration routines. This is due to token_cleanup() function not being called when the library is being unloaded. This does not impact memory performance and will be addressed in next release.

• A different OPN is used in the design examples

  The Intel Quartus Prime Pro Edition license uses a design example

  OPN of 10AX115N3F40E2SG, instead of the Intel PAC with Intel Arria
  10 GX FPGA OPN of 10AX115N2F40E2LG. This difference does not impact
  your design.

• PCIe directed speed changes are not supported

  Only automatic down-training at boot time is supported

• Virtual Function (VF) may fail to attach or detach when using the
  Linux Red Hat 3.10 kernel

  This is a known issue with qemu/kvm and libvirt. Refer to the Red
  Hat website for more information about this issue.

• The Intel FPGA Dynamic Profiler Tool for OpenCL GUI reports
  frequency and bandwidth incorrectly

  This issue will be resolved in a future version of the Intel
  Acceleration Stack.

• Partial reconfiguration with SR-IOV

  If using OPAE in a virtualized environment with SR-IOV enabled, we recommend disabling SR-IOV before performing partial reconfiguration. See "Partial Reconfiguration" in the "OPAE Intel FPGA Linux Device Driver Architecture" document for more information

• fpgaAssignToInterface() and fpgaReleaseFromInterface() not supported

  The OPAE C API provides functions to assign individual AFCs to host interfaces (i.e. a virtual or physical function). Due to the internal implementation of fpga_token, these functions are not yet supported. Instead, we provide a simplified call fpgaAssignPortToInterface() that can assign a port by number to either the physical function (PF) or virtual function (VF). This function will eventually be replaced by the more generic implementation of fpgaAssignToInterface() and fpgaReleaseFromInterface() in a future release.

• AP6 condition may prevent clearing of port errors

  If the system encounters an AP6 condition (exceeded power or temperature threshold), it will report a port error. These errors can only be cleared (e.g. using fpgainfo) after the AP6 condition has been removed.

• Driver may not display explicit incompatibility message if loaded on mismatched FIM version

  When trying to insert the Linux kernel driver modules while an FPGA platform with an unsupported FIM version is present in the system, the driver may fail to load and/or fail to print an explicit incompatibility warning message in the system log. Please make sure to use the driver only with a compatible FIM.

• ASE: Multiple ModelSim simulator instances may crash when run on the same host

  When trying to run multiple instances of the ModelSim simulator on a single system, the simulator may crash. Only run one instance of ModelSim at the same time per system.

• The current Python distributions included in this release are

  • opae.fpga-1.1.0.tar.gz - The source files for building the Python bindings. This requires OPAE development package to be installed prior to building
  • opae.fpga-1.1.0-cp27-cp27mu-linux_x86_64.whl - A binary package built with Python 2.7
  • opae.fpga-1.1.0-cp34-cp34m-linux_x86_64.whl - A binary package built with Python 3.4
  • opae.fpga-1.1.0-cp35-cp35m-linux_x86_64.whl - A binary package built with Python 3.5

opae-sdk-1.0.0

The Open Programmable Acceleration Engine is a software framework for managing and accessing programmable accelerators (FPGAs). Its main parts are:

• The OPAE Software Development Kit (OPAE SDK),

• the OPAE Linux driver for Intel(R) Xeon(R) CPU with Integrated FPGAs and Intel(R) PAC with Arria(R) 10 GX FPGA

• the Basic Building Block (BBB) library for accelerating AFU
  development (not part of this release, but pre-release code is
  available on GitHub: [https://github.com/OPAE/intel-fpga-bbb]

OPAE is under active development to extend to more hardware platforms, as well as to build up the software stack with additional abstractions to enable more software developers.

The OPAE SDK is a collection of libraries and tools to facilitate the development of software applications and accelerators using OPAE. It provides a library implementing the OPAE C API for presenting a streamlined and easy-to-use interface for software applications to discover, access, and manage FPGA devices and accelerators using the OPAE software stack. The OPAE SDK also includes the AFU Simulation Environment (ASE) for end-to-end simulation of accelerator RTL together with software applications using the OPAE C API.

OPAE's goal is to accelerate FPGA adoption. It is a community effort to simplify the development and deployment of FPGA applications, so we explicitly welcome discussions and contributions! The OPAE SDK source, unless otherwise noted, is released under a BSD 3-clause license.

More information about OPAE can be found
at http://01.org/OPAE.

Open Programmable Acceleration Engine (OPAE) 1.0.0 Release Notes

This document provides the Release Notes for the Open Programmable
Acceleration Engine (OPAE) 1.0.0 release.

System Compatibility

• Hardware: tightly coupled FPGA products and programmable FPGA
  acceleration cards for Intel(R) Xeon(R) processors (to be released):

  • Intel(R) PAC with Arria(R) 10 GX FPGA (PCI ID: 0x09c4) FIM version 1.0.3 (1.0 Production)
  • Intel(R) Xeon with Integrated FPGA (PCI ID: 0xbcc0) FIM version 6.4.0

• Operating System: tested on Red Hat Enterprise Linux 7.3, and CentOS
  7.4, with Linux kernels 3.10 through 4.7

Major Changes from 0.13.1 to 1.0.0

• Added API functions to retrieve libopae-c version information
• Added support for vendor ID and device ID properties
• MMIO mappings are now automatically freed on resource close
• Reduced minimum supported clock frequency to 25MHz
• Removed dependency on Boost
• Added support for building debian packages
• Building packages sets the default install location to /usr/local
• Improved error clearing flow in fpgainfo
• Added RAS support for discrete FPGA devices
• Improved test coverage
• Fixed "freq" option for bandwidth calculation in fpgadiag
• fpgadiag now reads pclock frequency from hardware
• Improved handling/generation of CCI-P FIFO signals in ASE by providing flexible clock and local memory
• Improved platform support in the platform database
• Enabling ASE platform support for tests
• Improved support for platform database in AFU JSON
• Updated documentation for build chain, packaging(DEB and RPM) and ASE
• Reorganized tools directory structure
• Code cleanup and improved error messages
• Various bug fixes

Notes / Known Issues

• A different OPN is used in the design examples

  The Intel Quartus Prime Pro Edition license uses a design example

  OPN of 10AX115N3F40E2SG, instead of the Intel PAC with Intel Arria
  10 GX FPGA OPN of 10AX115N2F40E2LG. This difference does not impact
  your design.

• PCIe directed speed changes are not supported

  Only automatic down-training at boot time is supported

• Virtual Function (VF) may fail to attach or detach when using the
  Linux Red Hat 3.10 kernel

  This is a known issue with qemu/kvm and libvirt. Refer to the Red
  Hat website for more information about this issue.

• The Intel FPGA Dynamic Profiler Tool for OpenCL GUI reports
  frequency and bandwidth incorrectly

  This issue will be resolved in a future version of the Intel
  Acceleration Stack.

• fpgainfo may raise a UnicodeEncodeError when the Python
  interpreter cannot determine what encoding to use

  This issue typically occurs when redirecting or piping output. The
  fpgabist tool calls fpgainfo and is also impacted.

  There are two workarounds for this issue:

  -- Set the PYTHONENCODING environment variable to UTF-8.

  -- Modify the fpgainfo script to force the use of UTF-8:

  • Add an import codecs statement at the top of the file with the
    other import statements.

  • Before the line that calls args.func(args), insert this comment and code line:

    # wrap stdout with the StreamWriter that does unicode sys.stdout = codecs.getwriter('UTF- 8')(sys.stdout)

• When simulating the hello_intr_afu sample code, the
  af2cp_sTxPort.c1.hdr.rsvd2[5:4] has a value of X

  This issue will be resolved in the Intel Acceleration Stack 1.1
  version.

• Partial reconfiguration with SR-IOV

  If using OPAE in a virtualized environment with SR-IOV enabled, we recommend disabling SR-IOV before performing partial reconfiguration. See "Partial Reconfiguration" in the "OPAE Intel FPGA Linux Device Driver Architecture" document for more information

• fpgaAssignToInterface() and fpgaReleaseFromInterface() not supported

  The OPAE C API provides functions to assign individual AFCs to host interfaces (i.e. a virtual or physical function). Due to the internal implementation of fpga_token, these functions are not yet supported. Instead, we provide a simplified call fpgaAssignPortToInterface() that can assign a port by number to either the physical function (PF) or virtual function (VF). This function will eventually be replaced by the more generic implementation of fpgaAssignToInterface() and fpgaReleaseFromInterface() in a future release.

• hssi_loopback tool help menu lists incorrect option for packet count

  The help menu indicates -p is the packet count, however the actual switch is -c.

• AP6 condition may prevent clearing of port errors

  If the system encounters an AP6 condition (exceeded power or temperature threshold), it will report a port error. These errors can only be cleared (e.g. using fpgainfo) after the AP6 condition has been removed.

• Driver may not display explicit incompatibility message if loaded on mismatched FIM version

  When trying to insert the Linux kernel driver modules while an FPGA platform with an unsupported FIM version is present in the system, the driver may fail to load and/or fail to print an explicit incompatibility warning message in the system log. Please make sure to use the driver only with a compatible FIM.

• ASE: Multiple ModelSim simulator instances may crash when run on the same host

  When trying to run multiple instances of the ModelSim simulator on a single system, the simulator may crash. Only run one instance of ModelSim at the same time per system.

opae-sdk-0.13.1

The Open Programmable Acceleration Engine is a software framework for managing and accessing programmable accelerators (FPGAs). Its main parts are:

• The OPAE Software Development Kit (OPAE SDK),

• the OPAE Linux driver for Intel(R) Xeon(R) CPU with FPGAs, and

• the Basic Building Block (BBB) library for accelerating AFU
  development (not part of this release, but pre-release code is
  available [on GitHub)[https://github.com/OPAE/intel-fpga-bbb\]

OPAE is under active development to extend to more hardware platforms, as well as to build up the software stack with additional abstractions to enable more software developers.

The OPAE SDK is a collection of libraries and tools to facilitate the development of software applications and accelerators using OPAE. It provides a library implementing the OPAE C API for presenting a streamlined and easy-to-use interface for software applications to discover, access, and manage FPGA devices and accelerators using the OPAE software stack. The OPAE SDK also includes the AFU Simulation Environment (ASE) for end-to-end simulation of accelerator RTL together with software applications using the OPAE C API.

OPAE's goal is to accelerate FPGA adoption. It is a community effort to simplify the development and deployment of FPGA applications, so we explicitly welcome discussions and contributions! The OPAE SDK source, unless otherwise noted, is released under a BSD 3-clause license.

More information about OPAE can be found
at [http://01.org/OPAE]{.underline}.

Open Programmable Acceleration Engine (OPAE) 0.13.1 Release Notes

This document provides the Release Notes for the Open Programmable
Acceleration Engine (OPAE) 0.13.1 release.

System Compatibility

• Hardware: tightly coupled FPGA products and programmable FPGA
  acceleration cards for Intel(R) Xeon(R) processors (to be released);
  Intel(R) PAC with Arria(R) 10 card

• Operating System: tested on Red Hat Enterprise Linux 7.4, and CentOS
  7.4, with Linux kernels 3.10 through 4.7

• Intel Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA (PCI ID: 0x09c4)
  FIM Version : 1.0.3 (1.0 Production)

Major Changes from 0.13.0 to 0.13.1

• Refactor fpga internals

  • Change object_ID to object_id to be more consistent with other property names

  • Rename `sysfs_resource` to `sysfs_node` class

  • Default log to /tmp + error handling. This changes fpgainfo to log to /tmp directory but also adds exception handling in case the log file can't be opened. If that happens, it will log to stderr

•  fpgabist:

  • Support identifying target card via "-b", "-d", and/or "-f" flags when multiple cards are present. If there is only one card on the system the tool will default to running on the only available fpga
  • Improve input parsing and output formatting

• Define usage of flags to work with vhdla on ModelSim(use "-F") and
  VCS(use "-f").

• Reduce amount of logging when interrupts are supported by hardware

• hssi: fix help message for `send` command

Notes / Known Issues

• A different OPN is used in the design examples

  The Intel Quartus Prime Pro Edition license uses a design example

  OPN of 10AX115N3F40E2SG, instead of the Intel PAC with Intel Arria
  10 GX FPGA OPN of 10AX115N2F40E2LG. This difference does not impact
  your design.

• PCIe directed speed changes are not supported

  Only automatic down-training at boot time is supported

• Virtual Function (VF) may fail to attach or detach when using the
  Linux Red Hat* 3.10 kernel
  
  This is a known issue with qemu/kvm and libvirt. Refer to the Red
  Hat* website for more information about this issue.

• The Intel FPGA Dynamic Profiler Tool for OpenCL* GUI reports
  frequency and bandwidth incorrectly

  This issue will be resolved in a future version of the Intel
  Acceleration Stack.

• fpgainfo may raise a UnicodeEncodeError when the Python*
  interpreter cannot determine what encoding to use
  
  This issue typically occurs when redirecting or piping output. The
  fpgabist tool calls fpgainfo and is also impacted.

  There are two workarounds for this issue:

• Set the PYTHONENCODING environment variable to UTF-8.

• Modify the fpgainfo script to force the use of UTF-8:

  -- Add an import codecs statement at the top of the file with the
  other import statements.

  -- Before the line that calls args.func(args), insert this comment and code line:

  # wrap stdout with the StreamWriter that does unicode
  sys.stdout = codecs.getwriter('UTF- 8')(sys.stdout)

• When simulating the hello_intr_afu sample code, the
  af2cp_sTxPort.c1.hdr.rsvd2[5:4] has a value of X

  This issue will be resolved in the Intel Acceleration Stack 1.1
  version.

opae-sdk-0.13.0

The Open Programmable Acceleration Engine is a software framework for managing and accessing programmable accelerators (FPGAs). Its main parts are:

• The OPAE Software Development Kit (OPAE SDK),
• the OPAE Linux driver for Intel(R) Xeon(R) CPU with FPGAs, and
• the Basic Building Block (BBB) library for accelerating AFU development (not part of this release, but pre-release code is available [on GitHub)[https://github.com/OPAE/intel-fpga-bbb]

OPAE is under active development to extend to more hardware platforms, as well as to build up the software stack with additional abstractions to enable more software developers.

The OPAE SDK is a collection of libraries and tools to facilitate the development of software applications and accelerators using OPAE. It provides a library implementing the OPAE C API for presenting a streamlined and easy-to-use interface for software applications to discover, access, and manage FPGA devices and accelerators using the OPAE software stack. The OPAE SDK also includes the AFU Simulation Environment (ASE) for end-to-end simulation of accelerator RTL together with software applications using the OPAE C API.

OPAE's goal is to accelerate FPGA adoption. It is a community effort to simplify the development and deployment of FPGA applications, so we explicitly welcome discussions and contributions! The OPAE SDK source, unless otherwise noted, is released under a BSD 3-clause license.

More information about OPAE can be found at http://01.org/OPAE.

Open Programmable Acceleration Engine (OPAE) 0.13.0 Release Notes

This document provides the Release Notes for the Open Programmable Acceleration Engine (OPAE) 0.13.0 release.

System Compatibility

• Hardware: tightly coupled FPGA products and programmable FPGA acceleration cards for Intel(R) Xeon(R) processors (to be released); Intel(R) PAC with Arria(R) 10 card
• Operating System: tested on Red Hat Enterprise Linux 7.3, Red Hat Enterprise Linux 7.4, and CentOS 7.4, with Linux kernels 3.10 through 4.7
• FIM (FPGA Interface Manager): 6.4.0

Major Changes from 0.9.0 to 0.13.0

For a detailed list of changes, please visit https://github.com/OPAE/opae-sdk/commits/0.13.0.

OPAE SDK

• Added port and user interrupt support for selected platforms
• Improved ASE simulator compatibility
• Augmented ASE with memory model for locally attached memory
• Added new tools
  • AFU packager (packager)
  • FIM flash tool (fpgaflash)
  • Port assignment tool for enabling virtualization (fpgaport)
  • Built-in self test (fpgabist)
  • Core idling tool for adjusting CPU power budget (coreidle)
  • CCIP-MUX testing tool (fpgamux)
• Added fpgainfo features
• Added support for object ID property
• Added platform database for AFU interface generation in ASE
• Integrated OPAE documentation sources
• Code quality improvements, bug fixes, and clean up
• Removed power threshold 2 to account for FIM changes
• Updated compilation flags for defensive compilation
• Added support for Travis CI regression testing

OPAE Linux driver for Intel(R) Xeon(R) CPU with FPGAs

• Added support for FIM 6.4.0 (including interrupt support for selected platforms)
• Integrated driver for Altera / intel mSGDMA IP core
• Code quality improvements, bug fixes, and clean up

Notes / Known Issues

• Partial reconfiguration with SR-IOV

  If using OPAE in a virtualized environment with SR-IOV enabled, we recommend disabling SR-IOV before performing partial reconfiguration. See "Partial Reconfiguration" in the "OPAE Intel FPGA Linux Device Driver Architecture" document for more information

• fpgaAssignToInterface() and fpgaReleaseFromInterface() not supported

  The OPAE C API provides functions to assign individual AFCs to host interfaces (i.e. a virtual or physical function). Due to the internal implementation of fpga_token, these functions are not yet supported. Instead, we provide a simplified call fpgaAssignPortToInterface() that can assign a port by number to either the physical function (PF) or virtual function (VF). This function will eventually be replaced by the more generic implementation of fpgaAssignToInterface() and fpgaReleaseFromInterface() in a future release.

• hssi_loopback tool help menu lists incorrect option for packet count

  The help menu indicates -p is the packet count, however the actual switch is -c.

• AP6 condition may prevent clearing of port errors

  If the system encounters an AP6 condition (exceeded power or temperature threshold), it will report a port error. These errors can only be cleared (e.g. using fpgainfo) after the AP6 condition has been removed.

• Driver may not display explicit incompatibility message if loaded on mismatched FIM version

  When trying to insert the Linux kernel driver modules while an FPGA platform with an unsupported FIM version is present in the system, the driver may fail to load and/or fail to print an explicit incompatibility warning message in the system log. Please make sure to use the driver only with a compatible FIM.

• Multiple ModelSim simulator instances may crash when run on the same host

  When trying to run multiple instances of the ModelSim simulator on a single system, the simulator may crash. Only run one instance of ModelSim at the same time per system.

opae-sdk-0.9.0

The Open Programmable Acceleration Engine is a software framework for managing and accessing programmable accelerators (FPGAs). It currently consists of two main parts, the OPAE SDK, and the OPAE Linux driver for Intel(R) Xeon(R) CPU with FPGAs, and is under active development to extend to more platforms.

The OPAE SDK is a collection of libraries and tools to facilitate the development of software applications and accelerators using OPAE. It provides a library implementing the OPAE C API for presenting a streamlined and easy-to-use interface for software applications to discover, access, and manage FPGA devices and accelerators using the OPAE software stack. The OPAE SDK also includes the AFU Simulation Environment (ASE) for end-to-end simulation of accelerator RTL together with software applications using the OPAE C API.

OPAE is intended to be a community effort to simplify the development and deployment of FPGA applications, so we explicitly welcome discussions and contributions! The OPAE SDK source, unless otherwise noted, is released under a BSD 3-clause license.

Open Programmable Acceleration Engine (OPAE) 0.9.0 Release Notes

This document provides the Release Notes for the Open Programmable Acceleration
Engine (OPAE) 0.9.0 release.

System Compatibility

• Hardware: tightly coupled FPGA products and programmable FPGA acceleration
  cards for Intel(R) Xeon(R) processors (to be released)
• Operating System: tested on RedHat 7.3, Linux kernels 3.10 through 4.7
• FIM (FPGA Interface Manager): 6.3.0

Known Issues

• Partial reconfiguration with SR-IOV

  If using OPAE in a virtualized environment with SR-IOV enabled, we recommend
  disabling SR-IOV before performing partial reconfiguration. See "Partial
  Reconfiguration" in the "OPAE Intel FPGA Linux Device Driver Architecture"
  document for more information

• fpgaAssignToInterface() and fpgaReleaseFromInterface() not supported

  The OPAE C API provides functions to assign individual AFCs to host interfaces
  (i.e. a virtual or physical function). Due to the internal implementation of
  fpga_token, these functions are not yet supported. Instead, we provide a
  simplified call fpgaAssignPortToInterface() that can assign a port by number
  to either the physical function (PF) or virtual function (VF). This function
  will eventually be replaced by the more generic implementation of
  fpgaAssignToInterface() and fpgaReleaseFromInterface() in a future release.

• UMsgs are not supported on BBS 6.3.0

  The 6.3.0 blue bitstream for the Xeon Processor with Integrated FPGA exposes
  UMsg functionality, but does not fully support it. We recommend not using UMsg
  functionality with a 6.3.0 bitstream, although software will report is as
  being supported.

• Driver RPM uninstallation does not clean up initrd on CentOS

  When removing the driver RPM on CentOS, the package may leave the compiled
  FPGA driver modules in initrd.

• Allocation of multiple 1 GiB buffers on VT-d-enabled system may sporadially
  fail

  In certain configurations, allocating multiple 1 GiB huge pages on a
  non-virtualized system with VT-d turned on and an activated IOMMU may result
  in system instability. As an alternative, try disabling VT-d or the IOMMU, or
  running in a virtual machine.

• Virtualized applications with frequent MMIO accesses may sporadically fail

  In certain configuration, high-frequency MMIO accesses from a virtual machine
  with a passed-through virtual function (VF) may trigger system instability.

• Parallel partial reconfiguration on multiple FPGAs using fpgaconf may fail

  When programing multiple FPGAs concurrently using the 'fpgaconf' tool, single
  configurations may fail with the message "device enumeration failed". This is
  due to a collision of enumeration with a partial reconfiguration process, and
  is a recoverable error; either clear the PORT errors of the respective FPGA,
  or to attempt another reconfiguration using 'fpgaconf'.

• AP events may not be triggered

  In certain circumstances, AP1/AP2 events may not be delivered to fpgad or user
  applications using fpgad for event delivery. Temperature status is correctly
  reported using fpgainfo or sysfs.