RVF.core_desc

import "RVI.core_desc"

// TODO: review instruction description wrt. Spec after type system is fixed
InstructionSet RVF extends RVFPBase {
    
    functions {
        extern unsigned<32> fadd_s(unsigned<32>, unsigned<32>, unsigned char);
        extern unsigned<32> fsub_s(unsigned<32>, unsigned<32>, unsigned char);
        extern unsigned<32> fmul_s(unsigned<32>, unsigned<32>, unsigned char);
        extern unsigned<32> fdiv_s(unsigned<32>, unsigned<32>, unsigned char);
        extern unsigned<32> fmadd_s(unsigned<32>, unsigned<32>, unsigned<32>, unsigned<32>, unsigned char);
        extern unsigned<32> fsel_s(unsigned<32>, unsigned<32>, unsigned<32>);
        extern unsigned<32> fsqrt_s(unsigned<32>, unsigned char);
        extern unsigned<32> fcmp_s(unsigned<32>, unsigned<32>, unsigned<32>);
        extern unsigned<32> fcvt_s(unsigned<32>, unsigned<32>, unsigned char);
        extern unsigned<64> fcvt_32_64(unsigned<32>, unsigned<32>, unsigned char);
        extern unsigned<32> fcvt_64_32(unsigned<64>, unsigned<32>, unsigned char);
        extern unsigned<32> unbox_s(unsigned<64>);
        extern unsigned<32> fclass_s(unsigned<32>);
        extern unsigned<32> fget_flags();

        unsigned<3> get_rm(unsigned<3> rm) {
            if (rm == 7) rm = FCSR[7:5];
            if (rm > 4) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION);
            return rm;
        }
    }

    instructions {
        FLW [[enable=FLEN==32]] {
            encoding: imm[11:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0000111;
            assembly:"{fname(rd)}, {imm}({name(rs1)})";
            behavior: if(rs1 >= RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<XLEN> offs = (unsigned<32>)(X[rs1] + (signed<12>)imm);
                F[rd] = (unsigned<32>)MEM[offs+3:offs];
            }
        }

        FLW [[enable=FLEN==64]] {
            encoding: imm[11:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0000111;
            assembly:"{fname(rd)}, {imm}({name(rs1)})";
            behavior: if(rs1 >= RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<XLEN> offs = (unsigned<32>)(X[rs1] + (signed<12>)imm);
                unsigned<32> res = (unsigned<32>)MEM[offs+3:offs];
                F[rd] = (unsigned<FLEN>)((signed<FLEN>)-1 << 32) | (unsigned<FLEN>)res;
            }
        }

        FSW {
            encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: imm[4:0] :: 7'b0100111;
            assembly: "{fname(rs2)}, {imm}({name(rs1)])";
            behavior: if(rs1 >= RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<XLEN> offs = (unsigned<32>)(X[rs1] + (signed<12>)imm);
                MEM[offs+3:offs] = (unsigned<32>)F[rs2];
            }
        }

        FMADD__S [[enable=FLEN==32]] {
            encoding: rs3[4:0] :: 2'b00 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1000011;
            assembly: "{name(rm)}, {name(rd)}, {fname(rs1)}, {fname(rs2)}, {fname(rs3)}";
            behavior: {
                F[rd] = (unsigned<FLEN>)fmadd_s(F[rs1], F[rs2], F[rs3], 0, rm<7? (unsigned char)rm:(unsigned char)FCSR);
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FMADD__S [[enable=FLEN==64]] {
            encoding: rs3[4:0] :: 2'b00 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1000011;
            assembly:"{name(rm)}, {name(rd)}, f {rs1}, f {rs2}, f {rs3}";
            behavior: {
                unsigned<32> res = fmadd_s(unbox_s(F[rs1]), unbox_s(F[rs2]), unbox_s(F[rs3]), 0, rm<7? rm: (unsigned char)FCSR);
                F[rd] = (unsigned<FLEN>)((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FMSUB__S [[enable=FLEN==32]] {
            encoding: rs3[4:0] :: 2'b00 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1000111;
            assembly: "{name(rm)}, {name(rd)}, {fname(rs1)}, {fname(rs2)}, {fname(rs3)}";
            behavior: {
                F[rd] = fmadd_s(F[rs1], F[rs2], F[rs3], 1, rm<7? rm: (unsigned char)FCSR);
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FMSUB__S [[enable=FLEN==64]] {
            encoding: rs3[4:0] :: 2'b00 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1000111;
            assembly:"{name(rm)}, {name(rd)}, f {rs1}, f {rs2}, f {rs3}";
            behavior: {
                unsigned<32> res = fmadd_s(unbox_s(F[rs1]), unbox_s(F[rs2]), unbox_s(F[rs3]), 1, rm<7? rm: (unsigned char)FCSR);
                F[rd] = (unsigned<FLEN>)((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FNMADD__S [[enable=FLEN==32]] {
            encoding: rs3[4:0] :: 2'b00 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1001111;
            assembly: "{name(rm)}, name(rd), {fname(rs1)}, {fname(rs2)}, {fname(rs3)}";
            behavior: {
                F[rd] = fmadd_s(F[rs1], F[rs2], F[rs3], 2, rm<7? rm: (unsigned char)FCSR);
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FNMADD__S [[enable=FLEN==64]] {
            encoding: rs3[4:0] :: 2'b00 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1001111;
            assembly:"{name(rm)}, name(rd), f {rs1}, f {rs2}, f {rs3}";
            behavior: {
                unsigned<32> frs1 = unbox_s(F[rs1]);
                unsigned<32> frs2 = unbox_s(F[rs2]);
                unsigned<32> frs3 = unbox_s(F[rs3]);
                unsigned<32> res = fmadd_s(frs1, frs2, frs3, 2, rm<7? rm: (unsigned char)FCSR);
                F[rd] = (unsigned<FLEN>)((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FNMSUB__S [[enable=FLEN==32]] {
            encoding: rs3[4:0] :: 2'b00 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1001011;
            assembly: "{name(rm)}, {name(rd)}, {fname(rs1)}, {fname(rs2)}, {fname(rs3)}";
            behavior: {
                F[rd] = fmadd_s(F[rs1], F[rs2], F[rs3], 3, rm<7? rm: (unsigned char)FCSR);
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FNMSUB__S [[enable=FLEN==64]] {
            encoding: rs3[4:0] :: 2'b00 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1001011;
            assembly:"{name(rm)}, {name(rd)}, f {rs1}, f {rs2}, f {rs3}";
            behavior: {
                unsigned<32> frs1 = unbox_s(F[rs1]);
                unsigned<32> frs2 = unbox_s(F[rs2]);
                unsigned<32> frs3 = unbox_s(F[rs3]);
                unsigned<32> res = fmadd_s(frs1, frs2, frs3, 3, rm<7? rm: (unsigned char)FCSR);
                F[rd] = (unsigned<FLEN>)((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FADD__S [[enable=FLEN==32]] {
            encoding: 7'b0000000 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly: {"fadd.s", "{name(rm)}, {fname(rd)}, {fname(rs1)}, {fname(rs2)}"};
            behavior: {
                F[rd] = fadd_s(F[rs1], F[rs2], rm<7? rm: (unsigned char)FCSR);
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FADD__S [[enable=FLEN==64]] {
            encoding: 7'b0000000 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly:"{name(rm)}, f {rd}, f {rs1}, f {rs2}";
            behavior: {
                unsigned<32> frs1 = unbox_s(F[rs1]);
                unsigned<32> frs2 = unbox_s(F[rs2]);
                unsigned<32> res = fadd_s(frs1, frs2, rm<7? rm: (unsigned char)FCSR);
                F[rd] = (unsigned<FLEN>)((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FSUB__S [[enable=FLEN==32]] {
            encoding: 7'b0000100 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly: {"fsub.s", "{name(rm)}, {fname(rd)}, {fname(rs1)}, {fname(rs2)}"};
            behavior: {
                F[rd] = fsub_s(F[rs1], F[rs2], rm<7? rm: (unsigned char)FCSR);
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FSUB__S [[enable=FLEN==64]] {
            encoding: 7'b0000100 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly:"{name(rm)}, f {rd}, f {rs1}, f {rs2}";
            behavior: {
                unsigned<32> frs1 = unbox_s(F[rs1]);
                unsigned<32> frs2 = unbox_s(F[rs2]);
                unsigned<32> res = fsub_s(frs1, frs2, rm<7? rm: (unsigned char)FCSR);
                F[rd] = (unsigned<FLEN>)((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FMUL__S [[enable=FLEN==32]] {
            encoding: 7'b0001000 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly: {"fmul.s", "{name(rm)}, {fname(rd)}, {fname(rs1)}, {fname(rs2)}"};
            behavior: {
                F[rd] = fmul_s(F[rs1], F[rs2], rm<7? rm: (unsigned char)FCSR);
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FMUL__S [[enable=FLEN==64]] {
            encoding: 7'b0001000 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly:"{name(rm)}, f {rd}, f {rs1}, f {rs2}";
            behavior: {
                unsigned<32> frs1 = unbox_s(F[rs1]);
                unsigned<32> frs2 = unbox_s(F[rs2]);
                unsigned<32> res = fmul_s(frs1, frs2, rm<7? rm: (unsigned char)FCSR);
                F[rd] = (unsigned<FLEN>)((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FDIV__S [[enable=FLEN==32]] {
            encoding: 7'b0001100 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly: {"fdiv.s", "{name(rm)}, {fname(rd)}, {fname(rs1)}, {fname(rs2)}"};
            behavior: {
                F[rd] = fdiv_s(F[rs1], F[rs2], rm<7? rm: (unsigned char)FCSR);
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FDIV__S [[enable=FLEN==64]] {
            encoding: 7'b0001100 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly:"{name(rm)}, f {rd}, f {rs1}, f {rs2}";
            behavior: {
                unsigned<32> frs1 = unbox_s(F[rs1]);
                unsigned<32> frs2 = unbox_s(F[rs2]);
                unsigned<32> res = fdiv_s(frs1, frs2, rm<7? rm: (unsigned char)FCSR);
                F[rd] = (unsigned<FLEN>)((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FSQRT__S [[enable=FLEN==32]] {
            encoding: 7'b0101100 :: 5'b00000 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly: {"fsqrt.s", "{name(rm)}, {fname(rd)}, {fname(rs1)}"};
            behavior: {
                F[rd] = fsqrt_s(F[rs1], rm<7? rm: (unsigned char)FCSR);
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FSQRT__S [[enable=FLEN==64]] {
            encoding: 7'b0101100 :: 5'b00000 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly:"{name(rm)}, f {rd}, f {rs1}";
            behavior: {
                unsigned<32> frs1 = unbox_s(F[rs1]);
                unsigned<32> res = fsqrt_s(frs1, rm<7? rm: (unsigned char)FCSR);
                F[rd] = (unsigned<FLEN>)((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FSGNJ__S [[enable=FLEN==32]] {
            encoding: 7'b0010000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1010011;
            assembly: {"fsgnj.s", "{fname(rd)}, {fname(rs1)}, {fname(rs2)}"};
            behavior: {
                F[rd] = F[rs2][31:31] :: F[rs1][30:0];
            }
        }

        FSGNJ__S [[enable=FLEN==64]] {
            encoding: 7'b0010000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1010011;
            assembly:"f {rd}, f {rs1}, f {rs2}";
            behavior: {// NaN boxing
                unsigned<32> frs1 = unbox_s(F[rs1]);
                unsigned<32> frs2 = unbox_s(F[rs2]);
                unsigned<32> res = frs2[31:31] :: frs1[30:0];
                F[rd] = (unsigned<FLEN>)(-1 << 32) | (unsigned<FLEN>)res;
            }
        }

        FSGNJN__S [[enable=FLEN==32]] {
            encoding: 7'b0010000 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1010011;
            assembly: {"fsgnjn.s", "{fname(rd)}, {fname(rs1)}, {fname(rs2)}"};
            behavior: {
                F[rd] = ~F[rs2][31:31] :: F[rs1][30:0];
            }
        }

        FSGNJN__S [[enable=FLEN==64]] {
            encoding: 7'b0010000 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1010011;
            assembly:"f {rd}, f {rs1}, f {rs2}";
            behavior: {// NaN boxing
                unsigned<32> frs1 = unbox_s(F[rs1]);
                unsigned<32> frs2 = unbox_s(F[rs2]);
                unsigned<32> res = ~frs2[31:31] :: frs1[30:0];
                F[rd] = (unsigned<FLEN>)(-1 << 32) | (unsigned<FLEN>)res;
            }
        }

        FSGNJX__S [[enable=FLEN==32]] {
            encoding: 7'b0010000 :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1010011;
            assembly: {"fsgnjx.s", "{fname(rd)}, {fname(rs1)}, {fname(rs2)}"};
            behavior: {
                F[rd] = F[rs1] ^ (F[rs2] & 0x80000000);
            }
        }

        FSGNJX__S [[enable=FLEN==64]] {
            encoding: 7'b0010000 :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1010011;
            assembly:"f {rd}, f {rs1}, f {rs2}";
            behavior: {// NaN boxing
                unsigned<32> frs1 = unbox_s(F[rs1]);
                unsigned<32> frs2 = unbox_s(F[rs2]);
                unsigned<32> res = frs1 ^ (frs2 & 0x80000000);
                F[rd] = (unsigned<FLEN>)((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
            }
        }

        FMIN__S [[enable=FLEN==32]] {
            encoding: 7'b0010100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1010011;
            assembly: {"fmin.s", "{fname(rd)}, {fname(rs1)}, {fname(rs2)}"};
            behavior: {
                F[rd] = fsel_s(F[rs1], F[rs2], 0);
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FMIN__S [[enable=FLEN==64]] {
            encoding: 7'b0010100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1010011;
            assembly:"f {rd}, f {rs1}, f {rs2}";
            behavior: {
                unsigned<32> frs1 = unbox_s(F[rs1]);
                unsigned<32> frs2 = unbox_s(F[rs2]);
                unsigned<32> res = fsel_s(frs1, frs2, 0);
                F[rd] = (unsigned<FLEN>)((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FMAX__S [[enable=FLEN==32]] {
            encoding: 7'b0010100 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1010011;
            assembly: {"fmax.s", "{fname(rd)}, {fname(rs1)}, {fname(rs2)}"};
            behavior: {
                F[rd] = fsel_s(F[rs1], F[rs2], 1);
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FMAX__S [[enable=FLEN==64]] {
            encoding: 7'b0010100 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1010011;
            assembly:"f {rd}, f {rs1}, f {rs2}";
            behavior: {
                unsigned<32> frs1 = unbox_s(F[rs1]);
                unsigned<32> frs2 = unbox_s(F[rs2]);
                unsigned<32> res = fsel_s(frs1, frs2, 1);
                F[rd] = (unsigned<FLEN>)((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FCVT__W__S [[enable=FLEN==32]] {
            encoding: 7'b1100000 :: 5'b00000 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly: {"fcvt.w.s", "{name(rm)}, {name(rd)}, {fname(rs1)}"};
            behavior: if(rd >=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<32> res = fcvt_s(F[rs1], 0, rm);
                if ((rd) != 0) X[rd] = res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FCVT__W__S [[enable=FLEN==64]] {
            encoding: 7'b1100000 :: 5'b00000 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly: {"fcvt.w.s", "{name(rm)}, {name(rd)}, {fname(rs1)}"};
            behavior: if(rd >=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<32> frs1 = unbox_s(F[rs1]);
                unsigned<32> res = fcvt_s(frs1, 0, rm);
                if ((rd) != 0) X[rd] = res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FCVT__WU__S [[enable=FLEN==32]] {
            encoding: 7'b1100000 :: 5'b00001 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly: {"fcvt.wu.s", "{name(rm)}, {name(rd)}, {fname(rs1)}"};
            behavior: if(rd >=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                //FIXME: according to the spec it should be zero-extended not sign extended
                unsigned<32> res = fcvt_s(F[rs1], 1, rm);
                if ((rd) != 0) X[rd] = res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FCVT__WU__S [[enable=FLEN==64]] {
            encoding: 7'b1100000 :: 5'b00001 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly:"{name(rm)}, {name(rd)}, f {rs1}";
            behavior: if(rd >=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                //FIXME: according to the spec it should be zero-extended not sign extended
                unsigned<32> frs1 = unbox_s(F[rs1]);
                unsigned<32> res = fcvt_s(frs1, 1, rm);
                if ((rd) != 0) X[rd] = res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FEQ__S [[enable=FLEN==32]] {
            encoding: 7'b1010000 :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1010011;
            assembly: {"feq.s", "{name(rd)}, {fname(rs1)}, {fname(rs2)}"};
            behavior: if(rd >=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<32> res = fcmp_s(F[rs1], F[rs2], 0);
                if ((rd) != 0) X[rd] = res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FEQ__S [[enable=FLEN==64]] {
            encoding: 7'b1010000 :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1010011;
            assembly: {"feq.s", "{name(rd)}, {fname(rs1)}, {fname(rs2)}"};
            behavior: if(rd >=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<32> frs1 = unbox_s(F[rs1]);
                unsigned<32> frs2 = unbox_s(F[rs2]);
                unsigned<32> res = fcmp_s(frs1, frs2, 0);
                if ((rd) != 0) X[rd] = res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FLT__S [[enable=FLEN==32]] {
            encoding: 7'b1010000 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1010011;
            assembly: {"flt.s", "{name(rd)}, {fname(rs1)}, {fname(rs2)}"};
            behavior: if(rd >=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<32> res = fcmp_s(F[rs1], F[rs2], 2);
                if ((rd) != 0) X[rd] = res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FLT__S [[enable=FLEN==64]] {
            encoding: 7'b1010000 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1010011;
            assembly: {"flt.s", "{name(rd)}, {fname(rs1)}, {fname(rs2)}"};
            behavior: if(rd >=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<32> frs1 = unbox_s(F[rs1]);
                unsigned<32> frs2 = unbox_s(F[rs2]);
                unsigned<32> res = fcmp_s(frs1, frs2, 2);
                if ((rd) != 0) X[rd] = res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FLE__S [[enable=FLEN==32]] {
            encoding: 7'b1010000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1010011;
            assembly: {"fle.s", "{name(rd)}, {fname(rs1)}, {fname(rs2)}"};
            behavior: if(rd >=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<32> res = fcmp_s(F[rs1], F[rs2], 1);
                if ((rd) != 0) X[rd] = res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FLE__S [[enable=FLEN==64]] {
            encoding: 7'b1010000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1010011;
            assembly: {"fle.s", "{name(rd)}, {fname(rs1)}, {fname(rs2)}"};
            behavior: if(rd >=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<32> frs1 = unbox_s(F[rs1]);
                unsigned<32> frs2 = unbox_s(F[rs2]);
                unsigned<32> res = fcmp_s(frs1, frs2, 1);
                if ((rd) != 0) X[rd] = res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FCLASS__S [[enable=FLEN==32]] {
            encoding: 7'b1110000 :: 5'b00000 :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1010011;
            assembly: {"fclass.s", "{name(rd)}, {fname(rs1)}"};
            behavior: if(rd >=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<32> res = fclass_s(F[rs1]);
                if ((rd) != 0) X[rd] = res;
            }
        }

        FCLASS__S [[enable=FLEN==64]] {
            encoding: 7'b1110000 :: 5'b00000 :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1010011;
            assembly: {"fclass.s", "{name(rd)}, {fname(rs1)}"};
            behavior: if(rd >=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<32> res = fclass_s(unbox_s(F[rs1]));
                if ((rd) != 0) X[rd] = res;
            }
        }

        FCVT__S__W [[enable=FLEN==32]] {
            encoding: 7'b1101000 :: 5'b00000 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly: {"fcvt.s.w", "{name(rm)}, {fname(rd)}, {name(rs1)}"};
            behavior: if(rs1 >= RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                F[rd] = fcvt_s((unsigned)X[rs1], 2, rm);
            }
        }

        FCVT__S__W [[enable=FLEN==64]] {
            encoding: 7'b1101000 :: 5'b00000 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly: {"fcvt.s.w", "{name(rm)}, {fname(rd)}, {name(rs1)}"};
            behavior: if(rs1 >= RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<32> res = fcvt_s((unsigned)X[rs1], 2, rm);
                F[rd] = (unsigned<FLEN>)((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
            }
        }

        FCVT__S__WU [[enable=FLEN==32]] {
            encoding: 7'b1101000 :: 5'b00001 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly: {"fcvt.s.wu", "{name(rm)}, {fname(rd)}, {name(rs1)}"};
            behavior: if(rs1 >= RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                F[rd] = fcvt_s((unsigned)X[rs1], 3, rm);
            }
        }

        FCVT__S__WU [[enable=FLEN==64]] {
            encoding: 7'b1101000 :: 5'b00001 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly: {"fcvt.s.wu", "{name(rm)}, {fname(rd)}, {name(rs1)}"};
            behavior: if(rs1 >= RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<32> res = fcvt_s((unsigned)X[rs1], 3, rm);
                F[rd] = (unsigned<FLEN>)((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
            }
        }

        FMV__X__W {
            encoding: 7'b1110000 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1010011;
            assembly: {"fmv.x.w", "{name(rd)}, {fname(rs1)}"};
            behavior: if(rd >=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                if ((rd) != 0) X[rd] = F[rs1];
            }
        }

        FMV__W__X [[enable=FLEN==32]] {
            encoding: 7'b1111000 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1010011;
            assembly:"f {rd}, {name(rs1)}";
            behavior: if(rs1 >= RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                F[rd] = X[rs1];
            }
        }

        FMV__W__X [[enable=FLEN==64]] {
            encoding: 7'b1111000 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1010011;
            assembly:"f {rd}, {name(rs1)}";
            behavior: if(rs1 >= RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                F[rd] = (unsigned<FLEN>)((signed<64>)-1 << 32) | (unsigned<FLEN>)X[rs1];
            }
        }

        FCVT_L_S [[enable=XLEN==64]] { // fp to 64bit signed integer
            encoding: 7'b1100000 :: 5'b00010 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly: {"fcvt.l.s", "{name(rm)}, {name(rd)}, {fname(rs1)}"};
            behavior: if(rd >=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<64> res = fcvt_32_64(unbox_s(F[rs1]), 0, rm);
                if ((rd) != 0) X[rd] = res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FCVT_LU_S [[enable=XLEN==64]] { // fp to 64bit unsigned integer
            encoding: 7'b1100000 :: 5'b00011 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly: {"fcvt.lu.s", "{name(rm)}, {name(rd)}, {fname(rs1)}"};
            behavior: if(rd >=RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<64> res = fcvt_32_64(unbox_s(F[rs1]), 1, rm);
                if ((rd) != 0) X[rd] = res;
                unsigned<32> flags = fget_flags();
                FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
            }
        }

        FCVT_S_L [[enable=XLEN==64]] { // 64bit signed int to to fp
            encoding: 7'b1101000 :: 5'b00010 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly: {"fcvt.s.l", "{name(rm)}, {fname(rd)}, {name(rs1)}"};
            behavior: if(rs1 >= RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<32> res = fcvt_64_32(X[rs1], 2, rm);
                if (FLEN == 32)
                    F[rd] = res;
                else { // NaN boxing
                    F[rd] = (unsigned<FLEN>)((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
                }
            }
        }

        FCVT_S_LU [[enable=XLEN==64]] { // 64bit unsigned int to to fp
            encoding: 7'b1101000 :: 5'b00011 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
            assembly: {"fcvt.s.lu", "{name(rm)}, {fname(rd)}, {name(rs1)}"};
            behavior: if(rs1 >= RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<32> res = fcvt_64_32(X[rs1], 3, rm);
                if (FLEN == 32)
                    F[rd] = res;
                else { // NaN boxing
                    F[rd] = (unsigned<FLEN>)((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
                }
            }
        }
    }
}