Questions regarding time abstraction

[felix-boeseler]

Hello,

In what timing abstraction does the RISC-V ISS work? Does it assume a fixed delay per instructions or has different delays per instructions? Are some features of a microarchitecture simulated e.g., branch predictions? Where are these parameters (delays) defined? I have found the Plugin cycle_estimate class I don’t understand how the delay is extracted from the properties taken and not_taken.

Furthermore, I want to ask, which transaction abstractions are supported. I find the usage of nb_transport and b_transport in the source code. Does DBT-RISE-RISCV support both, SystemC loosely timed and approximately timed modelling styles? In the build directory I also find the executable axi_pinlevel_example. It seems that the AXI bus is simulated on a even lower abstraction level there.

Best regards and many thanks in advance