MARTIn Chip

[nickguimara]

A chip developed at the University of São Paulo (USP) aimed at testing a median finding algorithm that should be encompassed in a front end readout ASIC for particle physics experiments.

Contact via: [email protected]

[nickguimara]

KrzysztofHerman filling script was used to remove DRC errors

[nickguimara]

The DRC check in this pull requested has dissapeared, is that expected?

[KrzysztofHerman]

@nickguimara thank you for the submission, your design is DRC clean (minimal set).
after a short review please fix the following:

1. Please provide your behavioral System Verilog, Verilog which was used for synthesis. The same applies to the configuration of the OpenORAD flow scripts and sv2v. Since our IHP-Open-PDK project has an educational purpose the general idea is that one should be able to replicate your design having data from this repository, documentation and valid version of the tools and the PDK.
2. gds names - please provide something more verbose and meaningful like MARTIn_nofill.gds
3. gds names - the final, filled version of the gds should start with the prefix FMD_QNC_
4. gds top level cell name - please provide some other name ie. MARTIn_TOP
5. fix other file names also
6. provide information which version/branch of the PDK and tools (OpenRoad, KLayout etc.) were used (the best is to provide a particular branch/commit)
7. Provide information about pad ring in the documentation (pinout).
8. Provide a block diagram which includes functional blocks implemented in System Verilog.

[nickguimara]

Added (1) to (7) corrections. 3 minimal DRC erros are expected, but are outside the chip area. The block diagram is being made

[nickguimara]

Block diagram added, everything should be right now. If you find out any modifications necessary, please let me know.

[KrzysztofHerman]

@nickguimara reviewing your last commit still I can not reproduce the design.

1. How one is supposed to tun the testbenches using SystemVerilog files, which open source tool supports it ?
2. In the config.mk there are no references to the IO pads and bondpad. So the question is how the physical design was performed using this script.

Please update the repository with the data and configuration necessary to reproduce your design.

[nickguimara]

The IO pads and bond pad configuration are configured trough the pad.tcl file. That file is called through the config.mk file. Do you want me to further clarify that in the specifications? Thought is was common procedure in OpenRoad environment

[nickguimara]

And I'll provide the correct Verilog testbenches

[KrzysztofHerman]

@nickguimara
Congratulations !
You design was accepted for production.
Testfield: T576
Top cell name: martin_top