Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Coriolis - Arlet6502 #19

Merged
merged 6 commits into from
Nov 25, 2024
Merged

Coriolis - Arlet6502 #19

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
6 commits
Select commit Hold shift + click to select a range
10a48cc
Layout is DRC clean. Density & seal remains to be done.
jpc-lip6 Nov 16, 2024
ef13bf9
Re-enable HFNS, integrate filler & sealring doit script.
jpc-lip6 Nov 18, 2024
8a52fc2
First iteration of the design.
jpc-lip6 Nov 18, 2024
937cce4
Add a short problem description for sealring.
jpc-lip6 Nov 18, 2024
de05fdb
The final design, pass most of the maximal DRC deck.
jpc-lip6 Nov 22, 2024
f9f664b
Manually adding the sealring and running filler scripts.
jpc-lip6 Nov 22, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 4 additions & 0 deletions .gitignore
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,4 @@
__pycache__/
logs/
cgt.log
.doit.db
Binary file added arlet6502/design_data/gds/FMD_QNC_Arlet6502.gds
View file
Open in desktop
Binary file not shown.
1 change: 1 addition & 0 deletions arlet6502/design_data/layout/ALU.v
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
../rtl/ALU.v
2,241 changes: 2,241 additions & 0 deletions arlet6502/design_data/layout/Arlet6502.blif
View file
Open in desktop

Large diffs are not rendered by default.

1 change: 1 addition & 0 deletions arlet6502/design_data/layout/Arlet6502.v
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
../rtl/Arlet6502.v
11 changes: 11 additions & 0 deletions arlet6502/design_data/layout/Arlet6502.ys
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
read_verilog -sv Arlet6502.v
hierarchy -check -top Arlet6502
synth -top Arlet6502
flatten
hierarchy -top Arlet6502
memory
dfflibmap -liberty /dsk/l1/jpc/coriolis-2.x/release/install/lib64/python3.9/site-packages/pdks/c4m_ihpsg13g2/libs.ref/StdCellLib/liberty/StdCellLib_nom.lib
abc -liberty /dsk/l1/jpc/coriolis-2.x/release/install/lib64/python3.9/site-packages/pdks/c4m_ihpsg13g2/libs.ref/StdCellLib/liberty/StdCellLib_nom.lib
stat
clean
write_blif Arlet6502.blif
21 changes: 21 additions & 0 deletions arlet6502/design_data/layout/README.rst
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,21 @@


Tools versions used for this design
===================================


.. note::

In order to match the deadline, a techno specific patch for BigVia has
been used. It is not yet in the Coriolis repository as I need a more
generic way to do it.


=================================== ============================================= =========
Tool Repository Commit
=================================== ============================================= =========
coriolis-eda https://github.com/lip6/coriolis ff9d73645
IHP-Open-PDK (LIP6 fork at 4c6508d) https://github.com/lip6/IHP-Open-PDK.git 03fe67f
c4m-ihpsg13g2 https://github.com/lip6/c4m-ihpsg13g2-pdk.git adbec6e
=================================== ============================================= =========

Loading
Loading