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Coriolis - Arlet6502 #19
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* DRC clean, save for densities. * Filler script not working. * Sealring script not working.
@jpc-lip6 thank you for the submission. I have some observations:
Would you like to repeat this and update the PR with these changes or shall I commit my changes and submit for production? |
Hello Krzysztof,
On Fri, 2024-11-22 at 03:02 -0800, Krzysztof Herman wrote:
@jpc-lip6 thank you for the submission.
I have some observations:
1. I had to remove the seal ring and add it manually using the newest main
branch
It is a bit strange, as I think I am up to date with main.
I am at commit:
4c6508d Merge pull request #260 from KrzysztofHerman/main
As far as I can tell, I am also up to date with the submodules.
2. I have to change the default value of metal2 filler distance to 0.55 to
meet global Metal2 density (in sg13g2_filler_Metal.lym)
I am not sure where in the file to do that, is it line 150 ?
And should I change both 0.42 or just one of them ?
149 M2Fil_c = Metal2.dup
150 M2Fil_c.size(0.42, 0.42, "square_limit")
151 M2Fil_d = TRANS.dup
152 M2Fil_d.size(1.0, 1.0, "square_limit")
153 exclLayM2 = M2Fil_c | M2Fil_d | Metal2_filler | Metal2_nofill | Metal2_slit | TRANS
And, incidentally, that would mean that I will have a if so slightly
different version of the IHP PDK ?
3. after filling the design I have got a clean minimal DRC.
Would you like to repeat this and update the PR with these changes or shall I
commit my changes and submit for production?
I will do it as soon as I got your advice on the previous point,
I would like to keep my repository as up to date and complete as
possible. Even as an example for the students at SU.
But, in case I do not make it, please do use yours.
The drawback is that seal ring placement is not ideally symmetric.
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Thanks for your checking work,
Best regards,
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/(___)\ work: (33) 01.44.27.53.99
^^ ^^ cell: 06.66.25.35.55 home: 09.65.29.83.38
S U Sorbonne Université (former UPMC)
L I P 6 Laboratoire d'Informatique de Paris VI
C I A N Circuits Intégrés Analogiques & Numériques
|
@jpc-lip6 your commit is ok. So please add seal ring using our pycells: and then modify the line 121 of the file, which will change the distance between fillers on metal2. Run filler and then DRC check (min and max). Seems that in max DRC you can have a lot of violations of the metal2 fill spacing but it is a false negative. |
On Fri, 2024-11-22 at 04:06 -0800, Krzysztof Herman wrote:
@jpc-lip6 your commit is ok.
So please add seal ring using our pycells:
image.png (view on web)
I have some trouble with the sizing of the PCell. I confess I am
not a fluent user of Klayout, except for visualisation.
What I get when I instanciate the sealring PCell is a way too
small box. With the text:
Device registration size: x=200.0 um y=200.0 um
I surely miss something obvious here or does the PCell rely on
some information *inside* the original GDS that I may not have
provided ?
By the way, should not calling the sealring.py do the same result?
Because that's what I do through the Coriolis design flow.
Then I just add it as a centered instance at the chip level.
Was the macro misplaced ? Or plainly wrong (using a non up to
date version) ?
and then modify the line 121 of the file, which will change the distance
between fillers on metal2.
The value of 0.55 worked for me to reach 40 % (35 is the minimum)
Run filler and then DRC check (min and max). Seems that in max DRC you can
have a lot of violations of the metal2 fill spacing but it is a false
negative.
You mean false positive?
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/(___)\ work: (33) 01.44.27.53.99
^^ ^^ cell: 06.66.25.35.55 home: 09.65.29.83.38
S U Sorbonne Université (former UPMC)
L I P 6 Laboratoire d'Informatique de Paris VI
C I A N Circuits Intégrés Analogiques & Numériques
|
maybe we could meet online and I can provide you some guidance. If you wish send me a |
Thanks Krzysztof,
Yes, would 3pm be ok for you (40 minutes from now) ?
I propose we use jitsi meet. I will send you the link
just before the meeting.
Best,
…On Fri, 2024-11-22 at 05:15 -0800, Krzysztof Herman wrote:
@jpc-lip6
maybe we could meet online and I can provide you some guidance. If you wish
send me a
video call link over email.
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.-. J e a n - P a u l C h a p u t / Administrateur Systeme
***@***.***
/(___)\ work: (33) 01.44.27.53.99
^^ ^^ cell: 06.66.25.35.55 home: 09.65.29.83.38
S U Sorbonne Université (former UPMC)
L I P 6 Laboratoire d'Informatique de Paris VI
C I A N Circuits Intégrés Analogiques & Numériques
|
Hello Again,
Here is the link:
https://meet.jit.si/JPC_IHP
…On Fri, 2024-11-22 at 05:15 -0800, Krzysztof Herman wrote:
@jpc-lip6
maybe we could meet online and I can provide you some guidance. If you wish
send me a
video call link over email.
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.-. J e a n - P a u l C h a p u t / Administrateur Systeme
***@***.***
/(___)\ work: (33) 01.44.27.53.99
^^ ^^ cell: 06.66.25.35.55 home: 09.65.29.83.38
S U Sorbonne Université (former UPMC)
L I P 6 Laboratoire d'Informatique de Paris VI
C I A N Circuits Intégrés Analogiques & Numériques
|
One last question: should I also run the filler script for
the "top metal" or "metal" is good enough ?
…On Fri, 2024-11-22 at 05:15 -0800, Krzysztof Herman wrote:
@jpc-lip6
maybe we could meet online and I can provide you some guidance. If you wish
send me a
video call link over email.
—
Reply to this email directly, view it on GitHub, or unsubscribe.
You are receiving this because you were mentioned.Message ID:
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--
.-. J e a n - P a u l C h a p u t / Administrateur Systeme
***@***.***
/(___)\ work: (33) 01.44.27.53.99
^^ ^^ cell: 06.66.25.35.55 home: 09.65.29.83.38
S U Sorbonne Université (former UPMC)
L I P 6 Laboratoire d'Informatique de Paris VI
C I A N Circuits Intégrés Analogiques & Numériques
|
I did push the fixed version of the layout.
Now the DRC passes on the final file, but the Github action still
fail because you are checking *all* gds presents in the tree, and
so fail on the intermediate versions of design...
If you want a nice PNG or PDF of the design you can look at
chip_r.png and chip_r.pdf.
Thanks for your help.
Best regards,
--
.-. J e a n - P a u l C h a p u t / Administrateur Systeme
***@***.***
/(___)\ work: (33) 01.44.27.53.99
^^ ^^ cell: 06.66.25.35.55 home: 09.65.29.83.38
S U Sorbonne Université (former UPMC)
L I P 6 Laboratoire d'Informatique de Paris VI
C I A N Circuits Intégrés Analogiques & Numériques
|
@jpc-lip6 Congratulations! Your design was accepted for production. |
A MOS6502 test bench for