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Primitive device: PNP/NPN (vertical oder lateral) for CMOS-only #267
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Is pnpMPA not the device you are looking for? |
Thanks for the pointer, you are absolutely right! I totally missed it because there is no pcell in KLayout (at least none that I can find) and no mention in the process description, but there is a model and symbol for simulation and a fixed layout in @KrzysztofHerman @sergeiandreyev Are there plans to provide a pcell, or is there one fixed size of PNP with a fixed layout (which is quite the norm for parasitic PNPs)? In any case, a description in the |
Hi @hpretl, yes, we're working on the |
@sergeiandreyev cool! Do you have a rough timeline for the remaining cells? Do you have an existing GH issue to track the implementation of these cells? Then I could link this and one other issue to the implementation one. |
unfortunately, we don't have dedicated resources for this task, so the timeline is rather hard to define.. |
after checking this internally, the feedback is that we have a new |
Excellent, good to hear! @sergeiandreyev Do you have a timeline for the bundle (doc, model, pcell)? |
around 6 month.. |
for now putting the list of 2nd priority/phase devices here..
for some of these devices there is still ongoing discussion |
because You allready give us the measurements of different pnpMPAs, it would be nice, You also give the test-chip-layouts as |
im also interested in the SVaricap. is there more information about what it can and how to use? |
For CMOS-only designs, an NPN or PNP (either lateral or vertical) would be needed for bandgaps and similar uses.
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