NOTES

# General Notes About These Labs

WIP:
  - lab 5 for sky130:
    - Verilog assignment requires dual-ported SRAMs, which we don't have with Sram22
    - DRC section needs to be for klayout (we can't use sky130 Calibre decks bc they are NDA'ed)
    - unclear how to teach LVS, netgen doesn't work well (it just dumps a text file...)
  - project for sky130:
    - does the project need dual-ported SRAMs for the cache? i.e. will single-ported make things much more difficult?


Other:
- update CAD tool versions to latest? maybe not because there's only Innovus 191 on inst servers
- don't create a new lab repo per semester, just create tagged branches for each semester
- there is lots of non-tech related info in the asap7/sky130.yml files...is it worth it to decouple these in a tools.yml, or will this further confuse students?
- in general there are tons of repeated files. so make sure to copy any changes to all correct locations

- there are ` <!---tech-->` identifiers in the README.md lab specs that indicates a line has tech-specific info. When you diff 
  the lab specs (`diff asap7/README.md sky130/README.md`), the only differences should have the ` <!---tech-->` identifier,
  or be part of a code block with this identifier right below the code block. We can "sync" changes between lab specs this way.


- should we symlink all identical files? e.g.:
    - tech.yml files to a central location, since for labs 2-5 they're identical
    - verilog src files
- should we put all YAML config files into a configs/ directory, so it de-clutters the main lab folder? again, this might backfire and further confuse studentss
- these labs are in desperate need of an accompanying set of instruction slides
- ideally we create a lab6 with some of the DRC/LVS content from lab 5 but get students to practice fixing the errors
- remove unnecessary stuff from Makefile?
- in lab4 makefile, sim-gl-par gets removed as a dependency of sim-to-power. I'm assuming dependencies were being accidentally rebuilt so a TA removed this, but needs to be tested.
    $(INPUT_PWR_SIM_GL_DB) sim-to-power: $(HAMMER_D_MK) sim-gl-par