.gitignore

*~
*.nm
*.elf
*.hex
*.itb
*.map
*.o
*.objdump
*.readelf
*.gtkw
*.vcd
*.vsif
*.sve
*.sdb
test_build
dsim.env
dsim.log
dsim_results
metrics.db
metrics_history.db
xrun_results
vsim_results
vmgr_sessions
__pycache__
*.swp
/.cproject
/.project
.dvt/
dvt_build.log
xrun.history
xrun.log
xcelium.d/
waves.shm/
*.log
stdout.txt
.vscode
cva6/tests/riscv-compliance/
cva6/tests/riscv-tests/
cva6/sim/dv/
cva6/sim/vcs_results
cva6/sim/verilator_work
cva6/sim/out_*
cva6/sim/Mem_init.txt
cva6/sim/trace*
cva6/sim/simv*
cva6/sim/ucli.key
cva6/sim/.inter*
cva6/sim/.vcs*
cva6/sim/inter*
cva6/sim/novas*
cva6/sim/verdiLog
cva6/sim/Verdi.ses*
riviera_results/
*/vendor_lib/dpi_dasm_spike/
*/vendor_lib/verilab/svlib/
work*
vsim.dbg
*.wlf
transcript
.lib-rtl
.opt-rtl
tools/spike
tools/verilator*